2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
39 amdgpu_mn_unregister(robj);
40 amdgpu_bo_unref(&robj);
44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
45 int alignment, u32 initial_domain,
46 u64 flags, bool kernel,
47 struct drm_gem_object **obj)
49 struct amdgpu_bo *robj;
50 unsigned long max_size;
54 /* At least align on page size */
55 if (alignment < PAGE_SIZE) {
56 alignment = PAGE_SIZE;
59 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
60 /* Maximum bo size is the unpinned gtt size since we use the gtt to
61 * handle vram to system pool migrations.
63 max_size = adev->mc.gtt_size - adev->gart_pin_size;
64 if (size > max_size) {
65 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
66 size >> 20, max_size >> 20);
71 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
72 flags, NULL, NULL, &robj);
74 if (r != -ERESTARTSYS) {
75 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
76 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
79 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
80 size, initial_domain, alignment, r);
84 *obj = &robj->gem_base;
89 void amdgpu_gem_force_release(struct amdgpu_device *adev)
91 struct drm_device *ddev = adev->ddev;
92 struct drm_file *file;
94 mutex_lock(&ddev->filelist_mutex);
96 list_for_each_entry(file, &ddev->filelist, lhead) {
97 struct drm_gem_object *gobj;
100 WARN_ONCE(1, "Still active user space clients!\n");
101 spin_lock(&file->table_lock);
102 idr_for_each_entry(&file->object_idr, gobj, handle) {
103 WARN_ONCE(1, "And also active allocations!\n");
104 drm_gem_object_unreference_unlocked(gobj);
106 idr_destroy(&file->object_idr);
107 spin_unlock(&file->table_lock);
110 mutex_unlock(&ddev->filelist_mutex);
114 * Call from drm_gem_handle_create which appear in both new and open ioctl
117 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
119 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
120 struct amdgpu_device *adev = abo->adev;
121 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
122 struct amdgpu_vm *vm = &fpriv->vm;
123 struct amdgpu_bo_va *bo_va;
125 r = amdgpu_bo_reserve(abo, false);
129 bo_va = amdgpu_vm_bo_find(vm, abo);
131 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
135 amdgpu_bo_unreserve(abo);
139 void amdgpu_gem_object_close(struct drm_gem_object *obj,
140 struct drm_file *file_priv)
142 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
143 struct amdgpu_device *adev = bo->adev;
144 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
145 struct amdgpu_vm *vm = &fpriv->vm;
147 struct amdgpu_bo_list_entry vm_pd;
148 struct list_head list, duplicates;
149 struct ttm_validate_buffer tv;
150 struct ww_acquire_ctx ticket;
151 struct amdgpu_bo_va *bo_va;
154 INIT_LIST_HEAD(&list);
155 INIT_LIST_HEAD(&duplicates);
159 list_add(&tv.head, &list);
161 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
163 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
165 dev_err(adev->dev, "leaking bo va because "
166 "we fail to reserve bo (%d)\n", r);
169 bo_va = amdgpu_vm_bo_find(vm, bo);
171 if (--bo_va->ref_count == 0) {
172 amdgpu_vm_bo_rmv(adev, bo_va);
175 ttm_eu_backoff_reservation(&ticket, &list);
178 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
181 r = amdgpu_gpu_reset(adev);
191 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *filp)
194 struct amdgpu_device *adev = dev->dev_private;
195 union drm_amdgpu_gem_create *args = data;
196 uint64_t size = args->in.bo_size;
197 struct drm_gem_object *gobj;
202 /* create a gem object to contain this object in */
203 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
204 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
206 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
207 size = size << AMDGPU_GDS_SHIFT;
208 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
209 size = size << AMDGPU_GWS_SHIFT;
210 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
211 size = size << AMDGPU_OA_SHIFT;
217 size = roundup(size, PAGE_SIZE);
219 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
220 (u32)(0xffffffff & args->in.domains),
221 args->in.domain_flags,
226 r = drm_gem_handle_create(filp, gobj, &handle);
227 /* drop reference from allocate - handle holds it now */
228 drm_gem_object_unreference_unlocked(gobj);
232 memset(args, 0, sizeof(*args));
233 args->out.handle = handle;
237 r = amdgpu_gem_handle_lockup(adev, r);
241 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
242 struct drm_file *filp)
244 struct amdgpu_device *adev = dev->dev_private;
245 struct drm_amdgpu_gem_userptr *args = data;
246 struct drm_gem_object *gobj;
247 struct amdgpu_bo *bo;
251 if (offset_in_page(args->addr | args->size))
254 /* reject unknown flag values */
255 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
256 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
257 AMDGPU_GEM_USERPTR_REGISTER))
260 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
261 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
263 /* if we want to write to it we must install a MMU notifier */
267 /* create a gem object to contain this object in */
268 r = amdgpu_gem_object_create(adev, args->size, 0,
269 AMDGPU_GEM_DOMAIN_CPU, 0,
274 bo = gem_to_amdgpu_bo(gobj);
275 bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
276 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
277 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
281 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
282 r = amdgpu_mn_register(bo, args->addr);
287 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
288 down_read(¤t->mm->mmap_sem);
290 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
293 goto unlock_mmap_sem;
295 r = amdgpu_bo_reserve(bo, true);
299 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
300 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
301 amdgpu_bo_unreserve(bo);
305 up_read(¤t->mm->mmap_sem);
308 r = drm_gem_handle_create(filp, gobj, &handle);
309 /* drop reference from allocate - handle holds it now */
310 drm_gem_object_unreference_unlocked(gobj);
314 args->handle = handle;
318 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
321 up_read(¤t->mm->mmap_sem);
324 drm_gem_object_unreference_unlocked(gobj);
327 r = amdgpu_gem_handle_lockup(adev, r);
332 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
333 struct drm_device *dev,
334 uint32_t handle, uint64_t *offset_p)
336 struct drm_gem_object *gobj;
337 struct amdgpu_bo *robj;
339 gobj = drm_gem_object_lookup(filp, handle);
343 robj = gem_to_amdgpu_bo(gobj);
344 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
345 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
346 drm_gem_object_unreference_unlocked(gobj);
349 *offset_p = amdgpu_bo_mmap_offset(robj);
350 drm_gem_object_unreference_unlocked(gobj);
354 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
355 struct drm_file *filp)
357 union drm_amdgpu_gem_mmap *args = data;
358 uint32_t handle = args->in.handle;
359 memset(args, 0, sizeof(*args));
360 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
364 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
366 * @timeout_ns: timeout in ns
368 * Calculate the timeout in jiffies from an absolute timeout in ns.
370 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
372 unsigned long timeout_jiffies;
375 /* clamp timeout if it's to large */
376 if (((int64_t)timeout_ns) < 0)
377 return MAX_SCHEDULE_TIMEOUT;
379 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
380 if (ktime_to_ns(timeout) < 0)
383 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
384 /* clamp timeout to avoid unsigned-> signed overflow */
385 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
386 return MAX_SCHEDULE_TIMEOUT - 1;
388 return timeout_jiffies;
391 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
392 struct drm_file *filp)
394 struct amdgpu_device *adev = dev->dev_private;
395 union drm_amdgpu_gem_wait_idle *args = data;
396 struct drm_gem_object *gobj;
397 struct amdgpu_bo *robj;
398 uint32_t handle = args->in.handle;
399 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
403 gobj = drm_gem_object_lookup(filp, handle);
407 robj = gem_to_amdgpu_bo(gobj);
409 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
411 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
413 /* ret == 0 means not signaled,
414 * ret > 0 means signaled
415 * ret < 0 means interrupted before timeout
418 memset(args, 0, sizeof(*args));
419 args->out.status = (ret == 0);
423 drm_gem_object_unreference_unlocked(gobj);
424 r = amdgpu_gem_handle_lockup(adev, r);
428 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
429 struct drm_file *filp)
431 struct drm_amdgpu_gem_metadata *args = data;
432 struct drm_gem_object *gobj;
433 struct amdgpu_bo *robj;
436 DRM_DEBUG("%d \n", args->handle);
437 gobj = drm_gem_object_lookup(filp, args->handle);
440 robj = gem_to_amdgpu_bo(gobj);
442 r = amdgpu_bo_reserve(robj, false);
443 if (unlikely(r != 0))
446 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
447 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
448 r = amdgpu_bo_get_metadata(robj, args->data.data,
449 sizeof(args->data.data),
450 &args->data.data_size_bytes,
452 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
453 if (args->data.data_size_bytes > sizeof(args->data.data)) {
457 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
459 r = amdgpu_bo_set_metadata(robj, args->data.data,
460 args->data.data_size_bytes,
465 amdgpu_bo_unreserve(robj);
467 drm_gem_object_unreference_unlocked(gobj);
472 * amdgpu_gem_va_update_vm -update the bo_va in its VM
474 * @adev: amdgpu_device pointer
475 * @bo_va: bo_va to update
477 * Update the bo_va directly after setting it's address. Errors are not
478 * vital here, so they are not reported back to userspace.
480 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
481 struct amdgpu_bo_va *bo_va, uint32_t operation)
483 struct ttm_validate_buffer tv, *entry;
484 struct amdgpu_bo_list_entry vm_pd;
485 struct ww_acquire_ctx ticket;
486 struct list_head list, duplicates;
490 INIT_LIST_HEAD(&list);
491 INIT_LIST_HEAD(&duplicates);
493 tv.bo = &bo_va->bo->tbo;
495 list_add(&tv.head, &list);
497 amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
499 /* Provide duplicates to avoid -EALREADY */
500 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
504 amdgpu_vm_get_pt_bos(adev, bo_va->vm, &duplicates);
505 list_for_each_entry(entry, &list, head) {
506 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
507 /* if anything is swapped out don't swap it in here,
508 just abort and wait for the next CS */
509 if (domain == AMDGPU_GEM_DOMAIN_CPU)
510 goto error_unreserve;
512 list_for_each_entry(entry, &duplicates, head) {
513 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
514 /* if anything is swapped out don't swap it in here,
515 just abort and wait for the next CS */
516 if (domain == AMDGPU_GEM_DOMAIN_CPU)
517 goto error_unreserve;
520 r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
522 goto error_unreserve;
524 r = amdgpu_vm_clear_freed(adev, bo_va->vm);
526 goto error_unreserve;
528 if (operation == AMDGPU_VA_OP_MAP)
529 r = amdgpu_vm_bo_update(adev, bo_va, false);
532 ttm_eu_backoff_reservation(&ticket, &list);
535 if (r && r != -ERESTARTSYS)
536 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
541 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
542 struct drm_file *filp)
544 struct drm_amdgpu_gem_va *args = data;
545 struct drm_gem_object *gobj;
546 struct amdgpu_device *adev = dev->dev_private;
547 struct amdgpu_fpriv *fpriv = filp->driver_priv;
548 struct amdgpu_bo *abo;
549 struct amdgpu_bo_va *bo_va;
550 struct ttm_validate_buffer tv, tv_pd;
551 struct ww_acquire_ctx ticket;
552 struct list_head list, duplicates;
553 uint32_t invalid_flags, va_flags = 0;
556 if (!adev->vm_manager.enabled)
559 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
560 dev_err(&dev->pdev->dev,
561 "va_address 0x%lX is in reserved area 0x%X\n",
562 (unsigned long)args->va_address,
563 AMDGPU_VA_RESERVED_SIZE);
567 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
568 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
569 if ((args->flags & invalid_flags)) {
570 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
571 args->flags, invalid_flags);
575 switch (args->operation) {
576 case AMDGPU_VA_OP_MAP:
577 case AMDGPU_VA_OP_UNMAP:
580 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
585 gobj = drm_gem_object_lookup(filp, args->handle);
588 abo = gem_to_amdgpu_bo(gobj);
589 INIT_LIST_HEAD(&list);
590 INIT_LIST_HEAD(&duplicates);
593 list_add(&tv.head, &list);
595 tv_pd.bo = &fpriv->vm.page_directory->tbo;
597 list_add(&tv_pd.head, &list);
599 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
601 drm_gem_object_unreference_unlocked(gobj);
605 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
607 ttm_eu_backoff_reservation(&ticket, &list);
608 drm_gem_object_unreference_unlocked(gobj);
612 switch (args->operation) {
613 case AMDGPU_VA_OP_MAP:
614 if (args->flags & AMDGPU_VM_PAGE_READABLE)
615 va_flags |= AMDGPU_PTE_READABLE;
616 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
617 va_flags |= AMDGPU_PTE_WRITEABLE;
618 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
619 va_flags |= AMDGPU_PTE_EXECUTABLE;
620 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
621 args->offset_in_bo, args->map_size,
624 case AMDGPU_VA_OP_UNMAP:
625 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
630 ttm_eu_backoff_reservation(&ticket, &list);
631 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
633 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
635 drm_gem_object_unreference_unlocked(gobj);
639 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *filp)
642 struct drm_amdgpu_gem_op *args = data;
643 struct drm_gem_object *gobj;
644 struct amdgpu_bo *robj;
647 gobj = drm_gem_object_lookup(filp, args->handle);
651 robj = gem_to_amdgpu_bo(gobj);
653 r = amdgpu_bo_reserve(robj, false);
658 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
659 struct drm_amdgpu_gem_create_in info;
660 void __user *out = (void __user *)(long)args->value;
662 info.bo_size = robj->gem_base.size;
663 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
664 info.domains = robj->prefered_domains;
665 info.domain_flags = robj->flags;
666 amdgpu_bo_unreserve(robj);
667 if (copy_to_user(out, &info, sizeof(info)))
671 case AMDGPU_GEM_OP_SET_PLACEMENT:
672 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
674 amdgpu_bo_unreserve(robj);
677 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
678 AMDGPU_GEM_DOMAIN_GTT |
679 AMDGPU_GEM_DOMAIN_CPU);
680 robj->allowed_domains = robj->prefered_domains;
681 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
682 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
684 amdgpu_bo_unreserve(robj);
687 amdgpu_bo_unreserve(robj);
692 drm_gem_object_unreference_unlocked(gobj);
696 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
697 struct drm_device *dev,
698 struct drm_mode_create_dumb *args)
700 struct amdgpu_device *adev = dev->dev_private;
701 struct drm_gem_object *gobj;
705 args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
706 args->size = (u64)args->pitch * args->height;
707 args->size = ALIGN(args->size, PAGE_SIZE);
709 r = amdgpu_gem_object_create(adev, args->size, 0,
710 AMDGPU_GEM_DOMAIN_VRAM,
711 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
717 r = drm_gem_handle_create(file_priv, gobj, &handle);
718 /* drop reference from allocate - handle holds it now */
719 drm_gem_object_unreference_unlocked(gobj);
723 args->handle = handle;
727 #if defined(CONFIG_DEBUG_FS)
728 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
730 struct drm_gem_object *gobj = ptr;
731 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
732 struct seq_file *m = data;
735 const char *placement;
738 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
740 case AMDGPU_GEM_DOMAIN_VRAM:
743 case AMDGPU_GEM_DOMAIN_GTT:
746 case AMDGPU_GEM_DOMAIN_CPU:
751 seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
752 id, amdgpu_bo_size(bo), placement,
753 amdgpu_bo_gpu_offset(bo));
755 pin_count = ACCESS_ONCE(bo->pin_count);
757 seq_printf(m, " pin count %d", pin_count);
763 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
765 struct drm_info_node *node = (struct drm_info_node *)m->private;
766 struct drm_device *dev = node->minor->dev;
767 struct drm_file *file;
770 r = mutex_lock_interruptible(&dev->filelist_mutex);
774 list_for_each_entry(file, &dev->filelist, lhead) {
775 struct task_struct *task;
778 * Although we have a valid reference on file->pid, that does
779 * not guarantee that the task_struct who called get_pid() is
780 * still alive (e.g. get_pid(current) => fork() => exit()).
781 * Therefore, we need to protect this ->comm access using RCU.
784 task = pid_task(file->pid, PIDTYPE_PID);
785 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
786 task ? task->comm : "<unknown>");
789 spin_lock(&file->table_lock);
790 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
791 spin_unlock(&file->table_lock);
794 mutex_unlock(&dev->filelist_mutex);
798 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
799 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
803 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
805 #if defined(CONFIG_DEBUG_FS)
806 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);