drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/pagemap.h>
  30 #include <drm/drmP.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu.h"
  33
  34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  35 {
  36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  37
  38         if (robj) {
  39                 amdgpu_mn_unregister(robj);
  40                 amdgpu_bo_unref(&robj);
  41         }
  42 }
  43
  44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  45                                 int alignment, u32 initial_domain,
  46                                 u64 flags, bool kernel,
  47                                 struct drm_gem_object **obj)
  48 {
  49         struct amdgpu_bo *robj;
  50         int r;
  51
  52         *obj = NULL;
  53         /* At least align on page size */
  54         if (alignment < PAGE_SIZE) {
  55                 alignment = PAGE_SIZE;
  56         }
  57
  58 retry:
  59         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
  60                              flags, NULL, NULL, 0, &robj);
  61         if (r) {
  62                 if (r != -ERESTARTSYS) {
  63                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
  64                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
  65                                 goto retry;
  66                         }
  67                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  68                                   size, initial_domain, alignment, r);
  69                 }
  70                 return r;
  71         }
  72         *obj = &robj->gem_base;
  73
  74         return 0;
  75 }
  76
  77 void amdgpu_gem_force_release(struct amdgpu_device *adev)
  78 {
  79         struct drm_device *ddev = adev->ddev;
  80         struct drm_file *file;
  81
  82         mutex_lock(&ddev->filelist_mutex);
  83
  84         list_for_each_entry(file, &ddev->filelist, lhead) {
  85                 struct drm_gem_object *gobj;
  86                 int handle;
  87
  88                 WARN_ONCE(1, "Still active user space clients!\n");
  89                 spin_lock(&file->table_lock);
  90                 idr_for_each_entry(&file->object_idr, gobj, handle) {
  91                         WARN_ONCE(1, "And also active allocations!\n");
  92                         drm_gem_object_put_unlocked(gobj);
  93                 }
  94                 idr_destroy(&file->object_idr);
  95                 spin_unlock(&file->table_lock);
  96         }
  97
  98         mutex_unlock(&ddev->filelist_mutex);
  99 }
 100
 101 /*
 102  * Call from drm_gem_handle_create which appear in both new and open ioctl
 103  * case.
 104  */
 105 int amdgpu_gem_object_open(struct drm_gem_object *obj,
 106                            struct drm_file *file_priv)
 107 {
 108         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 109         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 110         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 111         struct amdgpu_vm *vm = &fpriv->vm;
 112         struct amdgpu_bo_va *bo_va;
 113         int r;
 114         r = amdgpu_bo_reserve(abo, false);
 115         if (r)
 116                 return r;
 117
 118         bo_va = amdgpu_vm_bo_find(vm, abo);
 119         if (!bo_va) {
 120                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 121         } else {
 122                 ++bo_va->ref_count;
 123         }
 124         amdgpu_bo_unreserve(abo);
 125         return 0;
 126 }
 127
 128 static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
 129 {
 130         /* if anything is swapped out don't swap it in here,
 131            just abort and wait for the next CS */
 132         if (!amdgpu_bo_gpu_accessible(bo))
 133                 return -ERESTARTSYS;
 134
 135         if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
 136                 return -ERESTARTSYS;
 137
 138         return 0;
 139 }
 140
 141 static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
 142                                 struct amdgpu_vm *vm,
 143                                 struct list_head *list)
 144 {
 145         struct ttm_validate_buffer *entry;
 146
 147         list_for_each_entry(entry, list, head) {
 148                 struct amdgpu_bo *bo =
 149                         container_of(entry->bo, struct amdgpu_bo, tbo);
 150                 if (amdgpu_gem_vm_check(NULL, bo))
 151                         return false;
 152         }
 153
 154         return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
 155 }
 156
 157 void amdgpu_gem_object_close(struct drm_gem_object *obj,
 158                              struct drm_file *file_priv)
 159 {
 160         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 161         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 162         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 163         struct amdgpu_vm *vm = &fpriv->vm;
 164
 165         struct amdgpu_bo_list_entry vm_pd;
 166         struct list_head list;
 167         struct ttm_validate_buffer tv;
 168         struct ww_acquire_ctx ticket;
 169         struct amdgpu_bo_va *bo_va;
 170         int r;
 171
 172         INIT_LIST_HEAD(&list);
 173
 174         tv.bo = &bo->tbo;
 175         tv.shared = true;
 176         list_add(&tv.head, &list);
 177
 178         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 179
 180         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
 181         if (r) {
 182                 dev_err(adev->dev, "leaking bo va because "
 183                         "we fail to reserve bo (%d)\n", r);
 184                 return;
 185         }
 186         bo_va = amdgpu_vm_bo_find(vm, bo);
 187         if (bo_va && --bo_va->ref_count == 0) {
 188                 amdgpu_vm_bo_rmv(adev, bo_va);
 189
 190                 if (amdgpu_gem_vm_ready(adev, vm, &list)) {
 191                         struct dma_fence *fence = NULL;
 192
 193                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 194                         if (unlikely(r)) {
 195                                 dev_err(adev->dev, "failed to clear page "
 196                                         "tables on GEM object close (%d)\n", r);
 197                         }
 198
 199                         if (fence) {
 200                                 amdgpu_bo_fence(bo, fence, true);
 201                                 dma_fence_put(fence);
 202                         }
 203                 }
 204         }
 205         ttm_eu_backoff_reservation(&ticket, &list);
 206 }
 207
 208 /*
 209  * GEM ioctls.
 210  */
 211 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 212                             struct drm_file *filp)
 213 {
 214         struct amdgpu_device *adev = dev->dev_private;
 215         union drm_amdgpu_gem_create *args = data;
 216         uint64_t size = args->in.bo_size;
 217         struct drm_gem_object *gobj;
 218         uint32_t handle;
 219         bool kernel = false;
 220         int r;
 221
 222         /* reject invalid gem flags */
 223         if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 224                                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 225                                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 226                                       AMDGPU_GEM_CREATE_VRAM_CLEARED))
 227                 return -EINVAL;
 228
 229         /* reject invalid gem domains */
 230         if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
 231                                  AMDGPU_GEM_DOMAIN_GTT |
 232                                  AMDGPU_GEM_DOMAIN_VRAM |
 233                                  AMDGPU_GEM_DOMAIN_GDS |
 234                                  AMDGPU_GEM_DOMAIN_GWS |
 235                                  AMDGPU_GEM_DOMAIN_OA))
 236                 return -EINVAL;
 237
 238         /* create a gem object to contain this object in */
 239         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 240             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 241                 kernel = true;
 242                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
 243                         size = size << AMDGPU_GDS_SHIFT;
 244                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
 245                         size = size << AMDGPU_GWS_SHIFT;
 246                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
 247                         size = size << AMDGPU_OA_SHIFT;
 248                 else
 249                         return -EINVAL;
 250         }
 251         size = roundup(size, PAGE_SIZE);
 252
 253         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 254                                      (u32)(0xffffffff & args->in.domains),
 255                                      args->in.domain_flags,
 256                                      kernel, &gobj);
 257         if (r)
 258                 return r;
 259
 260         r = drm_gem_handle_create(filp, gobj, &handle);
 261         /* drop reference from allocate - handle holds it now */
 262         drm_gem_object_put_unlocked(gobj);
 263         if (r)
 264                 return r;
 265
 266         memset(args, 0, sizeof(*args));
 267         args->out.handle = handle;
 268         return 0;
 269 }
 270
 271 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 272                              struct drm_file *filp)
 273 {
 274         struct amdgpu_device *adev = dev->dev_private;
 275         struct drm_amdgpu_gem_userptr *args = data;
 276         struct drm_gem_object *gobj;
 277         struct amdgpu_bo *bo;
 278         uint32_t handle;
 279         int r;
 280
 281         if (offset_in_page(args->addr | args->size))
 282                 return -EINVAL;
 283
 284         /* reject unknown flag values */
 285         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 286             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 287             AMDGPU_GEM_USERPTR_REGISTER))
 288                 return -EINVAL;
 289
 290         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 291              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 292
 293                 /* if we want to write to it we must install a MMU notifier */
 294                 return -EACCES;
 295         }
 296
 297         /* create a gem object to contain this object in */
 298         r = amdgpu_gem_object_create(adev, args->size, 0,
 299                                      AMDGPU_GEM_DOMAIN_CPU, 0,
 300                                      0, &gobj);
 301         if (r)
 302                 return r;
 303
 304         bo = gem_to_amdgpu_bo(gobj);
 305         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 306         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 307         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
 308         if (r)
 309                 goto release_object;
 310
 311         r = amdgpu_mn_register(bo, args->addr);
 312         if (r)
 313                 goto release_object;
 314
 315         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 316                 down_read(&current->mm->mmap_sem);
 317
 318                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
 319                                                  bo->tbo.ttm->pages);
 320                 if (r)
 321                         goto unlock_mmap_sem;
 322
 323                 r = amdgpu_bo_reserve(bo, true);
 324                 if (r)
 325                         goto free_pages;
 326
 327                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 328                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 329                 amdgpu_bo_unreserve(bo);
 330                 if (r)
 331                         goto free_pages;
 332
 333                 up_read(&current->mm->mmap_sem);
 334         }
 335
 336         r = drm_gem_handle_create(filp, gobj, &handle);
 337         /* drop reference from allocate - handle holds it now */
 338         drm_gem_object_put_unlocked(gobj);
 339         if (r)
 340                 return r;
 341
 342         args->handle = handle;
 343         return 0;
 344
 345 free_pages:
 346         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
 347
 348 unlock_mmap_sem:
 349         up_read(&current->mm->mmap_sem);
 350
 351 release_object:
 352         drm_gem_object_put_unlocked(gobj);
 353
 354         return r;
 355 }
 356
 357 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 358                           struct drm_device *dev,
 359                           uint32_t handle, uint64_t *offset_p)
 360 {
 361         struct drm_gem_object *gobj;
 362         struct amdgpu_bo *robj;
 363
 364         gobj = drm_gem_object_lookup(filp, handle);
 365         if (gobj == NULL) {
 366                 return -ENOENT;
 367         }
 368         robj = gem_to_amdgpu_bo(gobj);
 369         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 370             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 371                 drm_gem_object_put_unlocked(gobj);
 372                 return -EPERM;
 373         }
 374         *offset_p = amdgpu_bo_mmap_offset(robj);
 375         drm_gem_object_put_unlocked(gobj);
 376         return 0;
 377 }
 378
 379 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 380                           struct drm_file *filp)
 381 {
 382         union drm_amdgpu_gem_mmap *args = data;
 383         uint32_t handle = args->in.handle;
 384         memset(args, 0, sizeof(*args));
 385         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 386 }
 387
 388 /**
 389  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 390  *
 391  * @timeout_ns: timeout in ns
 392  *
 393  * Calculate the timeout in jiffies from an absolute timeout in ns.
 394  */
 395 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 396 {
 397         unsigned long timeout_jiffies;
 398         ktime_t timeout;
 399
 400         /* clamp timeout if it's to large */
 401         if (((int64_t)timeout_ns) < 0)
 402                 return MAX_SCHEDULE_TIMEOUT;
 403
 404         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 405         if (ktime_to_ns(timeout) < 0)
 406                 return 0;
 407
 408         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 409         /*  clamp timeout to avoid unsigned-> signed overflow */
 410         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
 411                 return MAX_SCHEDULE_TIMEOUT - 1;
 412
 413         return timeout_jiffies;
 414 }
 415
 416 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 417                               struct drm_file *filp)
 418 {
 419         union drm_amdgpu_gem_wait_idle *args = data;
 420         struct drm_gem_object *gobj;
 421         struct amdgpu_bo *robj;
 422         uint32_t handle = args->in.handle;
 423         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 424         int r = 0;
 425         long ret;
 426
 427         gobj = drm_gem_object_lookup(filp, handle);
 428         if (gobj == NULL) {
 429                 return -ENOENT;
 430         }
 431         robj = gem_to_amdgpu_bo(gobj);
 432         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
 433                                                   timeout);
 434
 435         /* ret == 0 means not signaled,
 436          * ret > 0 means signaled
 437          * ret < 0 means interrupted before timeout
 438          */
 439         if (ret >= 0) {
 440                 memset(args, 0, sizeof(*args));
 441                 args->out.status = (ret == 0);
 442         } else
 443                 r = ret;
 444
 445         drm_gem_object_put_unlocked(gobj);
 446         return r;
 447 }
 448
 449 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 450                                 struct drm_file *filp)
 451 {
 452         struct drm_amdgpu_gem_metadata *args = data;
 453         struct drm_gem_object *gobj;
 454         struct amdgpu_bo *robj;
 455         int r = -1;
 456
 457         DRM_DEBUG("%d \n", args->handle);
 458         gobj = drm_gem_object_lookup(filp, args->handle);
 459         if (gobj == NULL)
 460                 return -ENOENT;
 461         robj = gem_to_amdgpu_bo(gobj);
 462
 463         r = amdgpu_bo_reserve(robj, false);
 464         if (unlikely(r != 0))
 465                 goto out;
 466
 467         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 468                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 469                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 470                                            sizeof(args->data.data),
 471                                            &args->data.data_size_bytes,
 472                                            &args->data.flags);
 473         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 474                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 475                         r = -EINVAL;
 476                         goto unreserve;
 477                 }
 478                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 479                 if (!r)
 480                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 481                                                    args->data.data_size_bytes,
 482                                                    args->data.flags);
 483         }
 484
 485 unreserve:
 486         amdgpu_bo_unreserve(robj);
 487 out:
 488         drm_gem_object_put_unlocked(gobj);
 489         return r;
 490 }
 491
 492 /**
 493  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 494  *
 495  * @adev: amdgpu_device pointer
 496  * @vm: vm to update
 497  * @bo_va: bo_va to update
 498  * @list: validation list
 499  * @operation: map, unmap or clear
 500  *
 501  * Update the bo_va directly after setting its address. Errors are not
 502  * vital here, so they are not reported back to userspace.
 503  */
 504 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 505                                     struct amdgpu_vm *vm,
 506                                     struct amdgpu_bo_va *bo_va,
 507                                     struct list_head *list,
 508                                     uint32_t operation)
 509 {
 510         int r = -ERESTARTSYS;
 511
 512         if (!amdgpu_gem_vm_ready(adev, vm, list))
 513                 goto error;
 514
 515         r = amdgpu_vm_update_directories(adev, vm);
 516         if (r)
 517                 goto error;
 518
 519         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 520         if (r)
 521                 goto error;
 522
 523         if (operation == AMDGPU_VA_OP_MAP ||
 524             operation == AMDGPU_VA_OP_REPLACE)
 525                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 526
 527 error:
 528         if (r && r != -ERESTARTSYS)
 529                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 530 }
 531
 532 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 533                           struct drm_file *filp)
 534 {
 535         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 536                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 537                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
 538         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 539                 AMDGPU_VM_PAGE_PRT;
 540
 541         struct drm_amdgpu_gem_va *args = data;
 542         struct drm_gem_object *gobj;
 543         struct amdgpu_device *adev = dev->dev_private;
 544         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 545         struct amdgpu_bo *abo;
 546         struct amdgpu_bo_va *bo_va;
 547         struct amdgpu_bo_list_entry vm_pd;
 548         struct ttm_validate_buffer tv;
 549         struct ww_acquire_ctx ticket;
 550         struct list_head list;
 551         uint64_t va_flags;
 552         uint64_t vm_size;
 553         int r = 0;
 554
 555         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
 556                 dev_err(&dev->pdev->dev,
 557                         "va_address 0x%lX is in reserved area 0x%X\n",
 558                         (unsigned long)args->va_address,
 559                         AMDGPU_VA_RESERVED_SIZE);
 560                 return -EINVAL;
 561         }
 562
 563         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 564         vm_size -= AMDGPU_VA_RESERVED_SIZE;
 565         if (args->va_address + args->map_size > vm_size) {
 566                 dev_dbg(&dev->pdev->dev,
 567                         "va_address 0x%llx is in top reserved area 0x%llx\n",
 568                         args->va_address + args->map_size, vm_size);
 569                 return -EINVAL;
 570         }
 571
 572         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 573                 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
 574                         args->flags);
 575                 return -EINVAL;
 576         }
 577
 578         switch (args->operation) {
 579         case AMDGPU_VA_OP_MAP:
 580         case AMDGPU_VA_OP_UNMAP:
 581         case AMDGPU_VA_OP_CLEAR:
 582         case AMDGPU_VA_OP_REPLACE:
 583                 break;
 584         default:
 585                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
 586                         args->operation);
 587                 return -EINVAL;
 588         }
 589         if ((args->operation == AMDGPU_VA_OP_MAP) ||
 590             (args->operation == AMDGPU_VA_OP_REPLACE)) {
 591                 if (amdgpu_kms_vram_lost(adev, fpriv))
 592                         return -ENODEV;
 593         }
 594
 595         INIT_LIST_HEAD(&list);
 596         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 597             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 598                 gobj = drm_gem_object_lookup(filp, args->handle);
 599                 if (gobj == NULL)
 600                         return -ENOENT;
 601                 abo = gem_to_amdgpu_bo(gobj);
 602                 tv.bo = &abo->tbo;
 603                 tv.shared = false;
 604                 list_add(&tv.head, &list);
 605         } else {
 606                 gobj = NULL;
 607                 abo = NULL;
 608         }
 609
 610         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 611
 612         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
 613         if (r)
 614                 goto error_unref;
 615
 616         if (abo) {
 617                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 618                 if (!bo_va) {
 619                         r = -ENOENT;
 620                         goto error_backoff;
 621                 }
 622         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 623                 bo_va = fpriv->prt_va;
 624         } else {
 625                 bo_va = NULL;
 626         }
 627
 628         switch (args->operation) {
 629         case AMDGPU_VA_OP_MAP:
 630                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 631                                         args->map_size);
 632                 if (r)
 633                         goto error_backoff;
 634
 635                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 636                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 637                                      args->offset_in_bo, args->map_size,
 638                                      va_flags);
 639                 break;
 640         case AMDGPU_VA_OP_UNMAP:
 641                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 642                 break;
 643
 644         case AMDGPU_VA_OP_CLEAR:
 645                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 646                                                 args->va_address,
 647                                                 args->map_size);
 648                 break;
 649         case AMDGPU_VA_OP_REPLACE:
 650                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
 651                                         args->map_size);
 652                 if (r)
 653                         goto error_backoff;
 654
 655                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
 656                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 657                                              args->offset_in_bo, args->map_size,
 658                                              va_flags);
 659                 break;
 660         default:
 661                 break;
 662         }
 663         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 664                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
 665                                         args->operation);
 666
 667 error_backoff:
 668         ttm_eu_backoff_reservation(&ticket, &list);
 669
 670 error_unref:
 671         drm_gem_object_put_unlocked(gobj);
 672         return r;
 673 }
 674
 675 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 676                         struct drm_file *filp)
 677 {
 678         struct drm_amdgpu_gem_op *args = data;
 679         struct drm_gem_object *gobj;
 680         struct amdgpu_bo *robj;
 681         int r;
 682
 683         gobj = drm_gem_object_lookup(filp, args->handle);
 684         if (gobj == NULL) {
 685                 return -ENOENT;
 686         }
 687         robj = gem_to_amdgpu_bo(gobj);
 688
 689         r = amdgpu_bo_reserve(robj, false);
 690         if (unlikely(r))
 691                 goto out;
 692
 693         switch (args->op) {
 694         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 695                 struct drm_amdgpu_gem_create_in info;
 696                 void __user *out = u64_to_user_ptr(args->value);
 697
 698                 info.bo_size = robj->gem_base.size;
 699                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
 700                 info.domains = robj->preferred_domains;
 701                 info.domain_flags = robj->flags;
 702                 amdgpu_bo_unreserve(robj);
 703                 if (copy_to_user(out, &info, sizeof(info)))
 704                         r = -EFAULT;
 705                 break;
 706         }
 707         case AMDGPU_GEM_OP_SET_PLACEMENT:
 708                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
 709                         r = -EINVAL;
 710                         amdgpu_bo_unreserve(robj);
 711                         break;
 712                 }
 713                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 714                         r = -EPERM;
 715                         amdgpu_bo_unreserve(robj);
 716                         break;
 717                 }
 718                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 719                                                         AMDGPU_GEM_DOMAIN_GTT |
 720                                                         AMDGPU_GEM_DOMAIN_CPU);
 721                 robj->allowed_domains = robj->preferred_domains;
 722                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 723                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 724
 725                 amdgpu_bo_unreserve(robj);
 726                 break;
 727         default:
 728                 amdgpu_bo_unreserve(robj);
 729                 r = -EINVAL;
 730         }
 731
 732 out:
 733         drm_gem_object_put_unlocked(gobj);
 734         return r;
 735 }
 736
 737 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 738                             struct drm_device *dev,
 739                             struct drm_mode_create_dumb *args)
 740 {
 741         struct amdgpu_device *adev = dev->dev_private;
 742         struct drm_gem_object *gobj;
 743         uint32_t handle;
 744         int r;
 745
 746         args->pitch = amdgpu_align_pitch(adev, args->width,
 747                                          DIV_ROUND_UP(args->bpp, 8), 0);
 748         args->size = (u64)args->pitch * args->height;
 749         args->size = ALIGN(args->size, PAGE_SIZE);
 750
 751         r = amdgpu_gem_object_create(adev, args->size, 0,
 752                                      AMDGPU_GEM_DOMAIN_VRAM,
 753                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 754                                      ttm_bo_type_device,
 755                                      &gobj);
 756         if (r)
 757                 return -ENOMEM;
 758
 759         r = drm_gem_handle_create(file_priv, gobj, &handle);
 760         /* drop reference from allocate - handle holds it now */
 761         drm_gem_object_put_unlocked(gobj);
 762         if (r) {
 763                 return r;
 764         }
 765         args->handle = handle;
 766         return 0;
 767 }
 768
 769 #if defined(CONFIG_DEBUG_FS)
 770 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 771 {
 772         struct drm_gem_object *gobj = ptr;
 773         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
 774         struct seq_file *m = data;
 775
 776         unsigned domain;
 777         const char *placement;
 778         unsigned pin_count;
 779         uint64_t offset;
 780
 781         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 782         switch (domain) {
 783         case AMDGPU_GEM_DOMAIN_VRAM:
 784                 placement = "VRAM";
 785                 break;
 786         case AMDGPU_GEM_DOMAIN_GTT:
 787                 placement = " GTT";
 788                 break;
 789         case AMDGPU_GEM_DOMAIN_CPU:
 790         default:
 791                 placement = " CPU";
 792                 break;
 793         }
 794         seq_printf(m, "\t0x%08x: %12ld byte %s",
 795                    id, amdgpu_bo_size(bo), placement);
 796
 797         offset = ACCESS_ONCE(bo->tbo.mem.start);
 798         if (offset != AMDGPU_BO_INVALID_OFFSET)
 799                 seq_printf(m, " @ 0x%010Lx", offset);
 800
 801         pin_count = ACCESS_ONCE(bo->pin_count);
 802         if (pin_count)
 803                 seq_printf(m, " pin count %d", pin_count);
 804         seq_printf(m, "\n");
 805
 806         return 0;
 807 }
 808
 809 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 810 {
 811         struct drm_info_node *node = (struct drm_info_node *)m->private;
 812         struct drm_device *dev = node->minor->dev;
 813         struct drm_file *file;
 814         int r;
 815
 816         r = mutex_lock_interruptible(&dev->filelist_mutex);
 817         if (r)
 818                 return r;
 819
 820         list_for_each_entry(file, &dev->filelist, lhead) {
 821                 struct task_struct *task;
 822
 823                 /*
 824                  * Although we have a valid reference on file->pid, that does
 825                  * not guarantee that the task_struct who called get_pid() is
 826                  * still alive (e.g. get_pid(current) => fork() => exit()).
 827                  * Therefore, we need to protect this ->comm access using RCU.
 828                  */
 829                 rcu_read_lock();
 830                 task = pid_task(file->pid, PIDTYPE_PID);
 831                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
 832                            task ? task->comm : "<unknown>");
 833                 rcu_read_unlock();
 834
 835                 spin_lock(&file->table_lock);
 836                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
 837                 spin_unlock(&file->table_lock);
 838         }
 839
 840         mutex_unlock(&dev->filelist_mutex);
 841         return 0;
 842 }
 843
 844 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
 845         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
 846 };
 847 #endif
 848
 849 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
 850 {
 851 #if defined(CONFIG_DEBUG_FS)
 852         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
 853 #endif
 854         return 0;
 855 }