2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/slab.h>
36 #include <linux/firmware.h>
39 #include "amdgpu_trace.h"
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed.
51 struct dma_fence base;
54 struct amdgpu_ring *ring;
57 static struct kmem_cache *amdgpu_fence_slab;
59 int amdgpu_fence_slab_init(void)
61 amdgpu_fence_slab = kmem_cache_create(
62 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
63 SLAB_HWCACHE_ALIGN, NULL);
64 if (!amdgpu_fence_slab)
69 void amdgpu_fence_slab_fini(void)
72 kmem_cache_destroy(amdgpu_fence_slab);
77 static const struct dma_fence_ops amdgpu_fence_ops;
78 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
80 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
82 if (__f->base.ops == &amdgpu_fence_ops)
89 * amdgpu_fence_write - write a fence value
91 * @ring: ring the fence is associated with
92 * @seq: sequence number to write
94 * Writes a fence value to memory (all asics).
96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
98 struct amdgpu_fence_driver *drv = &ring->fence_drv;
101 *drv->cpu_addr = cpu_to_le32(seq);
105 * amdgpu_fence_read - read a fence value
107 * @ring: ring the fence is associated with
109 * Reads a fence value from memory (all asics).
110 * Returns the value of the fence read from memory.
112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
114 struct amdgpu_fence_driver *drv = &ring->fence_drv;
118 seq = le32_to_cpu(*drv->cpu_addr);
120 seq = atomic_read(&drv->last_seq);
126 * amdgpu_fence_emit - emit a fence on the requested ring
128 * @ring: ring the fence is associated with
129 * @f: resulting fence object
131 * Emits a fence command on the requested ring (all asics).
132 * Returns 0 on success, -ENOMEM on failure.
134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
137 struct amdgpu_device *adev = ring->adev;
138 struct amdgpu_fence *fence;
139 struct dma_fence __rcu **ptr;
143 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
147 seq = ++ring->fence_drv.sync_seq;
149 dma_fence_init(&fence->base, &amdgpu_fence_ops,
150 &ring->fence_drv.lock,
151 adev->fence_context + ring->idx,
153 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
154 seq, flags | AMDGPU_FENCE_FLAG_INT);
156 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
157 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
158 struct dma_fence *old;
161 old = dma_fence_get_rcu_safe(ptr);
165 r = dma_fence_wait(old, false);
172 /* This function can't be called concurrently anyway, otherwise
173 * emitting the fence would mess up the hardware ring buffer.
175 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
183 * amdgpu_fence_emit_polling - emit a fence on the requeste ring
185 * @ring: ring the fence is associated with
186 * @s: resulting sequence number
188 * Emits a fence command on the requested ring (all asics).
189 * Used For polling fence.
190 * Returns 0 on success, -ENOMEM on failure.
192 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
199 seq = ++ring->fence_drv.sync_seq;
200 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
209 * amdgpu_fence_schedule_fallback - schedule fallback check
211 * @ring: pointer to struct amdgpu_ring
213 * Start a timer as fallback to our interrupts.
215 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
217 mod_timer(&ring->fence_drv.fallback_timer,
218 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
222 * amdgpu_fence_process - check for fence activity
224 * @ring: pointer to struct amdgpu_ring
226 * Checks the current fence value and calculates the last
227 * signalled fence value. Wakes the fence queue if the
228 * sequence number has increased.
230 void amdgpu_fence_process(struct amdgpu_ring *ring)
232 struct amdgpu_fence_driver *drv = &ring->fence_drv;
233 uint32_t seq, last_seq;
237 last_seq = atomic_read(&ring->fence_drv.last_seq);
238 seq = amdgpu_fence_read(ring);
240 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
242 if (seq != ring->fence_drv.sync_seq)
243 amdgpu_fence_schedule_fallback(ring);
245 if (unlikely(seq == last_seq))
248 last_seq &= drv->num_fences_mask;
249 seq &= drv->num_fences_mask;
252 struct dma_fence *fence, **ptr;
255 last_seq &= drv->num_fences_mask;
256 ptr = &drv->fences[last_seq];
258 /* There is always exactly one thread signaling this fence slot */
259 fence = rcu_dereference_protected(*ptr, 1);
260 RCU_INIT_POINTER(*ptr, NULL);
265 r = dma_fence_signal(fence);
267 DMA_FENCE_TRACE(fence, "signaled from irq context\n");
271 dma_fence_put(fence);
272 } while (last_seq != seq);
276 * amdgpu_fence_fallback - fallback for hardware interrupts
278 * @work: delayed work item
280 * Checks for fence activity.
282 static void amdgpu_fence_fallback(struct timer_list *t)
284 struct amdgpu_ring *ring = from_timer(ring, t,
285 fence_drv.fallback_timer);
287 amdgpu_fence_process(ring);
291 * amdgpu_fence_wait_empty - wait for all fences to signal
293 * @adev: amdgpu device pointer
294 * @ring: ring index the fence is associated with
296 * Wait for all fences on the requested ring to signal (all asics).
297 * Returns 0 if the fences have passed, error for all other cases.
299 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
301 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
302 struct dma_fence *fence, **ptr;
308 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
310 fence = rcu_dereference(*ptr);
311 if (!fence || !dma_fence_get_rcu(fence)) {
317 r = dma_fence_wait(fence, false);
318 dma_fence_put(fence);
323 * amdgpu_fence_wait_polling - busy wait for givn sequence number
325 * @ring: ring index the fence is associated with
326 * @wait_seq: sequence number to wait
327 * @timeout: the timeout for waiting in usecs
329 * Wait for all fences on the requested ring to signal (all asics).
330 * Returns left time if no timeout, 0 or minus if timeout.
332 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
339 seq = amdgpu_fence_read(ring);
342 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
344 return timeout > 0 ? timeout : 0;
347 * amdgpu_fence_count_emitted - get the count of emitted fences
349 * @ring: ring the fence is associated with
351 * Get the number of fences emitted on the requested ring (all asics).
352 * Returns the number of emitted fences on the ring. Used by the
353 * dynpm code to ring track activity.
355 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
359 /* We are not protected by ring lock when reading the last sequence
360 * but it's ok to report slightly wrong fence count here.
362 amdgpu_fence_process(ring);
363 emitted = 0x100000000ull;
364 emitted -= atomic_read(&ring->fence_drv.last_seq);
365 emitted += READ_ONCE(ring->fence_drv.sync_seq);
366 return lower_32_bits(emitted);
370 * amdgpu_fence_driver_start_ring - make the fence driver
371 * ready for use on the requested ring.
373 * @ring: ring to start the fence driver on
374 * @irq_src: interrupt source to use for this ring
375 * @irq_type: interrupt type to use for this ring
377 * Make the fence driver ready for processing (all asics).
378 * Not all asics have all rings, so each asic will only
379 * start the fence driver on the rings it has.
380 * Returns 0 for success, errors for failure.
382 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
383 struct amdgpu_irq_src *irq_src,
386 struct amdgpu_device *adev = ring->adev;
389 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
390 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
391 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
393 /* put fence directly behind firmware */
394 index = ALIGN(adev->uvd.fw->size, 8);
395 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
396 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
398 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
401 amdgpu_irq_get(adev, irq_src, irq_type);
403 ring->fence_drv.irq_src = irq_src;
404 ring->fence_drv.irq_type = irq_type;
405 ring->fence_drv.initialized = true;
407 dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
408 "cpu addr 0x%p\n", ring->idx,
409 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
414 * amdgpu_fence_driver_init_ring - init the fence driver
415 * for the requested ring.
417 * @ring: ring to init the fence driver on
418 * @num_hw_submission: number of entries on the hardware queue
420 * Init the fence driver for the requested ring (all asics).
421 * Helper function for amdgpu_fence_driver_init().
423 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
424 unsigned num_hw_submission)
429 /* Check that num_hw_submission is a power of two */
430 if ((num_hw_submission & (num_hw_submission - 1)) != 0)
433 ring->fence_drv.cpu_addr = NULL;
434 ring->fence_drv.gpu_addr = 0;
435 ring->fence_drv.sync_seq = 0;
436 atomic_set(&ring->fence_drv.last_seq, 0);
437 ring->fence_drv.initialized = false;
439 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
441 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
442 spin_lock_init(&ring->fence_drv.lock);
443 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
445 if (!ring->fence_drv.fences)
448 /* No need to setup the GPU scheduler for KIQ ring */
449 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
450 /* for non-sriov case, no timeout enforce on compute ring */
451 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
452 && !amdgpu_sriov_vf(ring->adev))
453 timeout = MAX_SCHEDULE_TIMEOUT;
455 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
457 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
458 num_hw_submission, amdgpu_job_hang_limit,
459 timeout, ring->name);
461 DRM_ERROR("Failed to create scheduler on ring %s.\n",
471 * amdgpu_fence_driver_init - init the fence driver
472 * for all possible rings.
474 * @adev: amdgpu device pointer
476 * Init the fence driver for all possible rings (all asics).
477 * Not all asics have all rings, so each asic will only
478 * start the fence driver on the rings it has using
479 * amdgpu_fence_driver_start_ring().
480 * Returns 0 for success.
482 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
484 if (amdgpu_debugfs_fence_init(adev))
485 dev_err(adev->dev, "fence debugfs file creation failed\n");
491 * amdgpu_fence_driver_fini - tear down the fence driver
492 * for all possible rings.
494 * @adev: amdgpu device pointer
496 * Tear down the fence driver for all possible rings (all asics).
498 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
503 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
504 struct amdgpu_ring *ring = adev->rings[i];
506 if (!ring || !ring->fence_drv.initialized)
508 r = amdgpu_fence_wait_empty(ring);
510 /* no need to trigger GPU reset as we are unloading */
511 amdgpu_fence_driver_force_completion(ring);
513 if (ring->fence_drv.irq_src)
514 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
515 ring->fence_drv.irq_type);
516 drm_sched_fini(&ring->sched);
517 del_timer_sync(&ring->fence_drv.fallback_timer);
518 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
519 dma_fence_put(ring->fence_drv.fences[j]);
520 kfree(ring->fence_drv.fences);
521 ring->fence_drv.fences = NULL;
522 ring->fence_drv.initialized = false;
527 * amdgpu_fence_driver_suspend - suspend the fence driver
528 * for all possible rings.
530 * @adev: amdgpu device pointer
532 * Suspend the fence driver for all possible rings (all asics).
534 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
538 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
539 struct amdgpu_ring *ring = adev->rings[i];
540 if (!ring || !ring->fence_drv.initialized)
543 /* wait for gpu to finish processing current batch */
544 r = amdgpu_fence_wait_empty(ring);
546 /* delay GPU reset to resume */
547 amdgpu_fence_driver_force_completion(ring);
550 /* disable the interrupt */
551 if (ring->fence_drv.irq_src)
552 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
553 ring->fence_drv.irq_type);
558 * amdgpu_fence_driver_resume - resume the fence driver
559 * for all possible rings.
561 * @adev: amdgpu device pointer
563 * Resume the fence driver for all possible rings (all asics).
564 * Not all asics have all rings, so each asic will only
565 * start the fence driver on the rings it has using
566 * amdgpu_fence_driver_start_ring().
567 * Returns 0 for success.
569 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
573 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
574 struct amdgpu_ring *ring = adev->rings[i];
575 if (!ring || !ring->fence_drv.initialized)
578 /* enable the interrupt */
579 if (ring->fence_drv.irq_src)
580 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
581 ring->fence_drv.irq_type);
586 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
588 * @ring: fence of the ring to signal
591 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
593 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
594 amdgpu_fence_process(ring);
598 * Common fence implementation
601 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
606 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
608 struct amdgpu_fence *fence = to_amdgpu_fence(f);
609 return (const char *)fence->ring->name;
613 * amdgpu_fence_enable_signaling - enable signalling on fence
616 * This function is called with fence_queue lock held, and adds a callback
617 * to fence_queue that checks if this fence is signaled, and if so it
618 * signals the fence and removes itself.
620 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
622 struct amdgpu_fence *fence = to_amdgpu_fence(f);
623 struct amdgpu_ring *ring = fence->ring;
625 if (!timer_pending(&ring->fence_drv.fallback_timer))
626 amdgpu_fence_schedule_fallback(ring);
628 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
634 * amdgpu_fence_free - free up the fence memory
636 * @rcu: RCU callback head
638 * Free up the fence memory after the RCU grace period.
640 static void amdgpu_fence_free(struct rcu_head *rcu)
642 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
643 struct amdgpu_fence *fence = to_amdgpu_fence(f);
644 kmem_cache_free(amdgpu_fence_slab, fence);
648 * amdgpu_fence_release - callback that fence can be freed
652 * This function is called when the reference count becomes zero.
653 * It just RCU schedules freeing up the fence.
655 static void amdgpu_fence_release(struct dma_fence *f)
657 call_rcu(&f->rcu, amdgpu_fence_free);
660 static const struct dma_fence_ops amdgpu_fence_ops = {
661 .get_driver_name = amdgpu_fence_get_driver_name,
662 .get_timeline_name = amdgpu_fence_get_timeline_name,
663 .enable_signaling = amdgpu_fence_enable_signaling,
664 .release = amdgpu_fence_release,
670 #if defined(CONFIG_DEBUG_FS)
671 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
673 struct drm_info_node *node = (struct drm_info_node *)m->private;
674 struct drm_device *dev = node->minor->dev;
675 struct amdgpu_device *adev = dev->dev_private;
678 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
679 struct amdgpu_ring *ring = adev->rings[i];
680 if (!ring || !ring->fence_drv.initialized)
683 amdgpu_fence_process(ring);
685 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
686 seq_printf(m, "Last signaled fence 0x%08x\n",
687 atomic_read(&ring->fence_drv.last_seq));
688 seq_printf(m, "Last emitted 0x%08x\n",
689 ring->fence_drv.sync_seq);
691 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
694 /* set in CP_VMID_PREEMPT and preemption occurred */
695 seq_printf(m, "Last preempted 0x%08x\n",
696 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
697 /* set in CP_VMID_RESET and reset occurred */
698 seq_printf(m, "Last reset 0x%08x\n",
699 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
700 /* Both preemption and reset occurred */
701 seq_printf(m, "Last both 0x%08x\n",
702 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
708 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
710 * Manually trigger a gpu reset at the next fence wait.
712 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
714 struct drm_info_node *node = (struct drm_info_node *) m->private;
715 struct drm_device *dev = node->minor->dev;
716 struct amdgpu_device *adev = dev->dev_private;
718 seq_printf(m, "gpu recover\n");
719 amdgpu_device_gpu_recover(adev, NULL, true);
724 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
725 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
726 {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
729 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
730 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
734 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
736 #if defined(CONFIG_DEBUG_FS)
737 if (amdgpu_sriov_vf(adev))
738 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
739 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);