GNU Linux-libre 4.14.290-gnu1
[releases.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_display.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include <asm/div64.h>
33
34 #include <linux/pm_runtime.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37
38 static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb)
39 {
40         struct amdgpu_flip_work *work =
41                 container_of(cb, struct amdgpu_flip_work, cb);
42
43         dma_fence_put(f);
44         schedule_work(&work->flip_work.work);
45 }
46
47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
48                                      struct dma_fence **f)
49 {
50         struct dma_fence *fence= *f;
51
52         if (fence == NULL)
53                 return false;
54
55         *f = NULL;
56
57         if (!dma_fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
58                 return true;
59
60         dma_fence_put(fence);
61         return false;
62 }
63
64 static void amdgpu_flip_work_func(struct work_struct *__work)
65 {
66         struct delayed_work *delayed_work =
67                 container_of(__work, struct delayed_work, work);
68         struct amdgpu_flip_work *work =
69                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
70         struct amdgpu_device *adev = work->adev;
71         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
72
73         struct drm_crtc *crtc = &amdgpu_crtc->base;
74         unsigned long flags;
75         unsigned i;
76         int vpos, hpos;
77
78         if (amdgpu_flip_handle_fence(work, &work->excl))
79                 return;
80
81         for (i = 0; i < work->shared_count; ++i)
82                 if (amdgpu_flip_handle_fence(work, &work->shared[i]))
83                         return;
84
85         /* Wait until we're out of the vertical blank period before the one
86          * targeted by the flip
87          */
88         if (amdgpu_crtc->enabled &&
89             (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0,
90                                         &vpos, &hpos, NULL, NULL,
91                                         &crtc->hwmode)
92              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
93             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
94             (int)(work->target_vblank -
95                   amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
96                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
97                 return;
98         }
99
100         /* We borrow the event spin lock for protecting flip_status */
101         spin_lock_irqsave(&crtc->dev->event_lock, flags);
102
103         /* Do the flip (mmio) */
104         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
105
106         /* Set the flip status */
107         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
108         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
109
110
111         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
112                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
113
114 }
115
116 /*
117  * Handle unpin events outside the interrupt handler proper.
118  */
119 static void amdgpu_unpin_work_func(struct work_struct *__work)
120 {
121         struct amdgpu_flip_work *work =
122                 container_of(__work, struct amdgpu_flip_work, unpin_work);
123         int r;
124
125         /* unpin of the old buffer */
126         r = amdgpu_bo_reserve(work->old_abo, true);
127         if (likely(r == 0)) {
128                 r = amdgpu_bo_unpin(work->old_abo);
129                 if (unlikely(r != 0)) {
130                         DRM_ERROR("failed to unpin buffer after flip\n");
131                 }
132                 amdgpu_bo_unreserve(work->old_abo);
133         } else
134                 DRM_ERROR("failed to reserve buffer after flip\n");
135
136         amdgpu_bo_unref(&work->old_abo);
137         kfree(work->shared);
138         kfree(work);
139 }
140
141 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
142                                  struct drm_framebuffer *fb,
143                                  struct drm_pending_vblank_event *event,
144                                  uint32_t page_flip_flags, uint32_t target,
145                                  struct drm_modeset_acquire_ctx *ctx)
146 {
147         struct drm_device *dev = crtc->dev;
148         struct amdgpu_device *adev = dev->dev_private;
149         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
150         struct amdgpu_framebuffer *old_amdgpu_fb;
151         struct amdgpu_framebuffer *new_amdgpu_fb;
152         struct drm_gem_object *obj;
153         struct amdgpu_flip_work *work;
154         struct amdgpu_bo *new_abo;
155         unsigned long flags;
156         u64 tiling_flags;
157         u64 base;
158         int i, r;
159
160         work = kzalloc(sizeof *work, GFP_KERNEL);
161         if (work == NULL)
162                 return -ENOMEM;
163
164         INIT_DELAYED_WORK(&work->flip_work, amdgpu_flip_work_func);
165         INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
166
167         work->event = event;
168         work->adev = adev;
169         work->crtc_id = amdgpu_crtc->crtc_id;
170         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
171
172         /* schedule unpin of the old buffer */
173         old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
174         obj = old_amdgpu_fb->obj;
175
176         /* take a reference to the old object */
177         work->old_abo = gem_to_amdgpu_bo(obj);
178         amdgpu_bo_ref(work->old_abo);
179
180         new_amdgpu_fb = to_amdgpu_framebuffer(fb);
181         obj = new_amdgpu_fb->obj;
182         new_abo = gem_to_amdgpu_bo(obj);
183
184         /* pin the new buffer */
185         r = amdgpu_bo_reserve(new_abo, false);
186         if (unlikely(r != 0)) {
187                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
188                 goto cleanup;
189         }
190
191         r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base);
192         if (unlikely(r != 0)) {
193                 DRM_ERROR("failed to pin new abo buffer before flip\n");
194                 goto unreserve;
195         }
196
197         r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl,
198                                               &work->shared_count,
199                                               &work->shared);
200         if (unlikely(r != 0)) {
201                 DRM_ERROR("failed to get fences for buffer\n");
202                 goto unpin;
203         }
204
205         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
206         amdgpu_bo_unreserve(new_abo);
207
208         work->base = base;
209         work->target_vblank = target - drm_crtc_vblank_count(crtc) +
210                 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
211
212         /* we borrow the event spin lock for protecting flip_wrok */
213         spin_lock_irqsave(&crtc->dev->event_lock, flags);
214         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
215                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
216                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
217                 r = -EBUSY;
218                 goto pflip_cleanup;
219         }
220
221         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
222         amdgpu_crtc->pflip_works = work;
223
224
225         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
226                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
227         /* update crtc fb */
228         crtc->primary->fb = fb;
229         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
230         amdgpu_flip_work_func(&work->flip_work.work);
231         return 0;
232
233 pflip_cleanup:
234         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
235                 DRM_ERROR("failed to reserve new abo in error path\n");
236                 goto cleanup;
237         }
238 unpin:
239         if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
240                 DRM_ERROR("failed to unpin new abo in error path\n");
241         }
242 unreserve:
243         amdgpu_bo_unreserve(new_abo);
244
245 cleanup:
246         amdgpu_bo_unref(&work->old_abo);
247         dma_fence_put(work->excl);
248         for (i = 0; i < work->shared_count; ++i)
249                 dma_fence_put(work->shared[i]);
250         kfree(work->shared);
251         kfree(work);
252
253         return r;
254 }
255
256 int amdgpu_crtc_set_config(struct drm_mode_set *set,
257                            struct drm_modeset_acquire_ctx *ctx)
258 {
259         struct drm_device *dev;
260         struct amdgpu_device *adev;
261         struct drm_crtc *crtc;
262         bool active = false;
263         int ret;
264
265         if (!set || !set->crtc)
266                 return -EINVAL;
267
268         dev = set->crtc->dev;
269
270         ret = pm_runtime_get_sync(dev->dev);
271         if (ret < 0)
272                 goto out;
273
274         ret = drm_crtc_helper_set_config(set, ctx);
275
276         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
277                 if (crtc->enabled)
278                         active = true;
279
280         pm_runtime_mark_last_busy(dev->dev);
281
282         adev = dev->dev_private;
283         /* if we have active crtcs and we don't have a power ref,
284            take the current one */
285         if (active && !adev->have_disp_power_ref) {
286                 adev->have_disp_power_ref = true;
287                 return ret;
288         }
289         /* if we have no active crtcs, then drop the power ref
290            we got before */
291         if (!active && adev->have_disp_power_ref) {
292                 pm_runtime_put_autosuspend(dev->dev);
293                 adev->have_disp_power_ref = false;
294         }
295
296 out:
297         /* drop the power reference we got coming in here */
298         pm_runtime_put_autosuspend(dev->dev);
299         return ret;
300 }
301
302 static const char *encoder_names[41] = {
303         "NONE",
304         "INTERNAL_LVDS",
305         "INTERNAL_TMDS1",
306         "INTERNAL_TMDS2",
307         "INTERNAL_DAC1",
308         "INTERNAL_DAC2",
309         "INTERNAL_SDVOA",
310         "INTERNAL_SDVOB",
311         "SI170B",
312         "CH7303",
313         "CH7301",
314         "INTERNAL_DVO1",
315         "EXTERNAL_SDVOA",
316         "EXTERNAL_SDVOB",
317         "TITFP513",
318         "INTERNAL_LVTM1",
319         "VT1623",
320         "HDMI_SI1930",
321         "HDMI_INTERNAL",
322         "INTERNAL_KLDSCP_TMDS1",
323         "INTERNAL_KLDSCP_DVO1",
324         "INTERNAL_KLDSCP_DAC1",
325         "INTERNAL_KLDSCP_DAC2",
326         "SI178",
327         "MVPU_FPGA",
328         "INTERNAL_DDI",
329         "VT1625",
330         "HDMI_SI1932",
331         "DP_AN9801",
332         "DP_DP501",
333         "INTERNAL_UNIPHY",
334         "INTERNAL_KLDSCP_LVTMA",
335         "INTERNAL_UNIPHY1",
336         "INTERNAL_UNIPHY2",
337         "NUTMEG",
338         "TRAVIS",
339         "INTERNAL_VCE",
340         "INTERNAL_UNIPHY3",
341         "HDMI_ANX9805",
342         "INTERNAL_AMCLK",
343         "VIRTUAL",
344 };
345
346 static const char *hpd_names[6] = {
347         "HPD1",
348         "HPD2",
349         "HPD3",
350         "HPD4",
351         "HPD5",
352         "HPD6",
353 };
354
355 void amdgpu_print_display_setup(struct drm_device *dev)
356 {
357         struct drm_connector *connector;
358         struct amdgpu_connector *amdgpu_connector;
359         struct drm_encoder *encoder;
360         struct amdgpu_encoder *amdgpu_encoder;
361         uint32_t devices;
362         int i = 0;
363
364         DRM_INFO("AMDGPU Display Connectors\n");
365         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
366                 amdgpu_connector = to_amdgpu_connector(connector);
367                 DRM_INFO("Connector %d:\n", i);
368                 DRM_INFO("  %s\n", connector->name);
369                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
370                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
371                 if (amdgpu_connector->ddc_bus) {
372                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
373                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
374                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
375                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
376                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
377                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
378                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
379                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
380                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
381                         if (amdgpu_connector->router.ddc_valid)
382                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
383                                          amdgpu_connector->router.ddc_mux_control_pin,
384                                          amdgpu_connector->router.ddc_mux_state);
385                         if (amdgpu_connector->router.cd_valid)
386                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
387                                          amdgpu_connector->router.cd_mux_control_pin,
388                                          amdgpu_connector->router.cd_mux_state);
389                 } else {
390                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
391                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
392                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
393                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
394                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
395                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
396                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
397                 }
398                 DRM_INFO("  Encoders:\n");
399                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
400                         amdgpu_encoder = to_amdgpu_encoder(encoder);
401                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
402                         if (devices) {
403                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
404                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
405                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
406                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
407                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
408                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
409                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
410                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
411                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
412                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
413                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
414                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
415                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
416                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
417                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
418                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
419                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
420                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
421                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
422                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
423                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
424                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
425                         }
426                 }
427                 i++;
428         }
429 }
430
431 /**
432  * amdgpu_ddc_probe
433  *
434  */
435 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
436                        bool use_aux)
437 {
438         u8 out = 0x0;
439         u8 buf[8];
440         int ret;
441         struct i2c_msg msgs[] = {
442                 {
443                         .addr = DDC_ADDR,
444                         .flags = 0,
445                         .len = 1,
446                         .buf = &out,
447                 },
448                 {
449                         .addr = DDC_ADDR,
450                         .flags = I2C_M_RD,
451                         .len = 8,
452                         .buf = buf,
453                 }
454         };
455
456         /* on hw with routers, select right port */
457         if (amdgpu_connector->router.ddc_valid)
458                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
459
460         if (use_aux) {
461                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
462         } else {
463                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
464         }
465
466         if (ret != 2)
467                 /* Couldn't find an accessible DDC on this connector */
468                 return false;
469         /* Probe also for valid EDID header
470          * EDID header starts with:
471          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
472          * Only the first 6 bytes must be valid as
473          * drm_edid_block_valid() can fix the last 2 bytes */
474         if (drm_edid_header_is_valid(buf) < 6) {
475                 /* Couldn't find an accessible EDID on this
476                  * connector */
477                 return false;
478         }
479         return true;
480 }
481
482 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
483 {
484         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
485
486         drm_gem_object_put_unlocked(amdgpu_fb->obj);
487         drm_framebuffer_cleanup(fb);
488         kfree(amdgpu_fb);
489 }
490
491 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
492                                                   struct drm_file *file_priv,
493                                                   unsigned int *handle)
494 {
495         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
496
497         return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
498 }
499
500 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
501         .destroy = amdgpu_user_framebuffer_destroy,
502         .create_handle = amdgpu_user_framebuffer_create_handle,
503 };
504
505 int
506 amdgpu_framebuffer_init(struct drm_device *dev,
507                         struct amdgpu_framebuffer *rfb,
508                         const struct drm_mode_fb_cmd2 *mode_cmd,
509                         struct drm_gem_object *obj)
510 {
511         int ret;
512         rfb->obj = obj;
513         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
514         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
515         if (ret) {
516                 rfb->obj = NULL;
517                 return ret;
518         }
519         return 0;
520 }
521
522 static struct drm_framebuffer *
523 amdgpu_user_framebuffer_create(struct drm_device *dev,
524                                struct drm_file *file_priv,
525                                const struct drm_mode_fb_cmd2 *mode_cmd)
526 {
527         struct drm_gem_object *obj;
528         struct amdgpu_framebuffer *amdgpu_fb;
529         int ret;
530
531         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
532         if (obj ==  NULL) {
533                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
534                         "can't create framebuffer\n", mode_cmd->handles[0]);
535                 return ERR_PTR(-ENOENT);
536         }
537
538         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
539         if (obj->import_attach) {
540                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
541                 return ERR_PTR(-EINVAL);
542         }
543
544         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
545         if (amdgpu_fb == NULL) {
546                 drm_gem_object_put_unlocked(obj);
547                 return ERR_PTR(-ENOMEM);
548         }
549
550         ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
551         if (ret) {
552                 kfree(amdgpu_fb);
553                 drm_gem_object_put_unlocked(obj);
554                 return ERR_PTR(ret);
555         }
556
557         return &amdgpu_fb->base;
558 }
559
560 static void amdgpu_output_poll_changed(struct drm_device *dev)
561 {
562         struct amdgpu_device *adev = dev->dev_private;
563         amdgpu_fb_output_poll_changed(adev);
564 }
565
566 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
567         .fb_create = amdgpu_user_framebuffer_create,
568         .output_poll_changed = amdgpu_output_poll_changed
569 };
570
571 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
572 {       { UNDERSCAN_OFF, "off" },
573         { UNDERSCAN_ON, "on" },
574         { UNDERSCAN_AUTO, "auto" },
575 };
576
577 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
578 {       { AMDGPU_AUDIO_DISABLE, "off" },
579         { AMDGPU_AUDIO_ENABLE, "on" },
580         { AMDGPU_AUDIO_AUTO, "auto" },
581 };
582
583 /* XXX support different dither options? spatial, temporal, both, etc. */
584 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
585 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
586         { AMDGPU_FMT_DITHER_ENABLE, "on" },
587 };
588
589 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
590 {
591         int sz;
592
593         adev->mode_info.coherent_mode_property =
594                 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
595         if (!adev->mode_info.coherent_mode_property)
596                 return -ENOMEM;
597
598         adev->mode_info.load_detect_property =
599                 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
600         if (!adev->mode_info.load_detect_property)
601                 return -ENOMEM;
602
603         drm_mode_create_scaling_mode_property(adev->ddev);
604
605         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
606         adev->mode_info.underscan_property =
607                 drm_property_create_enum(adev->ddev, 0,
608                                     "underscan",
609                                     amdgpu_underscan_enum_list, sz);
610
611         adev->mode_info.underscan_hborder_property =
612                 drm_property_create_range(adev->ddev, 0,
613                                         "underscan hborder", 0, 128);
614         if (!adev->mode_info.underscan_hborder_property)
615                 return -ENOMEM;
616
617         adev->mode_info.underscan_vborder_property =
618                 drm_property_create_range(adev->ddev, 0,
619                                         "underscan vborder", 0, 128);
620         if (!adev->mode_info.underscan_vborder_property)
621                 return -ENOMEM;
622
623         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
624         adev->mode_info.audio_property =
625                 drm_property_create_enum(adev->ddev, 0,
626                                          "audio",
627                                          amdgpu_audio_enum_list, sz);
628
629         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
630         adev->mode_info.dither_property =
631                 drm_property_create_enum(adev->ddev, 0,
632                                          "dither",
633                                          amdgpu_dither_enum_list, sz);
634
635         return 0;
636 }
637
638 void amdgpu_update_display_priority(struct amdgpu_device *adev)
639 {
640         /* adjustment options for the display watermarks */
641         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
642                 adev->mode_info.disp_priority = 0;
643         else
644                 adev->mode_info.disp_priority = amdgpu_disp_priority;
645
646 }
647
648 static bool is_hdtv_mode(const struct drm_display_mode *mode)
649 {
650         /* try and guess if this is a tv or a monitor */
651         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
652             (mode->vdisplay == 576) || /* 576p */
653             (mode->vdisplay == 720) || /* 720p */
654             (mode->vdisplay == 1080)) /* 1080p */
655                 return true;
656         else
657                 return false;
658 }
659
660 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
661                                     const struct drm_display_mode *mode,
662                                     struct drm_display_mode *adjusted_mode)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_encoder *encoder;
666         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
667         struct amdgpu_encoder *amdgpu_encoder;
668         struct drm_connector *connector;
669         struct amdgpu_connector *amdgpu_connector;
670         u32 src_v = 1, dst_v = 1;
671         u32 src_h = 1, dst_h = 1;
672
673         amdgpu_crtc->h_border = 0;
674         amdgpu_crtc->v_border = 0;
675
676         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
677                 if (encoder->crtc != crtc)
678                         continue;
679                 amdgpu_encoder = to_amdgpu_encoder(encoder);
680                 connector = amdgpu_get_connector_for_encoder(encoder);
681                 amdgpu_connector = to_amdgpu_connector(connector);
682
683                 /* set scaling */
684                 if (amdgpu_encoder->rmx_type == RMX_OFF)
685                         amdgpu_crtc->rmx_type = RMX_OFF;
686                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
687                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
688                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
689                 else
690                         amdgpu_crtc->rmx_type = RMX_OFF;
691                 /* copy native mode */
692                 memcpy(&amdgpu_crtc->native_mode,
693                        &amdgpu_encoder->native_mode,
694                        sizeof(struct drm_display_mode));
695                 src_v = crtc->mode.vdisplay;
696                 dst_v = amdgpu_crtc->native_mode.vdisplay;
697                 src_h = crtc->mode.hdisplay;
698                 dst_h = amdgpu_crtc->native_mode.hdisplay;
699
700                 /* fix up for overscan on hdmi */
701                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
702                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
703                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
704                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
705                       is_hdtv_mode(mode)))) {
706                         if (amdgpu_encoder->underscan_hborder != 0)
707                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
708                         else
709                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
710                         if (amdgpu_encoder->underscan_vborder != 0)
711                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
712                         else
713                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
714                         amdgpu_crtc->rmx_type = RMX_FULL;
715                         src_v = crtc->mode.vdisplay;
716                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
717                         src_h = crtc->mode.hdisplay;
718                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
719                 }
720         }
721         if (amdgpu_crtc->rmx_type != RMX_OFF) {
722                 fixed20_12 a, b;
723                 a.full = dfixed_const(src_v);
724                 b.full = dfixed_const(dst_v);
725                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
726                 a.full = dfixed_const(src_h);
727                 b.full = dfixed_const(dst_h);
728                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
729         } else {
730                 amdgpu_crtc->vsc.full = dfixed_const(1);
731                 amdgpu_crtc->hsc.full = dfixed_const(1);
732         }
733         return true;
734 }
735
736 /*
737  * Retrieve current video scanout position of crtc on a given gpu, and
738  * an optional accurate timestamp of when query happened.
739  *
740  * \param dev Device to query.
741  * \param pipe Crtc to query.
742  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
743  *              For driver internal use only also supports these flags:
744  *
745  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
746  *              of a fudged earlier start of vblank.
747  *
748  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
749  *              fudged earlier start of vblank in *vpos and the distance
750  *              to true start of vblank in *hpos.
751  *
752  * \param *vpos Location where vertical scanout position should be stored.
753  * \param *hpos Location where horizontal scanout position should go.
754  * \param *stime Target location for timestamp taken immediately before
755  *               scanout position query. Can be NULL to skip timestamp.
756  * \param *etime Target location for timestamp taken immediately after
757  *               scanout position query. Can be NULL to skip timestamp.
758  *
759  * Returns vpos as a positive number while in active scanout area.
760  * Returns vpos as a negative number inside vblank, counting the number
761  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
762  * until start of active scanout / end of vblank."
763  *
764  * \return Flags, or'ed together as follows:
765  *
766  * DRM_SCANOUTPOS_VALID = Query successful.
767  * DRM_SCANOUTPOS_INVBL = Inside vblank.
768  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
769  * this flag means that returned position may be offset by a constant but
770  * unknown small number of scanlines wrt. real scanout position.
771  *
772  */
773 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
774                                unsigned int flags, int *vpos, int *hpos,
775                                ktime_t *stime, ktime_t *etime,
776                                const struct drm_display_mode *mode)
777 {
778         u32 vbl = 0, position = 0;
779         int vbl_start, vbl_end, vtotal, ret = 0;
780         bool in_vbl = true;
781
782         struct amdgpu_device *adev = dev->dev_private;
783
784         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
785
786         /* Get optional system timestamp before query. */
787         if (stime)
788                 *stime = ktime_get();
789
790         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
791                 ret |= DRM_SCANOUTPOS_VALID;
792
793         /* Get optional system timestamp after query. */
794         if (etime)
795                 *etime = ktime_get();
796
797         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
798
799         /* Decode into vertical and horizontal scanout position. */
800         *vpos = position & 0x1fff;
801         *hpos = (position >> 16) & 0x1fff;
802
803         /* Valid vblank area boundaries from gpu retrieved? */
804         if (vbl > 0) {
805                 /* Yes: Decode. */
806                 ret |= DRM_SCANOUTPOS_ACCURATE;
807                 vbl_start = vbl & 0x1fff;
808                 vbl_end = (vbl >> 16) & 0x1fff;
809         }
810         else {
811                 /* No: Fake something reasonable which gives at least ok results. */
812                 vbl_start = mode->crtc_vdisplay;
813                 vbl_end = 0;
814         }
815
816         /* Called from driver internal vblank counter query code? */
817         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
818             /* Caller wants distance from real vbl_start in *hpos */
819             *hpos = *vpos - vbl_start;
820         }
821
822         /* Fudge vblank to start a few scanlines earlier to handle the
823          * problem that vblank irqs fire a few scanlines before start
824          * of vblank. Some driver internal callers need the true vblank
825          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
826          *
827          * The cause of the "early" vblank irq is that the irq is triggered
828          * by the line buffer logic when the line buffer read position enters
829          * the vblank, whereas our crtc scanout position naturally lags the
830          * line buffer read position.
831          */
832         if (!(flags & USE_REAL_VBLANKSTART))
833                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
834
835         /* Test scanout position against vblank region. */
836         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
837                 in_vbl = false;
838
839         /* In vblank? */
840         if (in_vbl)
841             ret |= DRM_SCANOUTPOS_IN_VBLANK;
842
843         /* Called from driver internal vblank counter query code? */
844         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
845                 /* Caller wants distance from fudged earlier vbl_start */
846                 *vpos -= vbl_start;
847                 return ret;
848         }
849
850         /* Check if inside vblank area and apply corrective offsets:
851          * vpos will then be >=0 in video scanout area, but negative
852          * within vblank area, counting down the number of lines until
853          * start of scanout.
854          */
855
856         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
857         if (in_vbl && (*vpos >= vbl_start)) {
858                 vtotal = mode->crtc_vtotal;
859                 *vpos = *vpos - vtotal;
860         }
861
862         /* Correct for shifted end of vbl at vbl_end. */
863         *vpos = *vpos - vbl_end;
864
865         return ret;
866 }
867
868 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
869 {
870         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
871                 return AMDGPU_CRTC_IRQ_NONE;
872
873         switch (crtc) {
874         case 0:
875                 return AMDGPU_CRTC_IRQ_VBLANK1;
876         case 1:
877                 return AMDGPU_CRTC_IRQ_VBLANK2;
878         case 2:
879                 return AMDGPU_CRTC_IRQ_VBLANK3;
880         case 3:
881                 return AMDGPU_CRTC_IRQ_VBLANK4;
882         case 4:
883                 return AMDGPU_CRTC_IRQ_VBLANK5;
884         case 5:
885                 return AMDGPU_CRTC_IRQ_VBLANK6;
886         default:
887                 return AMDGPU_CRTC_IRQ_NONE;
888         }
889 }