drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 /*(DEBLOBBED)*/
  63
  64 #define AMDGPU_RESUME_MS                2000
  65
  66 static const char *amdgpu_asic_name[] = {
  67         "TAHITI",
  68         "PITCAIRN",
  69         "VERDE",
  70         "OLAND",
  71         "HAINAN",
  72         "BONAIRE",
  73         "KAVERI",
  74         "KABINI",
  75         "HAWAII",
  76         "MULLINS",
  77         "TOPAZ",
  78         "TONGA",
  79         "FIJI",
  80         "CARRIZO",
  81         "STONEY",
  82         "POLARIS10",
  83         "POLARIS11",
  84         "POLARIS12",
  85         "VEGAM",
  86         "VEGA10",
  87         "VEGA12",
  88         "VEGA20",
  89         "RAVEN",
  90         "LAST",
  91 };
  92
  93 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
  94
  95 /**
  96  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
  97  *
  98  * @dev: drm_device pointer
  99  *
 100  * Returns true if the device is a dGPU with HG/PX power control,
 101  * otherwise return false.
 102  */
 103 bool amdgpu_device_is_px(struct drm_device *dev)
 104 {
 105         struct amdgpu_device *adev = dev->dev_private;
 106
 107         if (adev->flags & AMD_IS_PX)
 108                 return true;
 109         return false;
 110 }
 111
 112 /*
 113  * MMIO register access helper functions.
 114  */
 115 /**
 116  * amdgpu_mm_rreg - read a memory mapped IO register
 117  *
 118  * @adev: amdgpu_device pointer
 119  * @reg: dword aligned register offset
 120  * @acc_flags: access flags which require special behavior
 121  *
 122  * Returns the 32 bit value from the offset specified.
 123  */
 124 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 125                         uint32_t acc_flags)
 126 {
 127         uint32_t ret;
 128
 129         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 130                 return amdgpu_virt_kiq_rreg(adev, reg);
 131
 132         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 133                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 134         else {
 135                 unsigned long flags;
 136
 137                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 138                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 139                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 140                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 141         }
 142         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 143         return ret;
 144 }
 145
 146 /*
 147  * MMIO register read with bytes helper functions
 148  * @offset:bytes offset from MMIO start
 149  *
 150 */
 151
 152 /**
 153  * amdgpu_mm_rreg8 - read a memory mapped IO register
 154  *
 155  * @adev: amdgpu_device pointer
 156  * @offset: byte aligned register offset
 157  *
 158  * Returns the 8 bit value from the offset specified.
 159  */
 160 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 161         if (offset < adev->rmmio_size)
 162                 return (readb(adev->rmmio + offset));
 163         BUG();
 164 }
 165
 166 /*
 167  * MMIO register write with bytes helper functions
 168  * @offset:bytes offset from MMIO start
 169  * @value: the value want to be written to the register
 170  *
 171 */
 172 /**
 173  * amdgpu_mm_wreg8 - read a memory mapped IO register
 174  *
 175  * @adev: amdgpu_device pointer
 176  * @offset: byte aligned register offset
 177  * @value: 8 bit value to write
 178  *
 179  * Writes the value specified to the offset specified.
 180  */
 181 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 182         if (offset < adev->rmmio_size)
 183                 writeb(value, adev->rmmio + offset);
 184         else
 185                 BUG();
 186 }
 187
 188 /**
 189  * amdgpu_mm_wreg - write to a memory mapped IO register
 190  *
 191  * @adev: amdgpu_device pointer
 192  * @reg: dword aligned register offset
 193  * @v: 32 bit value to write to the register
 194  * @acc_flags: access flags which require special behavior
 195  *
 196  * Writes the value specified to the offset specified.
 197  */
 198 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 199                     uint32_t acc_flags)
 200 {
 201         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 202
 203         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 204                 adev->last_mm_index = v;
 205         }
 206
 207         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 208                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 209
 210         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 211                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 212         else {
 213                 unsigned long flags;
 214
 215                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 216                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 217                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 218                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 219         }
 220
 221         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 222                 udelay(500);
 223         }
 224 }
 225
 226 /**
 227  * amdgpu_io_rreg - read an IO register
 228  *
 229  * @adev: amdgpu_device pointer
 230  * @reg: dword aligned register offset
 231  *
 232  * Returns the 32 bit value from the offset specified.
 233  */
 234 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 235 {
 236         if ((reg * 4) < adev->rio_mem_size)
 237                 return ioread32(adev->rio_mem + (reg * 4));
 238         else {
 239                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 240                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 241         }
 242 }
 243
 244 /**
 245  * amdgpu_io_wreg - write to an IO register
 246  *
 247  * @adev: amdgpu_device pointer
 248  * @reg: dword aligned register offset
 249  * @v: 32 bit value to write to the register
 250  *
 251  * Writes the value specified to the offset specified.
 252  */
 253 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 254 {
 255         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 256                 adev->last_mm_index = v;
 257         }
 258
 259         if ((reg * 4) < adev->rio_mem_size)
 260                 iowrite32(v, adev->rio_mem + (reg * 4));
 261         else {
 262                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 263                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 264         }
 265
 266         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 267                 udelay(500);
 268         }
 269 }
 270
 271 /**
 272  * amdgpu_mm_rdoorbell - read a doorbell dword
 273  *
 274  * @adev: amdgpu_device pointer
 275  * @index: doorbell index
 276  *
 277  * Returns the value in the doorbell aperture at the
 278  * requested doorbell index (CIK).
 279  */
 280 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 281 {
 282         if (index < adev->doorbell.num_doorbells) {
 283                 return readl(adev->doorbell.ptr + index);
 284         } else {
 285                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 286                 return 0;
 287         }
 288 }
 289
 290 /**
 291  * amdgpu_mm_wdoorbell - write a doorbell dword
 292  *
 293  * @adev: amdgpu_device pointer
 294  * @index: doorbell index
 295  * @v: value to write
 296  *
 297  * Writes @v to the doorbell aperture at the
 298  * requested doorbell index (CIK).
 299  */
 300 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 301 {
 302         if (index < adev->doorbell.num_doorbells) {
 303                 writel(v, adev->doorbell.ptr + index);
 304         } else {
 305                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 306         }
 307 }
 308
 309 /**
 310  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @index: doorbell index
 314  *
 315  * Returns the value in the doorbell aperture at the
 316  * requested doorbell index (VEGA10+).
 317  */
 318 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 319 {
 320         if (index < adev->doorbell.num_doorbells) {
 321                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 322         } else {
 323                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 324                 return 0;
 325         }
 326 }
 327
 328 /**
 329  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 330  *
 331  * @adev: amdgpu_device pointer
 332  * @index: doorbell index
 333  * @v: value to write
 334  *
 335  * Writes @v to the doorbell aperture at the
 336  * requested doorbell index (VEGA10+).
 337  */
 338 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 339 {
 340         if (index < adev->doorbell.num_doorbells) {
 341                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 342         } else {
 343                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 344         }
 345 }
 346
 347 /**
 348  * amdgpu_invalid_rreg - dummy reg read function
 349  *
 350  * @adev: amdgpu device pointer
 351  * @reg: offset of register
 352  *
 353  * Dummy register read function.  Used for register blocks
 354  * that certain asics don't have (all asics).
 355  * Returns the value in the register.
 356  */
 357 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 358 {
 359         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 360         BUG();
 361         return 0;
 362 }
 363
 364 /**
 365  * amdgpu_invalid_wreg - dummy reg write function
 366  *
 367  * @adev: amdgpu device pointer
 368  * @reg: offset of register
 369  * @v: value to write to the register
 370  *
 371  * Dummy register read function.  Used for register blocks
 372  * that certain asics don't have (all asics).
 373  */
 374 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 375 {
 376         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 377                   reg, v);
 378         BUG();
 379 }
 380
 381 /**
 382  * amdgpu_block_invalid_rreg - dummy reg read function
 383  *
 384  * @adev: amdgpu device pointer
 385  * @block: offset of instance
 386  * @reg: offset of register
 387  *
 388  * Dummy register read function.  Used for register blocks
 389  * that certain asics don't have (all asics).
 390  * Returns the value in the register.
 391  */
 392 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 393                                           uint32_t block, uint32_t reg)
 394 {
 395         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 396                   reg, block);
 397         BUG();
 398         return 0;
 399 }
 400
 401 /**
 402  * amdgpu_block_invalid_wreg - dummy reg write function
 403  *
 404  * @adev: amdgpu device pointer
 405  * @block: offset of instance
 406  * @reg: offset of register
 407  * @v: value to write to the register
 408  *
 409  * Dummy register read function.  Used for register blocks
 410  * that certain asics don't have (all asics).
 411  */
 412 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 413                                       uint32_t block,
 414                                       uint32_t reg, uint32_t v)
 415 {
 416         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 417                   reg, block, v);
 418         BUG();
 419 }
 420
 421 /**
 422  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 423  *
 424  * @adev: amdgpu device pointer
 425  *
 426  * Allocates a scratch page of VRAM for use by various things in the
 427  * driver.
 428  */
 429 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 430 {
 431         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 432                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 433                                        &adev->vram_scratch.robj,
 434                                        &adev->vram_scratch.gpu_addr,
 435                                        (void **)&adev->vram_scratch.ptr);
 436 }
 437
 438 /**
 439  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 440  *
 441  * @adev: amdgpu device pointer
 442  *
 443  * Frees the VRAM scratch page.
 444  */
 445 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 446 {
 447         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 448 }
 449
 450 /**
 451  * amdgpu_device_program_register_sequence - program an array of registers.
 452  *
 453  * @adev: amdgpu_device pointer
 454  * @registers: pointer to the register array
 455  * @array_size: size of the register array
 456  *
 457  * Programs an array or registers with and and or masks.
 458  * This is a helper for setting golden registers.
 459  */
 460 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 461                                              const u32 *registers,
 462                                              const u32 array_size)
 463 {
 464         u32 tmp, reg, and_mask, or_mask;
 465         int i;
 466
 467         if (array_size % 3)
 468                 return;
 469
 470         for (i = 0; i < array_size; i +=3) {
 471                 reg = registers[i + 0];
 472                 and_mask = registers[i + 1];
 473                 or_mask = registers[i + 2];
 474
 475                 if (and_mask == 0xffffffff) {
 476                         tmp = or_mask;
 477                 } else {
 478                         tmp = RREG32(reg);
 479                         tmp &= ~and_mask;
 480                         tmp |= or_mask;
 481                 }
 482                 WREG32(reg, tmp);
 483         }
 484 }
 485
 486 /**
 487  * amdgpu_device_pci_config_reset - reset the GPU
 488  *
 489  * @adev: amdgpu_device pointer
 490  *
 491  * Resets the GPU using the pci config reset sequence.
 492  * Only applicable to asics prior to vega10.
 493  */
 494 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 495 {
 496         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 497 }
 498
 499 /*
 500  * GPU doorbell aperture helpers function.
 501  */
 502 /**
 503  * amdgpu_device_doorbell_init - Init doorbell driver information.
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Init doorbell driver information (CIK)
 508  * Returns 0 on success, error on failure.
 509  */
 510 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 511 {
 512         /* No doorbell on SI hardware generation */
 513         if (adev->asic_type < CHIP_BONAIRE) {
 514                 adev->doorbell.base = 0;
 515                 adev->doorbell.size = 0;
 516                 adev->doorbell.num_doorbells = 0;
 517                 adev->doorbell.ptr = NULL;
 518                 return 0;
 519         }
 520
 521         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 522                 return -EINVAL;
 523
 524         /* doorbell bar mapping */
 525         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 526         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 527
 528         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 529                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 530         if (adev->doorbell.num_doorbells == 0)
 531                 return -EINVAL;
 532
 533         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 534                                      adev->doorbell.num_doorbells *
 535                                      sizeof(u32));
 536         if (adev->doorbell.ptr == NULL)
 537                 return -ENOMEM;
 538
 539         return 0;
 540 }
 541
 542 /**
 543  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 544  *
 545  * @adev: amdgpu_device pointer
 546  *
 547  * Tear down doorbell driver information (CIK)
 548  */
 549 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 550 {
 551         iounmap(adev->doorbell.ptr);
 552         adev->doorbell.ptr = NULL;
 553 }
 554
 555
 556
 557 /*
 558  * amdgpu_device_wb_*()
 559  * Writeback is the method by which the GPU updates special pages in memory
 560  * with the status of certain GPU events (fences, ring pointers,etc.).
 561  */
 562
 563 /**
 564  * amdgpu_device_wb_fini - Disable Writeback and free memory
 565  *
 566  * @adev: amdgpu_device pointer
 567  *
 568  * Disables Writeback and frees the Writeback memory (all asics).
 569  * Used at driver shutdown.
 570  */
 571 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 572 {
 573         if (adev->wb.wb_obj) {
 574                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 575                                       &adev->wb.gpu_addr,
 576                                       (void **)&adev->wb.wb);
 577                 adev->wb.wb_obj = NULL;
 578         }
 579 }
 580
 581 /**
 582  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 583  *
 584  * @adev: amdgpu_device pointer
 585  *
 586  * Initializes writeback and allocates writeback memory (all asics).
 587  * Used at driver startup.
 588  * Returns 0 on success or an -error on failure.
 589  */
 590 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 591 {
 592         int r;
 593
 594         if (adev->wb.wb_obj == NULL) {
 595                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 596                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 597                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 598                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 599                                             (void **)&adev->wb.wb);
 600                 if (r) {
 601                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 602                         return r;
 603                 }
 604
 605                 adev->wb.num_wb = AMDGPU_MAX_WB;
 606                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 607
 608                 /* clear wb memory */
 609                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 610         }
 611
 612         return 0;
 613 }
 614
 615 /**
 616  * amdgpu_device_wb_get - Allocate a wb entry
 617  *
 618  * @adev: amdgpu_device pointer
 619  * @wb: wb index
 620  *
 621  * Allocate a wb slot for use by the driver (all asics).
 622  * Returns 0 on success or -EINVAL on failure.
 623  */
 624 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 625 {
 626         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 627
 628         if (offset < adev->wb.num_wb) {
 629                 __set_bit(offset, adev->wb.used);
 630                 *wb = offset << 3; /* convert to dw offset */
 631                 return 0;
 632         } else {
 633                 return -EINVAL;
 634         }
 635 }
 636
 637 /**
 638  * amdgpu_device_wb_free - Free a wb entry
 639  *
 640  * @adev: amdgpu_device pointer
 641  * @wb: wb index
 642  *
 643  * Free a wb slot allocated for use by the driver (all asics)
 644  */
 645 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 646 {
 647         wb >>= 3;
 648         if (wb < adev->wb.num_wb)
 649                 __clear_bit(wb, adev->wb.used);
 650 }
 651
 652 /**
 653  * amdgpu_device_vram_location - try to find VRAM location
 654  *
 655  * @adev: amdgpu device structure holding all necessary informations
 656  * @mc: memory controller structure holding memory informations
 657  * @base: base address at which to put VRAM
 658  *
 659  * Function will try to place VRAM at base address provided
 660  * as parameter.
 661  */
 662 void amdgpu_device_vram_location(struct amdgpu_device *adev,
 663                                  struct amdgpu_gmc *mc, u64 base)
 664 {
 665         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 666
 667         mc->vram_start = base;
 668         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 669         if (limit && limit < mc->real_vram_size)
 670                 mc->real_vram_size = limit;
 671         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 672                         mc->mc_vram_size >> 20, mc->vram_start,
 673                         mc->vram_end, mc->real_vram_size >> 20);
 674 }
 675
 676 /**
 677  * amdgpu_device_gart_location - try to find GART location
 678  *
 679  * @adev: amdgpu device structure holding all necessary informations
 680  * @mc: memory controller structure holding memory informations
 681  *
 682  * Function will place try to place GART before or after VRAM.
 683  *
 684  * If GART size is bigger than space left then we ajust GART size.
 685  * Thus function will never fails.
 686  */
 687 void amdgpu_device_gart_location(struct amdgpu_device *adev,
 688                                  struct amdgpu_gmc *mc)
 689 {
 690         u64 size_af, size_bf;
 691
 692         mc->gart_size += adev->pm.smu_prv_buffer_size;
 693
 694         size_af = adev->gmc.mc_mask - mc->vram_end;
 695         size_bf = mc->vram_start;
 696         if (size_bf > size_af) {
 697                 if (mc->gart_size > size_bf) {
 698                         dev_warn(adev->dev, "limiting GART\n");
 699                         mc->gart_size = size_bf;
 700                 }
 701                 mc->gart_start = 0;
 702         } else {
 703                 if (mc->gart_size > size_af) {
 704                         dev_warn(adev->dev, "limiting GART\n");
 705                         mc->gart_size = size_af;
 706                 }
 707                 /* VCE doesn't like it when BOs cross a 4GB segment, so align
 708                  * the GART base on a 4GB boundary as well.
 709                  */
 710                 mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
 711         }
 712         mc->gart_end = mc->gart_start + mc->gart_size - 1;
 713         dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
 714                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 715 }
 716
 717 /**
 718  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 719  *
 720  * @adev: amdgpu_device pointer
 721  *
 722  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 723  * to fail, but if any of the BARs is not accessible after the size we abort
 724  * driver loading by returning -ENODEV.
 725  */
 726 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 727 {
 728         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 729         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 730         struct pci_bus *root;
 731         struct resource *res;
 732         unsigned i;
 733         u16 cmd;
 734         int r;
 735
 736         if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
 737                 return 0;
 738
 739         /* Bypass for VF */
 740         if (amdgpu_sriov_vf(adev))
 741                 return 0;
 742
 743         /* Check if the root BUS has 64bit memory resources */
 744         root = adev->pdev->bus;
 745         while (root->parent)
 746                 root = root->parent;
 747
 748         pci_bus_for_each_resource(root, res, i) {
 749                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 750                     res->start > 0x100000000ull)
 751                         break;
 752         }
 753
 754         /* Trying to resize is pointless without a root hub window above 4GB */
 755         if (!res)
 756                 return 0;
 757
 758         /* Disable memory decoding while we change the BAR addresses and size */
 759         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 760         pci_write_config_word(adev->pdev, PCI_COMMAND,
 761                               cmd & ~PCI_COMMAND_MEMORY);
 762
 763         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 764         amdgpu_device_doorbell_fini(adev);
 765         if (adev->asic_type >= CHIP_BONAIRE)
 766                 pci_release_resource(adev->pdev, 2);
 767
 768         pci_release_resource(adev->pdev, 0);
 769
 770         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 771         if (r == -ENOSPC)
 772                 DRM_INFO("Not enough PCI address space for a large BAR.");
 773         else if (r && r != -ENOTSUPP)
 774                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 775
 776         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 777
 778         /* When the doorbell or fb BAR isn't available we have no chance of
 779          * using the device.
 780          */
 781         r = amdgpu_device_doorbell_init(adev);
 782         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 783                 return -ENODEV;
 784
 785         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 786
 787         return 0;
 788 }
 789
 790 /*
 791  * GPU helpers function.
 792  */
 793 /**
 794  * amdgpu_device_need_post - check if the hw need post or not
 795  *
 796  * @adev: amdgpu_device pointer
 797  *
 798  * Check if the asic has been initialized (all asics) at driver startup
 799  * or post is needed if  hw reset is performed.
 800  * Returns true if need or false if not.
 801  */
 802 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 803 {
 804         uint32_t reg;
 805
 806         if (amdgpu_sriov_vf(adev))
 807                 return false;
 808
 809         if (amdgpu_passthrough(adev)) {
 810                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 811                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 812                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 813                  * vpost executed for smc version below 22.15
 814                  */
 815                 if (adev->asic_type == CHIP_FIJI) {
 816                         int err;
 817                         uint32_t fw_ver;
 818                         err = reject_firmware(&adev->pm.fw, "/*(DEBLOBBED)*/", adev->dev);
 819                         /* force vPost if error occured */
 820                         if (err)
 821                                 return true;
 822
 823                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 824                         if (fw_ver < 0x00160e00)
 825                                 return true;
 826                 }
 827         }
 828
 829         if (adev->has_hw_reset) {
 830                 adev->has_hw_reset = false;
 831                 return true;
 832         }
 833
 834         /* bios scratch used on CIK+ */
 835         if (adev->asic_type >= CHIP_BONAIRE)
 836                 return amdgpu_atombios_scratch_need_asic_init(adev);
 837
 838         /* check MEM_SIZE for older asics */
 839         reg = amdgpu_asic_get_config_memsize(adev);
 840
 841         if ((reg != 0) && (reg != 0xffffffff))
 842                 return false;
 843
 844         return true;
 845 }
 846
 847 /* if we get transitioned to only one device, take VGA back */
 848 /**
 849  * amdgpu_device_vga_set_decode - enable/disable vga decode
 850  *
 851  * @cookie: amdgpu_device pointer
 852  * @state: enable/disable vga decode
 853  *
 854  * Enable/disable vga decode (all asics).
 855  * Returns VGA resource flags.
 856  */
 857 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 858 {
 859         struct amdgpu_device *adev = cookie;
 860         amdgpu_asic_set_vga_state(adev, state);
 861         if (state)
 862                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 863                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 864         else
 865                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 866 }
 867
 868 /**
 869  * amdgpu_device_check_block_size - validate the vm block size
 870  *
 871  * @adev: amdgpu_device pointer
 872  *
 873  * Validates the vm block size specified via module parameter.
 874  * The vm block size defines number of bits in page table versus page directory,
 875  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 876  * page table and the remaining bits are in the page directory.
 877  */
 878 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 879 {
 880         /* defines number of bits in page table versus page directory,
 881          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 882          * page table and the remaining bits are in the page directory */
 883         if (amdgpu_vm_block_size == -1)
 884                 return;
 885
 886         if (amdgpu_vm_block_size < 9) {
 887                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 888                          amdgpu_vm_block_size);
 889                 amdgpu_vm_block_size = -1;
 890         }
 891 }
 892
 893 /**
 894  * amdgpu_device_check_vm_size - validate the vm size
 895  *
 896  * @adev: amdgpu_device pointer
 897  *
 898  * Validates the vm size in GB specified via module parameter.
 899  * The VM size is the size of the GPU virtual memory space in GB.
 900  */
 901 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 902 {
 903         /* no need to check the default value */
 904         if (amdgpu_vm_size == -1)
 905                 return;
 906
 907         if (amdgpu_vm_size < 1) {
 908                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 909                          amdgpu_vm_size);
 910                 amdgpu_vm_size = -1;
 911         }
 912 }
 913
 914 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 915 {
 916         struct sysinfo si;
 917         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 918         uint64_t total_memory;
 919         uint64_t dram_size_seven_GB = 0x1B8000000;
 920         uint64_t dram_size_three_GB = 0xB8000000;
 921
 922         if (amdgpu_smu_memory_pool_size == 0)
 923                 return;
 924
 925         if (!is_os_64) {
 926                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 927                 goto def_value;
 928         }
 929         si_meminfo(&si);
 930         total_memory = (uint64_t)si.totalram * si.mem_unit;
 931
 932         if ((amdgpu_smu_memory_pool_size == 1) ||
 933                 (amdgpu_smu_memory_pool_size == 2)) {
 934                 if (total_memory < dram_size_three_GB)
 935                         goto def_value1;
 936         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 937                 (amdgpu_smu_memory_pool_size == 8)) {
 938                 if (total_memory < dram_size_seven_GB)
 939                         goto def_value1;
 940         } else {
 941                 DRM_WARN("Smu memory pool size not supported\n");
 942                 goto def_value;
 943         }
 944         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 945
 946         return;
 947
 948 def_value1:
 949         DRM_WARN("No enough system memory\n");
 950 def_value:
 951         adev->pm.smu_prv_buffer_size = 0;
 952 }
 953
 954 /**
 955  * amdgpu_device_check_arguments - validate module params
 956  *
 957  * @adev: amdgpu_device pointer
 958  *
 959  * Validates certain module parameters and updates
 960  * the associated values used by the driver (all asics).
 961  */
 962 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 963 {
 964         if (amdgpu_sched_jobs < 4) {
 965                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 966                          amdgpu_sched_jobs);
 967                 amdgpu_sched_jobs = 4;
 968         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 969                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 970                          amdgpu_sched_jobs);
 971                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 972         }
 973
 974         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 975                 /* gart size must be greater or equal to 32M */
 976                 dev_warn(adev->dev, "gart size (%d) too small\n",
 977                          amdgpu_gart_size);
 978                 amdgpu_gart_size = -1;
 979         }
 980
 981         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 982                 /* gtt size must be greater or equal to 32M */
 983                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 984                                  amdgpu_gtt_size);
 985                 amdgpu_gtt_size = -1;
 986         }
 987
 988         /* valid range is between 4 and 9 inclusive */
 989         if (amdgpu_vm_fragment_size != -1 &&
 990             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 991                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 992                 amdgpu_vm_fragment_size = -1;
 993         }
 994
 995         amdgpu_device_check_smu_prv_buffer_size(adev);
 996
 997         amdgpu_device_check_vm_size(adev);
 998
 999         amdgpu_device_check_block_size(adev);
1000
1001         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1002             !is_power_of_2(amdgpu_vram_page_split))) {
1003                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1004                          amdgpu_vram_page_split);
1005                 amdgpu_vram_page_split = 1024;
1006         }
1007
1008         if (amdgpu_lockup_timeout == 0) {
1009                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
1010                 amdgpu_lockup_timeout = 10000;
1011         }
1012
1013         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1014 }
1015
1016 /**
1017  * amdgpu_switcheroo_set_state - set switcheroo state
1018  *
1019  * @pdev: pci dev pointer
1020  * @state: vga_switcheroo state
1021  *
1022  * Callback for the switcheroo driver.  Suspends or resumes the
1023  * the asics before or after it is powered up using ACPI methods.
1024  */
1025 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1026 {
1027         struct drm_device *dev = pci_get_drvdata(pdev);
1028
1029         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1030                 return;
1031
1032         if (state == VGA_SWITCHEROO_ON) {
1033                 pr_info("amdgpu: switched on\n");
1034                 /* don't suspend or resume card normally */
1035                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1036
1037                 amdgpu_device_resume(dev, true, true);
1038
1039                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1040                 drm_kms_helper_poll_enable(dev);
1041         } else {
1042                 pr_info("amdgpu: switched off\n");
1043                 drm_kms_helper_poll_disable(dev);
1044                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1045                 amdgpu_device_suspend(dev, true, true);
1046                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1047         }
1048 }
1049
1050 /**
1051  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1052  *
1053  * @pdev: pci dev pointer
1054  *
1055  * Callback for the switcheroo driver.  Check of the switcheroo
1056  * state can be changed.
1057  * Returns true if the state can be changed, false if not.
1058  */
1059 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1060 {
1061         struct drm_device *dev = pci_get_drvdata(pdev);
1062
1063         /*
1064         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1065         * locking inversion with the driver load path. And the access here is
1066         * completely racy anyway. So don't bother with locking for now.
1067         */
1068         return dev->open_count == 0;
1069 }
1070
1071 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1072         .set_gpu_state = amdgpu_switcheroo_set_state,
1073         .reprobe = NULL,
1074         .can_switch = amdgpu_switcheroo_can_switch,
1075 };
1076
1077 /**
1078  * amdgpu_device_ip_set_clockgating_state - set the CG state
1079  *
1080  * @dev: amdgpu_device pointer
1081  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1082  * @state: clockgating state (gate or ungate)
1083  *
1084  * Sets the requested clockgating state for all instances of
1085  * the hardware IP specified.
1086  * Returns the error code from the last instance.
1087  */
1088 int amdgpu_device_ip_set_clockgating_state(void *dev,
1089                                            enum amd_ip_block_type block_type,
1090                                            enum amd_clockgating_state state)
1091 {
1092         struct amdgpu_device *adev = dev;
1093         int i, r = 0;
1094
1095         for (i = 0; i < adev->num_ip_blocks; i++) {
1096                 if (!adev->ip_blocks[i].status.valid)
1097                         continue;
1098                 if (adev->ip_blocks[i].version->type != block_type)
1099                         continue;
1100                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1101                         continue;
1102                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1103                         (void *)adev, state);
1104                 if (r)
1105                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1106                                   adev->ip_blocks[i].version->funcs->name, r);
1107         }
1108         return r;
1109 }
1110
1111 /**
1112  * amdgpu_device_ip_set_powergating_state - set the PG state
1113  *
1114  * @dev: amdgpu_device pointer
1115  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1116  * @state: powergating state (gate or ungate)
1117  *
1118  * Sets the requested powergating state for all instances of
1119  * the hardware IP specified.
1120  * Returns the error code from the last instance.
1121  */
1122 int amdgpu_device_ip_set_powergating_state(void *dev,
1123                                            enum amd_ip_block_type block_type,
1124                                            enum amd_powergating_state state)
1125 {
1126         struct amdgpu_device *adev = dev;
1127         int i, r = 0;
1128
1129         for (i = 0; i < adev->num_ip_blocks; i++) {
1130                 if (!adev->ip_blocks[i].status.valid)
1131                         continue;
1132                 if (adev->ip_blocks[i].version->type != block_type)
1133                         continue;
1134                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1135                         continue;
1136                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1137                         (void *)adev, state);
1138                 if (r)
1139                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1140                                   adev->ip_blocks[i].version->funcs->name, r);
1141         }
1142         return r;
1143 }
1144
1145 /**
1146  * amdgpu_device_ip_get_clockgating_state - get the CG state
1147  *
1148  * @adev: amdgpu_device pointer
1149  * @flags: clockgating feature flags
1150  *
1151  * Walks the list of IPs on the device and updates the clockgating
1152  * flags for each IP.
1153  * Updates @flags with the feature flags for each hardware IP where
1154  * clockgating is enabled.
1155  */
1156 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1157                                             u32 *flags)
1158 {
1159         int i;
1160
1161         for (i = 0; i < adev->num_ip_blocks; i++) {
1162                 if (!adev->ip_blocks[i].status.valid)
1163                         continue;
1164                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1165                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1166         }
1167 }
1168
1169 /**
1170  * amdgpu_device_ip_wait_for_idle - wait for idle
1171  *
1172  * @adev: amdgpu_device pointer
1173  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1174  *
1175  * Waits for the request hardware IP to be idle.
1176  * Returns 0 for success or a negative error code on failure.
1177  */
1178 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1179                                    enum amd_ip_block_type block_type)
1180 {
1181         int i, r;
1182
1183         for (i = 0; i < adev->num_ip_blocks; i++) {
1184                 if (!adev->ip_blocks[i].status.valid)
1185                         continue;
1186                 if (adev->ip_blocks[i].version->type == block_type) {
1187                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1188                         if (r)
1189                                 return r;
1190                         break;
1191                 }
1192         }
1193         return 0;
1194
1195 }
1196
1197 /**
1198  * amdgpu_device_ip_is_idle - is the hardware IP idle
1199  *
1200  * @adev: amdgpu_device pointer
1201  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1202  *
1203  * Check if the hardware IP is idle or not.
1204  * Returns true if it the IP is idle, false if not.
1205  */
1206 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1207                               enum amd_ip_block_type block_type)
1208 {
1209         int i;
1210
1211         for (i = 0; i < adev->num_ip_blocks; i++) {
1212                 if (!adev->ip_blocks[i].status.valid)
1213                         continue;
1214                 if (adev->ip_blocks[i].version->type == block_type)
1215                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1216         }
1217         return true;
1218
1219 }
1220
1221 /**
1222  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1223  *
1224  * @adev: amdgpu_device pointer
1225  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1226  *
1227  * Returns a pointer to the hardware IP block structure
1228  * if it exists for the asic, otherwise NULL.
1229  */
1230 struct amdgpu_ip_block *
1231 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1232                               enum amd_ip_block_type type)
1233 {
1234         int i;
1235
1236         for (i = 0; i < adev->num_ip_blocks; i++)
1237                 if (adev->ip_blocks[i].version->type == type)
1238                         return &adev->ip_blocks[i];
1239
1240         return NULL;
1241 }
1242
1243 /**
1244  * amdgpu_device_ip_block_version_cmp
1245  *
1246  * @adev: amdgpu_device pointer
1247  * @type: enum amd_ip_block_type
1248  * @major: major version
1249  * @minor: minor version
1250  *
1251  * return 0 if equal or greater
1252  * return 1 if smaller or the ip_block doesn't exist
1253  */
1254 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1255                                        enum amd_ip_block_type type,
1256                                        u32 major, u32 minor)
1257 {
1258         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1259
1260         if (ip_block && ((ip_block->version->major > major) ||
1261                         ((ip_block->version->major == major) &&
1262                         (ip_block->version->minor >= minor))))
1263                 return 0;
1264
1265         return 1;
1266 }
1267
1268 /**
1269  * amdgpu_device_ip_block_add
1270  *
1271  * @adev: amdgpu_device pointer
1272  * @ip_block_version: pointer to the IP to add
1273  *
1274  * Adds the IP block driver information to the collection of IPs
1275  * on the asic.
1276  */
1277 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1278                                const struct amdgpu_ip_block_version *ip_block_version)
1279 {
1280         if (!ip_block_version)
1281                 return -EINVAL;
1282
1283         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1284                   ip_block_version->funcs->name);
1285
1286         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1287
1288         return 0;
1289 }
1290
1291 /**
1292  * amdgpu_device_enable_virtual_display - enable virtual display feature
1293  *
1294  * @adev: amdgpu_device pointer
1295  *
1296  * Enabled the virtual display feature if the user has enabled it via
1297  * the module parameter virtual_display.  This feature provides a virtual
1298  * display hardware on headless boards or in virtualized environments.
1299  * This function parses and validates the configuration string specified by
1300  * the user and configues the virtual display configuration (number of
1301  * virtual connectors, crtcs, etc.) specified.
1302  */
1303 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1304 {
1305         adev->enable_virtual_display = false;
1306
1307         if (amdgpu_virtual_display) {
1308                 struct drm_device *ddev = adev->ddev;
1309                 const char *pci_address_name = pci_name(ddev->pdev);
1310                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1311
1312                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1313                 pciaddstr_tmp = pciaddstr;
1314                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1315                         pciaddname = strsep(&pciaddname_tmp, ",");
1316                         if (!strcmp("all", pciaddname)
1317                             || !strcmp(pci_address_name, pciaddname)) {
1318                                 long num_crtc;
1319                                 int res = -1;
1320
1321                                 adev->enable_virtual_display = true;
1322
1323                                 if (pciaddname_tmp)
1324                                         res = kstrtol(pciaddname_tmp, 10,
1325                                                       &num_crtc);
1326
1327                                 if (!res) {
1328                                         if (num_crtc < 1)
1329                                                 num_crtc = 1;
1330                                         if (num_crtc > 6)
1331                                                 num_crtc = 6;
1332                                         adev->mode_info.num_crtc = num_crtc;
1333                                 } else {
1334                                         adev->mode_info.num_crtc = 1;
1335                                 }
1336                                 break;
1337                         }
1338                 }
1339
1340                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1341                          amdgpu_virtual_display, pci_address_name,
1342                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1343
1344                 kfree(pciaddstr);
1345         }
1346 }
1347
1348 /**
1349  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1350  *
1351  * @adev: amdgpu_device pointer
1352  *
1353  * Parses the asic configuration parameters specified in the gpu info
1354  * firmware and makes them availale to the driver for use in configuring
1355  * the asic.
1356  * Returns 0 on success, -EINVAL on failure.
1357  */
1358 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1359 {
1360         const char *chip_name;
1361         char fw_name[30];
1362         int err;
1363         const struct gpu_info_firmware_header_v1_0 *hdr;
1364
1365         adev->firmware.gpu_info_fw = NULL;
1366
1367         switch (adev->asic_type) {
1368         case CHIP_TOPAZ:
1369         case CHIP_TONGA:
1370         case CHIP_FIJI:
1371         case CHIP_POLARIS10:
1372         case CHIP_POLARIS11:
1373         case CHIP_POLARIS12:
1374         case CHIP_VEGAM:
1375         case CHIP_CARRIZO:
1376         case CHIP_STONEY:
1377 #ifdef CONFIG_DRM_AMDGPU_SI
1378         case CHIP_VERDE:
1379         case CHIP_TAHITI:
1380         case CHIP_PITCAIRN:
1381         case CHIP_OLAND:
1382         case CHIP_HAINAN:
1383 #endif
1384 #ifdef CONFIG_DRM_AMDGPU_CIK
1385         case CHIP_BONAIRE:
1386         case CHIP_HAWAII:
1387         case CHIP_KAVERI:
1388         case CHIP_KABINI:
1389         case CHIP_MULLINS:
1390 #endif
1391         case CHIP_VEGA20:
1392         default:
1393                 return 0;
1394         case CHIP_VEGA10:
1395                 chip_name = "vega10";
1396                 break;
1397         case CHIP_VEGA12:
1398                 chip_name = "vega12";
1399                 break;
1400         case CHIP_RAVEN:
1401                 chip_name = "raven";
1402                 break;
1403         }
1404
1405         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1406         err = reject_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1407         if (err) {
1408                 dev_err(adev->dev,
1409                         "Failed to load gpu_info firmware \"%s\"\n",
1410                         fw_name);
1411                 goto out;
1412         }
1413         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1414         if (err) {
1415                 dev_err(adev->dev,
1416                         "Failed to validate gpu_info firmware \"%s\"\n",
1417                         fw_name);
1418                 goto out;
1419         }
1420
1421         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1422         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1423
1424         switch (hdr->version_major) {
1425         case 1:
1426         {
1427                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1428                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1429                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1430
1431                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1432                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1433                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1434                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1435                 adev->gfx.config.max_texture_channel_caches =
1436                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1437                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1438                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1439                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1440                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1441                 adev->gfx.config.double_offchip_lds_buf =
1442                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1443                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1444                 adev->gfx.cu_info.max_waves_per_simd =
1445                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1446                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1447                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1448                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1449                 break;
1450         }
1451         default:
1452                 dev_err(adev->dev,
1453                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1454                 err = -EINVAL;
1455                 goto out;
1456         }
1457 out:
1458         return err;
1459 }
1460
1461 /**
1462  * amdgpu_device_ip_early_init - run early init for hardware IPs
1463  *
1464  * @adev: amdgpu_device pointer
1465  *
1466  * Early initialization pass for hardware IPs.  The hardware IPs that make
1467  * up each asic are discovered each IP's early_init callback is run.  This
1468  * is the first stage in initializing the asic.
1469  * Returns 0 on success, negative error code on failure.
1470  */
1471 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1472 {
1473         int i, r;
1474
1475         amdgpu_device_enable_virtual_display(adev);
1476
1477         switch (adev->asic_type) {
1478         case CHIP_TOPAZ:
1479         case CHIP_TONGA:
1480         case CHIP_FIJI:
1481         case CHIP_POLARIS10:
1482         case CHIP_POLARIS11:
1483         case CHIP_POLARIS12:
1484         case CHIP_VEGAM:
1485         case CHIP_CARRIZO:
1486         case CHIP_STONEY:
1487                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1488                         adev->family = AMDGPU_FAMILY_CZ;
1489                 else
1490                         adev->family = AMDGPU_FAMILY_VI;
1491
1492                 r = vi_set_ip_blocks(adev);
1493                 if (r)
1494                         return r;
1495                 break;
1496 #ifdef CONFIG_DRM_AMDGPU_SI
1497         case CHIP_VERDE:
1498         case CHIP_TAHITI:
1499         case CHIP_PITCAIRN:
1500         case CHIP_OLAND:
1501         case CHIP_HAINAN:
1502                 adev->family = AMDGPU_FAMILY_SI;
1503                 r = si_set_ip_blocks(adev);
1504                 if (r)
1505                         return r;
1506                 break;
1507 #endif
1508 #ifdef CONFIG_DRM_AMDGPU_CIK
1509         case CHIP_BONAIRE:
1510         case CHIP_HAWAII:
1511         case CHIP_KAVERI:
1512         case CHIP_KABINI:
1513         case CHIP_MULLINS:
1514                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1515                         adev->family = AMDGPU_FAMILY_CI;
1516                 else
1517                         adev->family = AMDGPU_FAMILY_KV;
1518
1519                 r = cik_set_ip_blocks(adev);
1520                 if (r)
1521                         return r;
1522                 break;
1523 #endif
1524         case CHIP_VEGA10:
1525         case CHIP_VEGA12:
1526         case CHIP_VEGA20:
1527         case CHIP_RAVEN:
1528                 if (adev->asic_type == CHIP_RAVEN)
1529                         adev->family = AMDGPU_FAMILY_RV;
1530                 else
1531                         adev->family = AMDGPU_FAMILY_AI;
1532
1533                 r = soc15_set_ip_blocks(adev);
1534                 if (r)
1535                         return r;
1536                 break;
1537         default:
1538                 /* FIXME: not supported yet */
1539                 return -EINVAL;
1540         }
1541
1542         r = amdgpu_device_parse_gpu_info_fw(adev);
1543         if (r)
1544                 return r;
1545
1546         amdgpu_amdkfd_device_probe(adev);
1547
1548         if (amdgpu_sriov_vf(adev)) {
1549                 r = amdgpu_virt_request_full_gpu(adev, true);
1550                 if (r)
1551                         return -EAGAIN;
1552         }
1553
1554         adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1555
1556         for (i = 0; i < adev->num_ip_blocks; i++) {
1557                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1558                         DRM_ERROR("disabled ip block: %d <%s>\n",
1559                                   i, adev->ip_blocks[i].version->funcs->name);
1560                         adev->ip_blocks[i].status.valid = false;
1561                 } else {
1562                         if (adev->ip_blocks[i].version->funcs->early_init) {
1563                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1564                                 if (r == -ENOENT) {
1565                                         adev->ip_blocks[i].status.valid = false;
1566                                 } else if (r) {
1567                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1568                                                   adev->ip_blocks[i].version->funcs->name, r);
1569                                         return r;
1570                                 } else {
1571                                         adev->ip_blocks[i].status.valid = true;
1572                                 }
1573                         } else {
1574                                 adev->ip_blocks[i].status.valid = true;
1575                         }
1576                 }
1577         }
1578
1579         adev->cg_flags &= amdgpu_cg_mask;
1580         adev->pg_flags &= amdgpu_pg_mask;
1581
1582         return 0;
1583 }
1584
1585 /**
1586  * amdgpu_device_ip_init - run init for hardware IPs
1587  *
1588  * @adev: amdgpu_device pointer
1589  *
1590  * Main initialization pass for hardware IPs.  The list of all the hardware
1591  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1592  * are run.  sw_init initializes the software state associated with each IP
1593  * and hw_init initializes the hardware associated with each IP.
1594  * Returns 0 on success, negative error code on failure.
1595  */
1596 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1597 {
1598         int i, r;
1599
1600         for (i = 0; i < adev->num_ip_blocks; i++) {
1601                 if (!adev->ip_blocks[i].status.valid)
1602                         continue;
1603                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1604                 if (r) {
1605                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1606                                   adev->ip_blocks[i].version->funcs->name, r);
1607                         return r;
1608                 }
1609                 adev->ip_blocks[i].status.sw = true;
1610
1611                 /* need to do gmc hw init early so we can allocate gpu mem */
1612                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1613                         r = amdgpu_device_vram_scratch_init(adev);
1614                         if (r) {
1615                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1616                                 return r;
1617                         }
1618                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1619                         if (r) {
1620                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1621                                 return r;
1622                         }
1623                         r = amdgpu_device_wb_init(adev);
1624                         if (r) {
1625                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1626                                 return r;
1627                         }
1628                         adev->ip_blocks[i].status.hw = true;
1629
1630                         /* right after GMC hw init, we create CSA */
1631                         if (amdgpu_sriov_vf(adev)) {
1632                                 r = amdgpu_allocate_static_csa(adev);
1633                                 if (r) {
1634                                         DRM_ERROR("allocate CSA failed %d\n", r);
1635                                         return r;
1636                                 }
1637                         }
1638                 }
1639         }
1640
1641         for (i = 0; i < adev->num_ip_blocks; i++) {
1642                 if (!adev->ip_blocks[i].status.sw)
1643                         continue;
1644                 if (adev->ip_blocks[i].status.hw)
1645                         continue;
1646                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1647                 if (r) {
1648                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1649                                   adev->ip_blocks[i].version->funcs->name, r);
1650                         return r;
1651                 }
1652                 adev->ip_blocks[i].status.hw = true;
1653         }
1654
1655         amdgpu_amdkfd_device_init(adev);
1656
1657         if (amdgpu_sriov_vf(adev)) {
1658                 amdgpu_virt_init_data_exchange(adev);
1659                 amdgpu_virt_release_full_gpu(adev, true);
1660         }
1661
1662         return 0;
1663 }
1664
1665 /**
1666  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1667  *
1668  * @adev: amdgpu_device pointer
1669  *
1670  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1671  * this function before a GPU reset.  If the value is retained after a
1672  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1673  */
1674 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1675 {
1676         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1677 }
1678
1679 /**
1680  * amdgpu_device_check_vram_lost - check if vram is valid
1681  *
1682  * @adev: amdgpu_device pointer
1683  *
1684  * Checks the reset magic value written to the gart pointer in VRAM.
1685  * The driver calls this after a GPU reset to see if the contents of
1686  * VRAM is lost or now.
1687  * returns true if vram is lost, false if not.
1688  */
1689 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1690 {
1691         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1692                         AMDGPU_RESET_MAGIC_NUM);
1693 }
1694
1695 /**
1696  * amdgpu_device_ip_late_set_cg_state - late init for clockgating
1697  *
1698  * @adev: amdgpu_device pointer
1699  *
1700  * Late initialization pass enabling clockgating for hardware IPs.
1701  * The list of all the hardware IPs that make up the asic is walked and the
1702  * set_clockgating_state callbacks are run.  This stage is run late
1703  * in the init process.
1704  * Returns 0 on success, negative error code on failure.
1705  */
1706 static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
1707 {
1708         int i = 0, r;
1709
1710         if (amdgpu_emu_mode == 1)
1711                 return 0;
1712
1713         for (i = 0; i < adev->num_ip_blocks; i++) {
1714                 if (!adev->ip_blocks[i].status.valid)
1715                         continue;
1716                 /* skip CG for VCE/UVD, it's handled specially */
1717                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1718                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1719                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1720                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1721                         /* enable clockgating to save power */
1722                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1723                                                                                      AMD_CG_STATE_GATE);
1724                         if (r) {
1725                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1726                                           adev->ip_blocks[i].version->funcs->name, r);
1727                                 return r;
1728                         }
1729                 }
1730         }
1731
1732         return 0;
1733 }
1734
1735 static int amdgpu_device_ip_late_set_pg_state(struct amdgpu_device *adev)
1736 {
1737         int i = 0, r;
1738
1739         if (amdgpu_emu_mode == 1)
1740                 return 0;
1741
1742         for (i = 0; i < adev->num_ip_blocks; i++) {
1743                 if (!adev->ip_blocks[i].status.valid)
1744                         continue;
1745                 /* skip CG for VCE/UVD, it's handled specially */
1746                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1747                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1748                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1749                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1750                         /* enable powergating to save power */
1751                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1752                                                                                      AMD_PG_STATE_GATE);
1753                         if (r) {
1754                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1755                                           adev->ip_blocks[i].version->funcs->name, r);
1756                                 return r;
1757                         }
1758                 }
1759         }
1760         return 0;
1761 }
1762
1763 /**
1764  * amdgpu_device_ip_late_init - run late init for hardware IPs
1765  *
1766  * @adev: amdgpu_device pointer
1767  *
1768  * Late initialization pass for hardware IPs.  The list of all the hardware
1769  * IPs that make up the asic is walked and the late_init callbacks are run.
1770  * late_init covers any special initialization that an IP requires
1771  * after all of the have been initialized or something that needs to happen
1772  * late in the init process.
1773  * Returns 0 on success, negative error code on failure.
1774  */
1775 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1776 {
1777         int i = 0, r;
1778
1779         for (i = 0; i < adev->num_ip_blocks; i++) {
1780                 if (!adev->ip_blocks[i].status.valid)
1781                         continue;
1782                 if (adev->ip_blocks[i].version->funcs->late_init) {
1783                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1784                         if (r) {
1785                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1786                                           adev->ip_blocks[i].version->funcs->name, r);
1787                                 return r;
1788                         }
1789                         adev->ip_blocks[i].status.late_initialized = true;
1790                 }
1791         }
1792
1793         amdgpu_device_ip_late_set_cg_state(adev);
1794         amdgpu_device_ip_late_set_pg_state(adev);
1795
1796         queue_delayed_work(system_wq, &adev->late_init_work,
1797                            msecs_to_jiffies(AMDGPU_RESUME_MS));
1798
1799         amdgpu_device_fill_reset_magic(adev);
1800
1801         return 0;
1802 }
1803
1804 /**
1805  * amdgpu_device_ip_fini - run fini for hardware IPs
1806  *
1807  * @adev: amdgpu_device pointer
1808  *
1809  * Main teardown pass for hardware IPs.  The list of all the hardware
1810  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1811  * are run.  hw_fini tears down the hardware associated with each IP
1812  * and sw_fini tears down any software state associated with each IP.
1813  * Returns 0 on success, negative error code on failure.
1814  */
1815 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1816 {
1817         int i, r;
1818
1819         amdgpu_amdkfd_device_fini(adev);
1820         /* need to disable SMC first */
1821         for (i = 0; i < adev->num_ip_blocks; i++) {
1822                 if (!adev->ip_blocks[i].status.hw)
1823                         continue;
1824                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC &&
1825                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1826                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1827                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1828                                                                                      AMD_CG_STATE_UNGATE);
1829                         if (r) {
1830                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1831                                           adev->ip_blocks[i].version->funcs->name, r);
1832                                 return r;
1833                         }
1834                         if (adev->powerplay.pp_funcs->set_powergating_by_smu)
1835                                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
1836                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1837                         /* XXX handle errors */
1838                         if (r) {
1839                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1840                                           adev->ip_blocks[i].version->funcs->name, r);
1841                         }
1842                         adev->ip_blocks[i].status.hw = false;
1843                         break;
1844                 }
1845         }
1846
1847         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1848                 if (!adev->ip_blocks[i].status.hw)
1849                         continue;
1850
1851                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1852                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1853                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1854                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1855                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1856                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1857                                                                                      AMD_CG_STATE_UNGATE);
1858                         if (r) {
1859                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1860                                           adev->ip_blocks[i].version->funcs->name, r);
1861                                 return r;
1862                         }
1863                 }
1864
1865                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1866                 /* XXX handle errors */
1867                 if (r) {
1868                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1869                                   adev->ip_blocks[i].version->funcs->name, r);
1870                 }
1871
1872                 adev->ip_blocks[i].status.hw = false;
1873         }
1874
1875
1876         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1877                 if (!adev->ip_blocks[i].status.sw)
1878                         continue;
1879
1880                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1881                         amdgpu_free_static_csa(adev);
1882                         amdgpu_device_wb_fini(adev);
1883                         amdgpu_device_vram_scratch_fini(adev);
1884                 }
1885
1886                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1887                 /* XXX handle errors */
1888                 if (r) {
1889                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1890                                   adev->ip_blocks[i].version->funcs->name, r);
1891                 }
1892                 adev->ip_blocks[i].status.sw = false;
1893                 adev->ip_blocks[i].status.valid = false;
1894         }
1895
1896         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1897                 if (!adev->ip_blocks[i].status.late_initialized)
1898                         continue;
1899                 if (adev->ip_blocks[i].version->funcs->late_fini)
1900                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1901                 adev->ip_blocks[i].status.late_initialized = false;
1902         }
1903
1904         if (amdgpu_sriov_vf(adev))
1905                 if (amdgpu_virt_release_full_gpu(adev, false))
1906                         DRM_ERROR("failed to release exclusive mode on fini\n");
1907
1908         return 0;
1909 }
1910
1911 /**
1912  * amdgpu_device_ip_late_init_func_handler - work handler for clockgating
1913  *
1914  * @work: work_struct
1915  *
1916  * Work handler for amdgpu_device_ip_late_set_cg_state.  We put the
1917  * clockgating setup into a worker thread to speed up driver init and
1918  * resume from suspend.
1919  */
1920 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1921 {
1922         struct amdgpu_device *adev =
1923                 container_of(work, struct amdgpu_device, late_init_work.work);
1924         int r;
1925
1926         r = amdgpu_ib_ring_tests(adev);
1927         if (r)
1928                 DRM_ERROR("ib ring test failed (%d).\n", r);
1929 }
1930
1931 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
1932 {
1933         struct amdgpu_device *adev =
1934                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
1935
1936         mutex_lock(&adev->gfx.gfx_off_mutex);
1937         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
1938                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
1939                         adev->gfx.gfx_off_state = true;
1940         }
1941         mutex_unlock(&adev->gfx.gfx_off_mutex);
1942 }
1943
1944 /**
1945  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
1946  *
1947  * @adev: amdgpu_device pointer
1948  *
1949  * Main suspend function for hardware IPs.  The list of all the hardware
1950  * IPs that make up the asic is walked, clockgating is disabled and the
1951  * suspend callbacks are run.  suspend puts the hardware and software state
1952  * in each IP into a state suitable for suspend.
1953  * Returns 0 on success, negative error code on failure.
1954  */
1955 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
1956 {
1957         int i, r;
1958
1959         if (amdgpu_sriov_vf(adev))
1960                 amdgpu_virt_request_full_gpu(adev, false);
1961
1962         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1963                 if (!adev->ip_blocks[i].status.valid)
1964                         continue;
1965                 /* displays are handled separately */
1966                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
1967                         /* ungate blocks so that suspend can properly shut them down */
1968                         if (adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1969                                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1970                                                                                              AMD_CG_STATE_UNGATE);
1971                                 if (r) {
1972                                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1973                                                   adev->ip_blocks[i].version->funcs->name, r);
1974                                 }
1975                         }
1976                         /* XXX handle errors */
1977                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
1978                         /* XXX handle errors */
1979                         if (r) {
1980                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1981                                           adev->ip_blocks[i].version->funcs->name, r);
1982                         }
1983                 }
1984         }
1985
1986         if (amdgpu_sriov_vf(adev))
1987                 amdgpu_virt_release_full_gpu(adev, false);
1988
1989         return 0;
1990 }
1991
1992 /**
1993  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
1994  *
1995  * @adev: amdgpu_device pointer
1996  *
1997  * Main suspend function for hardware IPs.  The list of all the hardware
1998  * IPs that make up the asic is walked, clockgating is disabled and the
1999  * suspend callbacks are run.  suspend puts the hardware and software state
2000  * in each IP into a state suitable for suspend.
2001  * Returns 0 on success, negative error code on failure.
2002  */
2003 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2004 {
2005         int i, r;
2006
2007         if (amdgpu_sriov_vf(adev))
2008                 amdgpu_virt_request_full_gpu(adev, false);
2009
2010         /* ungate SMC block first */
2011         r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
2012                                                    AMD_CG_STATE_UNGATE);
2013         if (r) {
2014                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
2015         }
2016
2017         /* call smu to disable gfx off feature first when suspend */
2018         if (adev->powerplay.pp_funcs->set_powergating_by_smu)
2019                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
2020
2021         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2022                 if (!adev->ip_blocks[i].status.valid)
2023                         continue;
2024                 /* displays are handled in phase1 */
2025                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2026                         continue;
2027                 /* ungate blocks so that suspend can properly shut them down */
2028                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC &&
2029                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2030                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2031                                                                                      AMD_CG_STATE_UNGATE);
2032                         if (r) {
2033                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
2034                                           adev->ip_blocks[i].version->funcs->name, r);
2035                         }
2036                 }
2037                 /* XXX handle errors */
2038                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2039                 /* XXX handle errors */
2040                 if (r) {
2041                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2042                                   adev->ip_blocks[i].version->funcs->name, r);
2043                 }
2044         }
2045
2046         if (amdgpu_sriov_vf(adev))
2047                 amdgpu_virt_release_full_gpu(adev, false);
2048
2049         return 0;
2050 }
2051
2052 /**
2053  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2054  *
2055  * @adev: amdgpu_device pointer
2056  *
2057  * Main suspend function for hardware IPs.  The list of all the hardware
2058  * IPs that make up the asic is walked, clockgating is disabled and the
2059  * suspend callbacks are run.  suspend puts the hardware and software state
2060  * in each IP into a state suitable for suspend.
2061  * Returns 0 on success, negative error code on failure.
2062  */
2063 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2064 {
2065         int r;
2066
2067         r = amdgpu_device_ip_suspend_phase1(adev);
2068         if (r)
2069                 return r;
2070         r = amdgpu_device_ip_suspend_phase2(adev);
2071
2072         return r;
2073 }
2074
2075 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2076 {
2077         int i, r;
2078
2079         static enum amd_ip_block_type ip_order[] = {
2080                 AMD_IP_BLOCK_TYPE_GMC,
2081                 AMD_IP_BLOCK_TYPE_COMMON,
2082                 AMD_IP_BLOCK_TYPE_PSP,
2083                 AMD_IP_BLOCK_TYPE_IH,
2084         };
2085
2086         for (i = 0; i < adev->num_ip_blocks; i++) {
2087                 int j;
2088                 struct amdgpu_ip_block *block;
2089
2090                 for (j = 0; j < adev->num_ip_blocks; j++) {
2091                         block = &adev->ip_blocks[j];
2092
2093                         if (block->version->type != ip_order[i] ||
2094                                 !block->status.valid)
2095                                 continue;
2096
2097                         r = block->version->funcs->hw_init(adev);
2098                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2099                         if (r)
2100                                 return r;
2101                 }
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2108 {
2109         int i, r;
2110
2111         static enum amd_ip_block_type ip_order[] = {
2112                 AMD_IP_BLOCK_TYPE_SMC,
2113                 AMD_IP_BLOCK_TYPE_DCE,
2114                 AMD_IP_BLOCK_TYPE_GFX,
2115                 AMD_IP_BLOCK_TYPE_SDMA,
2116                 AMD_IP_BLOCK_TYPE_UVD,
2117                 AMD_IP_BLOCK_TYPE_VCE
2118         };
2119
2120         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2121                 int j;
2122                 struct amdgpu_ip_block *block;
2123
2124                 for (j = 0; j < adev->num_ip_blocks; j++) {
2125                         block = &adev->ip_blocks[j];
2126
2127                         if (block->version->type != ip_order[i] ||
2128                                 !block->status.valid)
2129                                 continue;
2130
2131                         r = block->version->funcs->hw_init(adev);
2132                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2133                         if (r)
2134                                 return r;
2135                 }
2136         }
2137
2138         return 0;
2139 }
2140
2141 /**
2142  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2143  *
2144  * @adev: amdgpu_device pointer
2145  *
2146  * First resume function for hardware IPs.  The list of all the hardware
2147  * IPs that make up the asic is walked and the resume callbacks are run for
2148  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2149  * after a suspend and updates the software state as necessary.  This
2150  * function is also used for restoring the GPU after a GPU reset.
2151  * Returns 0 on success, negative error code on failure.
2152  */
2153 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2154 {
2155         int i, r;
2156
2157         for (i = 0; i < adev->num_ip_blocks; i++) {
2158                 if (!adev->ip_blocks[i].status.valid)
2159                         continue;
2160                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2161                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2162                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2163                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2164                         if (r) {
2165                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2166                                           adev->ip_blocks[i].version->funcs->name, r);
2167                                 return r;
2168                         }
2169                 }
2170         }
2171
2172         return 0;
2173 }
2174
2175 /**
2176  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2177  *
2178  * @adev: amdgpu_device pointer
2179  *
2180  * First resume function for hardware IPs.  The list of all the hardware
2181  * IPs that make up the asic is walked and the resume callbacks are run for
2182  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2183  * functional state after a suspend and updates the software state as
2184  * necessary.  This function is also used for restoring the GPU after a GPU
2185  * reset.
2186  * Returns 0 on success, negative error code on failure.
2187  */
2188 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2189 {
2190         int i, r;
2191
2192         for (i = 0; i < adev->num_ip_blocks; i++) {
2193                 if (!adev->ip_blocks[i].status.valid)
2194                         continue;
2195                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2196                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2197                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
2198                         continue;
2199                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2200                 if (r) {
2201                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2202                                   adev->ip_blocks[i].version->funcs->name, r);
2203                         return r;
2204                 }
2205         }
2206
2207         return 0;
2208 }
2209
2210 /**
2211  * amdgpu_device_ip_resume - run resume for hardware IPs
2212  *
2213  * @adev: amdgpu_device pointer
2214  *
2215  * Main resume function for hardware IPs.  The hardware IPs
2216  * are split into two resume functions because they are
2217  * are also used in in recovering from a GPU reset and some additional
2218  * steps need to be take between them.  In this case (S3/S4) they are
2219  * run sequentially.
2220  * Returns 0 on success, negative error code on failure.
2221  */
2222 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2223 {
2224         int r;
2225
2226         r = amdgpu_device_ip_resume_phase1(adev);
2227         if (r)
2228                 return r;
2229         r = amdgpu_device_ip_resume_phase2(adev);
2230
2231         return r;
2232 }
2233
2234 /**
2235  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2236  *
2237  * @adev: amdgpu_device pointer
2238  *
2239  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2240  */
2241 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2242 {
2243         if (amdgpu_sriov_vf(adev)) {
2244                 if (adev->is_atom_fw) {
2245                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2246                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2247                 } else {
2248                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2249                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2250                 }
2251
2252                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2253                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2254         }
2255 }
2256
2257 /**
2258  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2259  *
2260  * @asic_type: AMD asic type
2261  *
2262  * Check if there is DC (new modesetting infrastructre) support for an asic.
2263  * returns true if DC has support, false if not.
2264  */
2265 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2266 {
2267         switch (asic_type) {
2268 #if defined(CONFIG_DRM_AMD_DC)
2269         case CHIP_BONAIRE:
2270         case CHIP_KAVERI:
2271         case CHIP_KABINI:
2272         case CHIP_MULLINS:
2273                 /*
2274                  * We have systems in the wild with these ASICs that require
2275                  * LVDS and VGA support which is not supported with DC.
2276                  *
2277                  * Fallback to the non-DC driver here by default so as not to
2278                  * cause regressions.
2279                  */
2280                 return amdgpu_dc > 0;
2281         case CHIP_HAWAII:
2282         case CHIP_CARRIZO:
2283         case CHIP_STONEY:
2284         case CHIP_POLARIS10:
2285         case CHIP_POLARIS11:
2286         case CHIP_POLARIS12:
2287         case CHIP_VEGAM:
2288         case CHIP_TONGA:
2289         case CHIP_FIJI:
2290         case CHIP_VEGA10:
2291         case CHIP_VEGA12:
2292         case CHIP_VEGA20:
2293 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2294         case CHIP_RAVEN:
2295 #endif
2296                 return amdgpu_dc != 0;
2297 #endif
2298         default:
2299                 return false;
2300         }
2301 }
2302
2303 /**
2304  * amdgpu_device_has_dc_support - check if dc is supported
2305  *
2306  * @adev: amdgpu_device_pointer
2307  *
2308  * Returns true for supported, false for not supported
2309  */
2310 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2311 {
2312         if (amdgpu_sriov_vf(adev))
2313                 return false;
2314
2315         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2316 }
2317
2318 /**
2319  * amdgpu_device_init - initialize the driver
2320  *
2321  * @adev: amdgpu_device pointer
2322  * @ddev: drm dev pointer
2323  * @pdev: pci dev pointer
2324  * @flags: driver flags
2325  *
2326  * Initializes the driver info and hw (all asics).
2327  * Returns 0 for success or an error on failure.
2328  * Called at driver startup.
2329  */
2330 int amdgpu_device_init(struct amdgpu_device *adev,
2331                        struct drm_device *ddev,
2332                        struct pci_dev *pdev,
2333                        uint32_t flags)
2334 {
2335         int r, i;
2336         bool runtime = false;
2337         u32 max_MBps;
2338
2339         adev->shutdown = false;
2340         adev->dev = &pdev->dev;
2341         adev->ddev = ddev;
2342         adev->pdev = pdev;
2343         adev->flags = flags;
2344         adev->asic_type = flags & AMD_ASIC_MASK;
2345         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2346         if (amdgpu_emu_mode == 1)
2347                 adev->usec_timeout *= 2;
2348         adev->gmc.gart_size = 512 * 1024 * 1024;
2349         adev->accel_working = false;
2350         adev->num_rings = 0;
2351         adev->mman.buffer_funcs = NULL;
2352         adev->mman.buffer_funcs_ring = NULL;
2353         adev->vm_manager.vm_pte_funcs = NULL;
2354         adev->vm_manager.vm_pte_num_rings = 0;
2355         adev->gmc.gmc_funcs = NULL;
2356         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2357         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2358
2359         adev->smc_rreg = &amdgpu_invalid_rreg;
2360         adev->smc_wreg = &amdgpu_invalid_wreg;
2361         adev->pcie_rreg = &amdgpu_invalid_rreg;
2362         adev->pcie_wreg = &amdgpu_invalid_wreg;
2363         adev->pciep_rreg = &amdgpu_invalid_rreg;
2364         adev->pciep_wreg = &amdgpu_invalid_wreg;
2365         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2366         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2367         adev->didt_rreg = &amdgpu_invalid_rreg;
2368         adev->didt_wreg = &amdgpu_invalid_wreg;
2369         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2370         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2371         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2372         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2373
2374         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2375                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2376                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2377
2378         /* mutex initialization are all done here so we
2379          * can recall function without having locking issues */
2380         atomic_set(&adev->irq.ih.lock, 0);
2381         mutex_init(&adev->firmware.mutex);
2382         mutex_init(&adev->pm.mutex);
2383         mutex_init(&adev->gfx.gpu_clock_mutex);
2384         mutex_init(&adev->srbm_mutex);
2385         mutex_init(&adev->gfx.pipe_reserve_mutex);
2386         mutex_init(&adev->gfx.gfx_off_mutex);
2387         mutex_init(&adev->grbm_idx_mutex);
2388         mutex_init(&adev->mn_lock);
2389         mutex_init(&adev->virt.vf_errors.lock);
2390         hash_init(adev->mn_hash);
2391         mutex_init(&adev->lock_reset);
2392
2393         amdgpu_device_check_arguments(adev);
2394
2395         spin_lock_init(&adev->mmio_idx_lock);
2396         spin_lock_init(&adev->smc_idx_lock);
2397         spin_lock_init(&adev->pcie_idx_lock);
2398         spin_lock_init(&adev->uvd_ctx_idx_lock);
2399         spin_lock_init(&adev->didt_idx_lock);
2400         spin_lock_init(&adev->gc_cac_idx_lock);
2401         spin_lock_init(&adev->se_cac_idx_lock);
2402         spin_lock_init(&adev->audio_endpt_idx_lock);
2403         spin_lock_init(&adev->mm_stats.lock);
2404
2405         INIT_LIST_HEAD(&adev->shadow_list);
2406         mutex_init(&adev->shadow_list_lock);
2407
2408         INIT_LIST_HEAD(&adev->ring_lru_list);
2409         spin_lock_init(&adev->ring_lru_list_lock);
2410
2411         INIT_DELAYED_WORK(&adev->late_init_work,
2412                           amdgpu_device_ip_late_init_func_handler);
2413         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2414                           amdgpu_device_delay_enable_gfx_off);
2415
2416         adev->gfx.gfx_off_req_count = 1;
2417         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2418
2419         /* Registers mapping */
2420         /* TODO: block userspace mapping of io register */
2421         if (adev->asic_type >= CHIP_BONAIRE) {
2422                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2423                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2424         } else {
2425                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2426                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2427         }
2428
2429         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2430         if (adev->rmmio == NULL) {
2431                 return -ENOMEM;
2432         }
2433         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2434         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2435
2436         /* doorbell bar mapping */
2437         amdgpu_device_doorbell_init(adev);
2438
2439         /* io port mapping */
2440         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2441                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2442                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2443                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2444                         break;
2445                 }
2446         }
2447         if (adev->rio_mem == NULL)
2448                 DRM_INFO("PCI I/O BAR is not found.\n");
2449
2450         amdgpu_device_get_pcie_info(adev);
2451
2452         /* early init functions */
2453         r = amdgpu_device_ip_early_init(adev);
2454         if (r)
2455                 return r;
2456
2457         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2458         /* this will fail for cards that aren't VGA class devices, just
2459          * ignore it */
2460         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2461
2462         if (amdgpu_device_is_px(ddev))
2463                 runtime = true;
2464         if (!pci_is_thunderbolt_attached(adev->pdev))
2465                 vga_switcheroo_register_client(adev->pdev,
2466                                                &amdgpu_switcheroo_ops, runtime);
2467         if (runtime)
2468                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2469
2470         if (amdgpu_emu_mode == 1) {
2471                 /* post the asic on emulation mode */
2472                 emu_soc_asic_init(adev);
2473                 goto fence_driver_init;
2474         }
2475
2476         /* Read BIOS */
2477         if (!amdgpu_get_bios(adev)) {
2478                 r = -EINVAL;
2479                 goto failed;
2480         }
2481
2482         r = amdgpu_atombios_init(adev);
2483         if (r) {
2484                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2485                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2486                 goto failed;
2487         }
2488
2489         /* detect if we are with an SRIOV vbios */
2490         amdgpu_device_detect_sriov_bios(adev);
2491
2492         /* Post card if necessary */
2493         if (amdgpu_device_need_post(adev)) {
2494                 if (!adev->bios) {
2495                         dev_err(adev->dev, "no vBIOS found\n");
2496                         r = -EINVAL;
2497                         goto failed;
2498                 }
2499                 DRM_INFO("GPU posting now...\n");
2500                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2501                 if (r) {
2502                         dev_err(adev->dev, "gpu post error!\n");
2503                         goto failed;
2504                 }
2505         }
2506
2507         if (adev->is_atom_fw) {
2508                 /* Initialize clocks */
2509                 r = amdgpu_atomfirmware_get_clock_info(adev);
2510                 if (r) {
2511                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2512                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2513                         goto failed;
2514                 }
2515         } else {
2516                 /* Initialize clocks */
2517                 r = amdgpu_atombios_get_clock_info(adev);
2518                 if (r) {
2519                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2520                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2521                         goto failed;
2522                 }
2523                 /* init i2c buses */
2524                 if (!amdgpu_device_has_dc_support(adev))
2525                         amdgpu_atombios_i2c_init(adev);
2526         }
2527
2528 fence_driver_init:
2529         /* Fence driver */
2530         r = amdgpu_fence_driver_init(adev);
2531         if (r) {
2532                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2533                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2534                 goto failed;
2535         }
2536
2537         /* init the mode config */
2538         drm_mode_config_init(adev->ddev);
2539
2540         r = amdgpu_device_ip_init(adev);
2541         if (r) {
2542                 /* failed in exclusive mode due to timeout */
2543                 if (amdgpu_sriov_vf(adev) &&
2544                     !amdgpu_sriov_runtime(adev) &&
2545                     amdgpu_virt_mmio_blocked(adev) &&
2546                     !amdgpu_virt_wait_reset(adev)) {
2547                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2548                         /* Don't send request since VF is inactive. */
2549                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2550                         adev->virt.ops = NULL;
2551                         r = -EAGAIN;
2552                         goto failed;
2553                 }
2554                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2555                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2556                 goto failed;
2557         }
2558
2559         adev->accel_working = true;
2560
2561         amdgpu_vm_check_compute_bug(adev);
2562
2563         /* Initialize the buffer migration limit. */
2564         if (amdgpu_moverate >= 0)
2565                 max_MBps = amdgpu_moverate;
2566         else
2567                 max_MBps = 8; /* Allow 8 MB/s. */
2568         /* Get a log2 for easy divisions. */
2569         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2570
2571         r = amdgpu_ib_pool_init(adev);
2572         if (r) {
2573                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2574                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2575                 goto failed;
2576         }
2577
2578         amdgpu_fbdev_init(adev);
2579
2580         r = amdgpu_pm_sysfs_init(adev);
2581         if (r)
2582                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2583
2584         r = amdgpu_debugfs_gem_init(adev);
2585         if (r)
2586                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2587
2588         r = amdgpu_debugfs_regs_init(adev);
2589         if (r)
2590                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2591
2592         r = amdgpu_debugfs_firmware_init(adev);
2593         if (r)
2594                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2595
2596         r = amdgpu_debugfs_init(adev);
2597         if (r)
2598                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2599
2600         if ((amdgpu_testing & 1)) {
2601                 if (adev->accel_working)
2602                         amdgpu_test_moves(adev);
2603                 else
2604                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2605         }
2606         if (amdgpu_benchmarking) {
2607                 if (adev->accel_working)
2608                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2609                 else
2610                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2611         }
2612
2613         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2614          * explicit gating rather than handling it automatically.
2615          */
2616         r = amdgpu_device_ip_late_init(adev);
2617         if (r) {
2618                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2619                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2620                 goto failed;
2621         }
2622
2623         return 0;
2624
2625 failed:
2626         amdgpu_vf_error_trans_all(adev);
2627         if (runtime)
2628                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2629
2630         return r;
2631 }
2632
2633 /**
2634  * amdgpu_device_fini - tear down the driver
2635  *
2636  * @adev: amdgpu_device pointer
2637  *
2638  * Tear down the driver info (all asics).
2639  * Called at driver shutdown.
2640  */
2641 void amdgpu_device_fini(struct amdgpu_device *adev)
2642 {
2643         int r;
2644
2645         DRM_INFO("amdgpu: finishing device.\n");
2646         adev->shutdown = true;
2647         /* disable all interrupts */
2648         amdgpu_irq_disable_all(adev);
2649         if (adev->mode_info.mode_config_initialized){
2650                 if (!amdgpu_device_has_dc_support(adev))
2651                         drm_crtc_force_disable_all(adev->ddev);
2652                 else
2653                         drm_atomic_helper_shutdown(adev->ddev);
2654         }
2655         amdgpu_ib_pool_fini(adev);
2656         amdgpu_fence_driver_fini(adev);
2657         amdgpu_pm_sysfs_fini(adev);
2658         amdgpu_fbdev_fini(adev);
2659         r = amdgpu_device_ip_fini(adev);
2660         if (adev->firmware.gpu_info_fw) {
2661                 release_firmware(adev->firmware.gpu_info_fw);
2662                 adev->firmware.gpu_info_fw = NULL;
2663         }
2664         adev->accel_working = false;
2665         cancel_delayed_work_sync(&adev->late_init_work);
2666         /* free i2c buses */
2667         if (!amdgpu_device_has_dc_support(adev))
2668                 amdgpu_i2c_fini(adev);
2669
2670         if (amdgpu_emu_mode != 1)
2671                 amdgpu_atombios_fini(adev);
2672
2673         kfree(adev->bios);
2674         adev->bios = NULL;
2675         if (!pci_is_thunderbolt_attached(adev->pdev))
2676                 vga_switcheroo_unregister_client(adev->pdev);
2677         if (adev->flags & AMD_IS_PX)
2678                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2679         vga_client_register(adev->pdev, NULL, NULL, NULL);
2680         if (adev->rio_mem)
2681                 pci_iounmap(adev->pdev, adev->rio_mem);
2682         adev->rio_mem = NULL;
2683         iounmap(adev->rmmio);
2684         adev->rmmio = NULL;
2685         amdgpu_device_doorbell_fini(adev);
2686         amdgpu_debugfs_regs_cleanup(adev);
2687 }
2688
2689
2690 /*
2691  * Suspend & resume.
2692  */
2693 /**
2694  * amdgpu_device_suspend - initiate device suspend
2695  *
2696  * @dev: drm dev pointer
2697  * @suspend: suspend state
2698  * @fbcon : notify the fbdev of suspend
2699  *
2700  * Puts the hw in the suspend state (all asics).
2701  * Returns 0 for success or an error on failure.
2702  * Called at driver suspend.
2703  */
2704 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2705 {
2706         struct amdgpu_device *adev;
2707         struct drm_crtc *crtc;
2708         struct drm_connector *connector;
2709         int r;
2710
2711         if (dev == NULL || dev->dev_private == NULL) {
2712                 return -ENODEV;
2713         }
2714
2715         adev = dev->dev_private;
2716
2717         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2718                 return 0;
2719
2720         drm_kms_helper_poll_disable(dev);
2721
2722         if (fbcon)
2723                 amdgpu_fbdev_set_suspend(adev, 1);
2724
2725         if (!amdgpu_device_has_dc_support(adev)) {
2726                 /* turn off display hw */
2727                 drm_modeset_lock_all(dev);
2728                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2729                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2730                 }
2731                 drm_modeset_unlock_all(dev);
2732                         /* unpin the front buffers and cursors */
2733                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2734                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2735                         struct drm_framebuffer *fb = crtc->primary->fb;
2736                         struct amdgpu_bo *robj;
2737
2738                         if (amdgpu_crtc->cursor_bo) {
2739                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2740                                 r = amdgpu_bo_reserve(aobj, true);
2741                                 if (r == 0) {
2742                                         amdgpu_bo_unpin(aobj);
2743                                         amdgpu_bo_unreserve(aobj);
2744                                 }
2745                         }
2746
2747                         if (fb == NULL || fb->obj[0] == NULL) {
2748                                 continue;
2749                         }
2750                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2751                         /* don't unpin kernel fb objects */
2752                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2753                                 r = amdgpu_bo_reserve(robj, true);
2754                                 if (r == 0) {
2755                                         amdgpu_bo_unpin(robj);
2756                                         amdgpu_bo_unreserve(robj);
2757                                 }
2758                         }
2759                 }
2760         }
2761
2762         amdgpu_amdkfd_suspend(adev);
2763
2764         r = amdgpu_device_ip_suspend_phase1(adev);
2765
2766         /* evict vram memory */
2767         amdgpu_bo_evict_vram(adev);
2768
2769         amdgpu_fence_driver_suspend(adev);
2770
2771         r = amdgpu_device_ip_suspend_phase2(adev);
2772
2773         /* evict remaining vram memory
2774          * This second call to evict vram is to evict the gart page table
2775          * using the CPU.
2776          */
2777         amdgpu_bo_evict_vram(adev);
2778
2779         pci_save_state(dev->pdev);
2780         if (suspend) {
2781                 /* Shut down the device */
2782                 pci_disable_device(dev->pdev);
2783                 pci_set_power_state(dev->pdev, PCI_D3hot);
2784         } else {
2785                 r = amdgpu_asic_reset(adev);
2786                 if (r)
2787                         DRM_ERROR("amdgpu asic reset failed\n");
2788         }
2789
2790         return 0;
2791 }
2792
2793 /**
2794  * amdgpu_device_resume - initiate device resume
2795  *
2796  * @dev: drm dev pointer
2797  * @resume: resume state
2798  * @fbcon : notify the fbdev of resume
2799  *
2800  * Bring the hw back to operating state (all asics).
2801  * Returns 0 for success or an error on failure.
2802  * Called at driver resume.
2803  */
2804 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2805 {
2806         struct drm_connector *connector;
2807         struct amdgpu_device *adev = dev->dev_private;
2808         struct drm_crtc *crtc;
2809         int r = 0;
2810
2811         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2812                 return 0;
2813
2814         if (resume) {
2815                 pci_set_power_state(dev->pdev, PCI_D0);
2816                 pci_restore_state(dev->pdev);
2817                 r = pci_enable_device(dev->pdev);
2818                 if (r)
2819                         return r;
2820         }
2821
2822         /* post card */
2823         if (amdgpu_device_need_post(adev)) {
2824                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2825                 if (r)
2826                         DRM_ERROR("amdgpu asic init failed\n");
2827         }
2828
2829         r = amdgpu_device_ip_resume(adev);
2830         if (r) {
2831                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2832                 return r;
2833         }
2834         amdgpu_fence_driver_resume(adev);
2835
2836
2837         r = amdgpu_device_ip_late_init(adev);
2838         if (r)
2839                 return r;
2840
2841         if (!amdgpu_device_has_dc_support(adev)) {
2842                 /* pin cursors */
2843                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2844                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2845
2846                         if (amdgpu_crtc->cursor_bo) {
2847                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2848                                 r = amdgpu_bo_reserve(aobj, true);
2849                                 if (r == 0) {
2850                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2851                                         if (r != 0)
2852                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2853                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2854                                         amdgpu_bo_unreserve(aobj);
2855                                 }
2856                         }
2857                 }
2858         }
2859         r = amdgpu_amdkfd_resume(adev);
2860         if (r)
2861                 return r;
2862
2863         /* Make sure IB tests flushed */
2864         flush_delayed_work(&adev->late_init_work);
2865
2866         /* blat the mode back in */
2867         if (fbcon) {
2868                 if (!amdgpu_device_has_dc_support(adev)) {
2869                         /* pre DCE11 */
2870                         drm_helper_resume_force_mode(dev);
2871
2872                         /* turn on display hw */
2873                         drm_modeset_lock_all(dev);
2874                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2875                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2876                         }
2877                         drm_modeset_unlock_all(dev);
2878                 }
2879                 amdgpu_fbdev_set_suspend(adev, 0);
2880         }
2881
2882         drm_kms_helper_poll_enable(dev);
2883
2884         /*
2885          * Most of the connector probing functions try to acquire runtime pm
2886          * refs to ensure that the GPU is powered on when connector polling is
2887          * performed. Since we're calling this from a runtime PM callback,
2888          * trying to acquire rpm refs will cause us to deadlock.
2889          *
2890          * Since we're guaranteed to be holding the rpm lock, it's safe to
2891          * temporarily disable the rpm helpers so this doesn't deadlock us.
2892          */
2893 #ifdef CONFIG_PM
2894         dev->dev->power.disable_depth++;
2895 #endif
2896         if (!amdgpu_device_has_dc_support(adev))
2897                 drm_helper_hpd_irq_event(dev);
2898         else
2899                 drm_kms_helper_hotplug_event(dev);
2900 #ifdef CONFIG_PM
2901         dev->dev->power.disable_depth--;
2902 #endif
2903         return 0;
2904 }
2905
2906 /**
2907  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
2908  *
2909  * @adev: amdgpu_device pointer
2910  *
2911  * The list of all the hardware IPs that make up the asic is walked and
2912  * the check_soft_reset callbacks are run.  check_soft_reset determines
2913  * if the asic is still hung or not.
2914  * Returns true if any of the IPs are still in a hung state, false if not.
2915  */
2916 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2917 {
2918         int i;
2919         bool asic_hang = false;
2920
2921         if (amdgpu_sriov_vf(adev))
2922                 return true;
2923
2924         if (amdgpu_asic_need_full_reset(adev))
2925                 return true;
2926
2927         for (i = 0; i < adev->num_ip_blocks; i++) {
2928                 if (!adev->ip_blocks[i].status.valid)
2929                         continue;
2930                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2931                         adev->ip_blocks[i].status.hang =
2932                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2933                 if (adev->ip_blocks[i].status.hang) {
2934                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2935                         asic_hang = true;
2936                 }
2937         }
2938         return asic_hang;
2939 }
2940
2941 /**
2942  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
2943  *
2944  * @adev: amdgpu_device pointer
2945  *
2946  * The list of all the hardware IPs that make up the asic is walked and the
2947  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
2948  * handles any IP specific hardware or software state changes that are
2949  * necessary for a soft reset to succeed.
2950  * Returns 0 on success, negative error code on failure.
2951  */
2952 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
2953 {
2954         int i, r = 0;
2955
2956         for (i = 0; i < adev->num_ip_blocks; i++) {
2957                 if (!adev->ip_blocks[i].status.valid)
2958                         continue;
2959                 if (adev->ip_blocks[i].status.hang &&
2960                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2961                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2962                         if (r)
2963                                 return r;
2964                 }
2965         }
2966
2967         return 0;
2968 }
2969
2970 /**
2971  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
2972  *
2973  * @adev: amdgpu_device pointer
2974  *
2975  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
2976  * reset is necessary to recover.
2977  * Returns true if a full asic reset is required, false if not.
2978  */
2979 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
2980 {
2981         int i;
2982
2983         if (amdgpu_asic_need_full_reset(adev))
2984                 return true;
2985
2986         for (i = 0; i < adev->num_ip_blocks; i++) {
2987                 if (!adev->ip_blocks[i].status.valid)
2988                         continue;
2989                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2990                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2991                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2992                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2993                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2994                         if (adev->ip_blocks[i].status.hang) {
2995                                 DRM_INFO("Some block need full reset!\n");
2996                                 return true;
2997                         }
2998                 }
2999         }
3000         return false;
3001 }
3002
3003 /**
3004  * amdgpu_device_ip_soft_reset - do a soft reset
3005  *
3006  * @adev: amdgpu_device pointer
3007  *
3008  * The list of all the hardware IPs that make up the asic is walked and the
3009  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3010  * IP specific hardware or software state changes that are necessary to soft
3011  * reset the IP.
3012  * Returns 0 on success, negative error code on failure.
3013  */
3014 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3015 {
3016         int i, r = 0;
3017
3018         for (i = 0; i < adev->num_ip_blocks; i++) {
3019                 if (!adev->ip_blocks[i].status.valid)
3020                         continue;
3021                 if (adev->ip_blocks[i].status.hang &&
3022                     adev->ip_blocks[i].version->funcs->soft_reset) {
3023                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3024                         if (r)
3025                                 return r;
3026                 }
3027         }
3028
3029         return 0;
3030 }
3031
3032 /**
3033  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3034  *
3035  * @adev: amdgpu_device pointer
3036  *
3037  * The list of all the hardware IPs that make up the asic is walked and the
3038  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3039  * handles any IP specific hardware or software state changes that are
3040  * necessary after the IP has been soft reset.
3041  * Returns 0 on success, negative error code on failure.
3042  */
3043 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3044 {
3045         int i, r = 0;
3046
3047         for (i = 0; i < adev->num_ip_blocks; i++) {
3048                 if (!adev->ip_blocks[i].status.valid)
3049                         continue;
3050                 if (adev->ip_blocks[i].status.hang &&
3051                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3052                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3053                 if (r)
3054                         return r;
3055         }
3056
3057         return 0;
3058 }
3059
3060 /**
3061  * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers
3062  *
3063  * @adev: amdgpu_device pointer
3064  * @ring: amdgpu_ring for the engine handling the buffer operations
3065  * @bo: amdgpu_bo buffer whose shadow is being restored
3066  * @fence: dma_fence associated with the operation
3067  *
3068  * Restores the VRAM buffer contents from the shadow in GTT.  Used to
3069  * restore things like GPUVM page tables after a GPU reset where
3070  * the contents of VRAM might be lost.
3071  * Returns 0 on success, negative error code on failure.
3072  */
3073 static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev,
3074                                                   struct amdgpu_ring *ring,
3075                                                   struct amdgpu_bo *bo,
3076                                                   struct dma_fence **fence)
3077 {
3078         uint32_t domain;
3079         int r;
3080
3081         if (!bo->shadow)
3082                 return 0;
3083
3084         r = amdgpu_bo_reserve(bo, true);
3085         if (r)
3086                 return r;
3087         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
3088         /* if bo has been evicted, then no need to recover */
3089         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
3090                 r = amdgpu_bo_validate(bo->shadow);
3091                 if (r) {
3092                         DRM_ERROR("bo validate failed!\n");
3093                         goto err;
3094                 }
3095
3096                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
3097                                                  NULL, fence, true);
3098                 if (r) {
3099                         DRM_ERROR("recover page table failed!\n");
3100                         goto err;
3101                 }
3102         }
3103 err:
3104         amdgpu_bo_unreserve(bo);
3105         return r;
3106 }
3107
3108 /**
3109  * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents
3110  *
3111  * @adev: amdgpu_device pointer
3112  *
3113  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3114  * restore things like GPUVM page tables after a GPU reset where
3115  * the contents of VRAM might be lost.
3116  * Returns 0 on success, 1 on failure.
3117  */
3118 static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev)
3119 {
3120         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3121         struct amdgpu_bo *bo, *tmp;
3122         struct dma_fence *fence = NULL, *next = NULL;
3123         long r = 1;
3124         int i = 0;
3125         long tmo;
3126
3127         if (amdgpu_sriov_runtime(adev))
3128                 tmo = msecs_to_jiffies(8000);
3129         else
3130                 tmo = msecs_to_jiffies(100);
3131
3132         DRM_INFO("recover vram bo from shadow start\n");
3133         mutex_lock(&adev->shadow_list_lock);
3134         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3135                 next = NULL;
3136                 amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next);
3137                 if (fence) {
3138                         r = dma_fence_wait_timeout(fence, false, tmo);
3139                         if (r == 0)
3140                                 pr_err("wait fence %p[%d] timeout\n", fence, i);
3141                         else if (r < 0)
3142                                 pr_err("wait fence %p[%d] interrupted\n", fence, i);
3143                         if (r < 1) {
3144                                 dma_fence_put(fence);
3145                                 fence = next;
3146                                 break;
3147                         }
3148                         i++;
3149                 }
3150
3151                 dma_fence_put(fence);
3152                 fence = next;
3153         }
3154         mutex_unlock(&adev->shadow_list_lock);
3155
3156         if (fence) {
3157                 r = dma_fence_wait_timeout(fence, false, tmo);
3158                 if (r == 0)
3159                         pr_err("wait fence %p[%d] timeout\n", fence, i);
3160                 else if (r < 0)
3161                         pr_err("wait fence %p[%d] interrupted\n", fence, i);
3162
3163         }
3164         dma_fence_put(fence);
3165
3166         if (r > 0)
3167                 DRM_INFO("recover vram bo from shadow done\n");
3168         else
3169                 DRM_ERROR("recover vram bo from shadow failed\n");
3170
3171         return (r > 0) ? 0 : 1;
3172 }
3173
3174 /**
3175  * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough
3176  *
3177  * @adev: amdgpu device pointer
3178  *
3179  * attempt to do soft-reset or full-reset and reinitialize Asic
3180  * return 0 means succeeded otherwise failed
3181  */
3182 static int amdgpu_device_reset(struct amdgpu_device *adev)
3183 {
3184         bool need_full_reset, vram_lost = 0;
3185         int r;
3186
3187         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3188
3189         if (!need_full_reset) {
3190                 amdgpu_device_ip_pre_soft_reset(adev);
3191                 r = amdgpu_device_ip_soft_reset(adev);
3192                 amdgpu_device_ip_post_soft_reset(adev);
3193                 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3194                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
3195                         need_full_reset = true;
3196                 }
3197         }
3198
3199         if (need_full_reset) {
3200                 r = amdgpu_device_ip_suspend(adev);
3201
3202 retry:
3203                 r = amdgpu_asic_reset(adev);
3204                 /* post card */
3205                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
3206
3207                 if (!r) {
3208                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
3209                         r = amdgpu_device_ip_resume_phase1(adev);
3210                         if (r)
3211                                 goto out;
3212
3213                         vram_lost = amdgpu_device_check_vram_lost(adev);
3214                         if (vram_lost) {
3215                                 DRM_ERROR("VRAM is lost!\n");
3216                                 atomic_inc(&adev->vram_lost_counter);
3217                         }
3218
3219                         r = amdgpu_gtt_mgr_recover(
3220                                 &adev->mman.bdev.man[TTM_PL_TT]);
3221                         if (r)
3222                                 goto out;
3223
3224                         r = amdgpu_device_ip_resume_phase2(adev);
3225                         if (r)
3226                                 goto out;
3227
3228                         if (vram_lost)
3229                                 amdgpu_device_fill_reset_magic(adev);
3230                 }
3231         }
3232
3233 out:
3234         if (!r) {
3235                 amdgpu_irq_gpu_reset_resume_helper(adev);
3236                 r = amdgpu_ib_ring_tests(adev);
3237                 if (r) {
3238                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
3239                         r = amdgpu_device_ip_suspend(adev);
3240                         need_full_reset = true;
3241                         goto retry;
3242                 }
3243         }
3244
3245         if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost))
3246                 r = amdgpu_device_handle_vram_lost(adev);
3247
3248         return r;
3249 }
3250
3251 /**
3252  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3253  *
3254  * @adev: amdgpu device pointer
3255  * @from_hypervisor: request from hypervisor
3256  *
3257  * do VF FLR and reinitialize Asic
3258  * return 0 means succeeded otherwise failed
3259  */
3260 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3261                                      bool from_hypervisor)
3262 {
3263         int r;
3264
3265         if (from_hypervisor)
3266                 r = amdgpu_virt_request_full_gpu(adev, true);
3267         else
3268                 r = amdgpu_virt_reset_gpu(adev);
3269         if (r)
3270                 return r;
3271
3272         /* Resume IP prior to SMC */
3273         r = amdgpu_device_ip_reinit_early_sriov(adev);
3274         if (r)
3275                 goto error;
3276
3277         /* we need recover gart prior to run SMC/CP/SDMA resume */
3278         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3279
3280         /* now we are okay to resume SMC/CP/SDMA */
3281         r = amdgpu_device_ip_reinit_late_sriov(adev);
3282         if (r)
3283                 goto error;
3284
3285         amdgpu_irq_gpu_reset_resume_helper(adev);
3286         r = amdgpu_ib_ring_tests(adev);
3287
3288 error:
3289         amdgpu_virt_init_data_exchange(adev);
3290         amdgpu_virt_release_full_gpu(adev, true);
3291         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3292                 atomic_inc(&adev->vram_lost_counter);
3293                 r = amdgpu_device_handle_vram_lost(adev);
3294         }
3295
3296         return r;
3297 }
3298
3299 /**
3300  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3301  *
3302  * @adev: amdgpu device pointer
3303  * @job: which job trigger hang
3304  * @force: forces reset regardless of amdgpu_gpu_recovery
3305  *
3306  * Attempt to reset the GPU if it has hung (all asics).
3307  * Returns 0 for success or an error on failure.
3308  */
3309 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3310                               struct amdgpu_job *job, bool force)
3311 {
3312         int i, r, resched;
3313
3314         if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
3315                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
3316                 return 0;
3317         }
3318
3319         if (!force && (amdgpu_gpu_recovery == 0 ||
3320                         (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))) {
3321                 DRM_INFO("GPU recovery disabled.\n");
3322                 return 0;
3323         }
3324
3325         dev_info(adev->dev, "GPU reset begin!\n");
3326
3327         mutex_lock(&adev->lock_reset);
3328         atomic_inc(&adev->gpu_reset_counter);
3329         adev->in_gpu_reset = 1;
3330
3331         /* Block kfd */
3332         amdgpu_amdkfd_pre_reset(adev);
3333
3334         /* block TTM */
3335         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3336
3337         /* block all schedulers and reset given job's ring */
3338         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3339                 struct amdgpu_ring *ring = adev->rings[i];
3340
3341                 if (!ring || !ring->sched.thread)
3342                         continue;
3343
3344                 kthread_park(ring->sched.thread);
3345
3346                 if (job && job->base.sched == &ring->sched)
3347                         continue;
3348
3349                 drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
3350
3351                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3352                 amdgpu_fence_driver_force_completion(ring);
3353         }
3354
3355         if (amdgpu_sriov_vf(adev))
3356                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3357         else
3358                 r = amdgpu_device_reset(adev);
3359
3360         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3361                 struct amdgpu_ring *ring = adev->rings[i];
3362
3363                 if (!ring || !ring->sched.thread)
3364                         continue;
3365
3366                 /* only need recovery sched of the given job's ring
3367                  * or all rings (in the case @job is NULL)
3368                  * after above amdgpu_reset accomplished
3369                  */
3370                 if ((!job || job->base.sched == &ring->sched) && !r)
3371                         drm_sched_job_recovery(&ring->sched);
3372
3373                 kthread_unpark(ring->sched.thread);
3374         }
3375
3376         if (!amdgpu_device_has_dc_support(adev)) {
3377                 drm_helper_resume_force_mode(adev->ddev);
3378         }
3379
3380         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3381
3382         if (r) {
3383                 /* bad news, how to tell it to userspace ? */
3384                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3385                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3386         } else {
3387                 dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter));
3388         }
3389
3390         /*unlock kfd */
3391         amdgpu_amdkfd_post_reset(adev);
3392         amdgpu_vf_error_trans_all(adev);
3393         adev->in_gpu_reset = 0;
3394         mutex_unlock(&adev->lock_reset);
3395         return r;
3396 }
3397
3398 /**
3399  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3400  *
3401  * @adev: amdgpu_device pointer
3402  *
3403  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3404  * and lanes) of the slot the device is in. Handles APUs and
3405  * virtualized environments where PCIE config space may not be available.
3406  */
3407 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3408 {
3409         struct pci_dev *pdev;
3410         enum pci_bus_speed speed_cap;
3411         enum pcie_link_width link_width;
3412
3413         if (amdgpu_pcie_gen_cap)
3414                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3415
3416         if (amdgpu_pcie_lane_cap)
3417                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3418
3419         /* covers APUs as well */
3420         if (pci_is_root_bus(adev->pdev->bus)) {
3421                 if (adev->pm.pcie_gen_mask == 0)
3422                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3423                 if (adev->pm.pcie_mlw_mask == 0)
3424                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3425                 return;
3426         }
3427
3428         if (adev->pm.pcie_gen_mask == 0) {
3429                 /* asic caps */
3430                 pdev = adev->pdev;
3431                 speed_cap = pcie_get_speed_cap(pdev);
3432                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3433                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3434                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3435                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3436                 } else {
3437                         if (speed_cap == PCIE_SPEED_16_0GT)
3438                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3439                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3440                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3441                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3442                         else if (speed_cap == PCIE_SPEED_8_0GT)
3443                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3444                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3445                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3446                         else if (speed_cap == PCIE_SPEED_5_0GT)
3447                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3448                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3449                         else
3450                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3451                 }
3452                 /* platform caps */
3453                 pdev = adev->ddev->pdev->bus->self;
3454                 speed_cap = pcie_get_speed_cap(pdev);
3455                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3456                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3457                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3458                 } else {
3459                         if (speed_cap == PCIE_SPEED_16_0GT)
3460                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3461                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3462                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3463                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3464                         else if (speed_cap == PCIE_SPEED_8_0GT)
3465                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3466                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3467                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3468                         else if (speed_cap == PCIE_SPEED_5_0GT)
3469                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3470                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3471                         else
3472                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3473
3474                 }
3475         }
3476         if (adev->pm.pcie_mlw_mask == 0) {
3477                 pdev = adev->ddev->pdev->bus->self;
3478                 link_width = pcie_get_width_cap(pdev);
3479                 if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3480                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3481                 } else {
3482                         switch (link_width) {
3483                         case PCIE_LNK_X32:
3484                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3485                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3486                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3487                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3488                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3489                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3490                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3491                                 break;
3492                         case PCIE_LNK_X16:
3493                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3494                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3495                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3496                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3497                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3498                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3499                                 break;
3500                         case PCIE_LNK_X12:
3501                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3502                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3503                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3504                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3505                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3506                                 break;
3507                         case PCIE_LNK_X8:
3508                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3509                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3510                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3511                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3512                                 break;
3513                         case PCIE_LNK_X4:
3514                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3515                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3516                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3517                                 break;
3518                         case PCIE_LNK_X2:
3519                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3520                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3521                                 break;
3522                         case PCIE_LNK_X1:
3523                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3524                                 break;
3525                         default:
3526                                 break;
3527                         }
3528                 }
3529         }
3530 }
3531