2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
47 #ifdef CONFIG_DRM_AMDGPU_CIK
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
53 #include <linux/firmware.h>
55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
58 static const char *amdgpu_asic_name[] = {
79 bool amdgpu_device_is_px(struct drm_device *dev)
81 struct amdgpu_device *adev = dev->dev_private;
83 if (adev->flags & AMD_IS_PX)
89 * MMIO register access helper functions.
91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
96 if ((reg * 4) < adev->rmmio_size && !always_indirect)
97 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
101 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
102 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
103 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
104 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
106 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
111 bool always_indirect)
113 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
115 if ((reg * 4) < adev->rmmio_size && !always_indirect)
116 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
120 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
121 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
122 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
123 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
129 if ((reg * 4) < adev->rio_mem_size)
130 return ioread32(adev->rio_mem + (reg * 4));
132 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
133 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
140 if ((reg * 4) < adev->rio_mem_size)
141 iowrite32(v, adev->rio_mem + (reg * 4));
143 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
144 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
149 * amdgpu_mm_rdoorbell - read a doorbell dword
151 * @adev: amdgpu_device pointer
152 * @index: doorbell index
154 * Returns the value in the doorbell aperture at the
155 * requested doorbell index (CIK).
157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
159 if (index < adev->doorbell.num_doorbells) {
160 return readl(adev->doorbell.ptr + index);
162 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
168 * amdgpu_mm_wdoorbell - write a doorbell dword
170 * @adev: amdgpu_device pointer
171 * @index: doorbell index
174 * Writes @v to the doorbell aperture at the
175 * requested doorbell index (CIK).
177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
179 if (index < adev->doorbell.num_doorbells) {
180 writel(v, adev->doorbell.ptr + index);
182 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
187 * amdgpu_invalid_rreg - dummy reg read function
189 * @adev: amdgpu device pointer
190 * @reg: offset of register
192 * Dummy register read function. Used for register blocks
193 * that certain asics don't have (all asics).
194 * Returns the value in the register.
196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
198 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
204 * amdgpu_invalid_wreg - dummy reg write function
206 * @adev: amdgpu device pointer
207 * @reg: offset of register
208 * @v: value to write to the register
210 * Dummy register read function. Used for register blocks
211 * that certain asics don't have (all asics).
213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
215 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
221 * amdgpu_block_invalid_rreg - dummy reg read function
223 * @adev: amdgpu device pointer
224 * @block: offset of instance
225 * @reg: offset of register
227 * Dummy register read function. Used for register blocks
228 * that certain asics don't have (all asics).
229 * Returns the value in the register.
231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
232 uint32_t block, uint32_t reg)
234 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
241 * amdgpu_block_invalid_wreg - dummy reg write function
243 * @adev: amdgpu device pointer
244 * @block: offset of instance
245 * @reg: offset of register
246 * @v: value to write to the register
248 * Dummy register read function. Used for register blocks
249 * that certain asics don't have (all asics).
251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
253 uint32_t reg, uint32_t v)
255 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
264 if (adev->vram_scratch.robj == NULL) {
265 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
266 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
267 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
268 NULL, NULL, &adev->vram_scratch.robj);
274 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
275 if (unlikely(r != 0))
277 r = amdgpu_bo_pin(adev->vram_scratch.robj,
278 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
280 amdgpu_bo_unreserve(adev->vram_scratch.robj);
283 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
284 (void **)&adev->vram_scratch.ptr);
286 amdgpu_bo_unpin(adev->vram_scratch.robj);
287 amdgpu_bo_unreserve(adev->vram_scratch.robj);
292 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
296 if (adev->vram_scratch.robj == NULL) {
299 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
300 if (likely(r == 0)) {
301 amdgpu_bo_kunmap(adev->vram_scratch.robj);
302 amdgpu_bo_unpin(adev->vram_scratch.robj);
303 amdgpu_bo_unreserve(adev->vram_scratch.robj);
305 amdgpu_bo_unref(&adev->vram_scratch.robj);
309 * amdgpu_program_register_sequence - program an array of registers.
311 * @adev: amdgpu_device pointer
312 * @registers: pointer to the register array
313 * @array_size: size of the register array
315 * Programs an array or registers with and and or masks.
316 * This is a helper for setting golden registers.
318 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
319 const u32 *registers,
320 const u32 array_size)
322 u32 tmp, reg, and_mask, or_mask;
328 for (i = 0; i < array_size; i +=3) {
329 reg = registers[i + 0];
330 and_mask = registers[i + 1];
331 or_mask = registers[i + 2];
333 if (and_mask == 0xffffffff) {
344 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
346 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
350 * GPU doorbell aperture helpers function.
353 * amdgpu_doorbell_init - Init doorbell driver information.
355 * @adev: amdgpu_device pointer
357 * Init doorbell driver information (CIK)
358 * Returns 0 on success, error on failure.
360 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
362 /* doorbell bar mapping */
363 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
364 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
366 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
367 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
368 if (adev->doorbell.num_doorbells == 0)
371 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
372 if (adev->doorbell.ptr == NULL) {
375 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
376 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
382 * amdgpu_doorbell_fini - Tear down doorbell driver information.
384 * @adev: amdgpu_device pointer
386 * Tear down doorbell driver information (CIK)
388 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
390 iounmap(adev->doorbell.ptr);
391 adev->doorbell.ptr = NULL;
395 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
398 * @adev: amdgpu_device pointer
399 * @aperture_base: output returning doorbell aperture base physical address
400 * @aperture_size: output returning doorbell aperture size in bytes
401 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
403 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
404 * takes doorbells required for its own rings and reports the setup to amdkfd.
405 * amdgpu reserved doorbells are at the start of the doorbell aperture.
407 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
408 phys_addr_t *aperture_base,
409 size_t *aperture_size,
410 size_t *start_offset)
413 * The first num_doorbells are used by amdgpu.
414 * amdkfd takes whatever's left in the aperture.
416 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
417 *aperture_base = adev->doorbell.base;
418 *aperture_size = adev->doorbell.size;
419 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
429 * Writeback is the the method by which the the GPU updates special pages
430 * in memory with the status of certain GPU events (fences, ring pointers,
435 * amdgpu_wb_fini - Disable Writeback and free memory
437 * @adev: amdgpu_device pointer
439 * Disables Writeback and frees the Writeback memory (all asics).
440 * Used at driver shutdown.
442 static void amdgpu_wb_fini(struct amdgpu_device *adev)
444 if (adev->wb.wb_obj) {
445 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
446 amdgpu_bo_kunmap(adev->wb.wb_obj);
447 amdgpu_bo_unpin(adev->wb.wb_obj);
448 amdgpu_bo_unreserve(adev->wb.wb_obj);
450 amdgpu_bo_unref(&adev->wb.wb_obj);
452 adev->wb.wb_obj = NULL;
457 * amdgpu_wb_init- Init Writeback driver info and allocate memory
459 * @adev: amdgpu_device pointer
461 * Disables Writeback and frees the Writeback memory (all asics).
462 * Used at driver startup.
463 * Returns 0 on success or an -error on failure.
465 static int amdgpu_wb_init(struct amdgpu_device *adev)
469 if (adev->wb.wb_obj == NULL) {
470 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
471 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
474 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
477 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
478 if (unlikely(r != 0)) {
479 amdgpu_wb_fini(adev);
482 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
485 amdgpu_bo_unreserve(adev->wb.wb_obj);
486 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
487 amdgpu_wb_fini(adev);
490 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
491 amdgpu_bo_unreserve(adev->wb.wb_obj);
493 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
494 amdgpu_wb_fini(adev);
498 adev->wb.num_wb = AMDGPU_MAX_WB;
499 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
501 /* clear wb memory */
502 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
509 * amdgpu_wb_get - Allocate a wb entry
511 * @adev: amdgpu_device pointer
514 * Allocate a wb slot for use by the driver (all asics).
515 * Returns 0 on success or -EINVAL on failure.
517 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
519 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
520 if (offset < adev->wb.num_wb) {
521 __set_bit(offset, adev->wb.used);
530 * amdgpu_wb_free - Free a wb entry
532 * @adev: amdgpu_device pointer
535 * Free a wb slot allocated for use by the driver (all asics)
537 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
539 if (wb < adev->wb.num_wb)
540 __clear_bit(wb, adev->wb.used);
544 * amdgpu_vram_location - try to find VRAM location
545 * @adev: amdgpu device structure holding all necessary informations
546 * @mc: memory controller structure holding memory informations
547 * @base: base address at which to put VRAM
549 * Function will place try to place VRAM at base address provided
550 * as parameter (which is so far either PCI aperture address or
551 * for IGP TOM base address).
553 * If there is not enough space to fit the unvisible VRAM in the 32bits
554 * address space then we limit the VRAM size to the aperture.
556 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
557 * this shouldn't be a problem as we are using the PCI aperture as a reference.
558 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
561 * Note: we use mc_vram_size as on some board we need to program the mc to
562 * cover the whole aperture even if VRAM size is inferior to aperture size
563 * Novell bug 204882 + along with lots of ubuntu ones
565 * Note: when limiting vram it's safe to overwritte real_vram_size because
566 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
567 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
570 * Note: IGP TOM addr should be the same as the aperture addr, we don't
571 * explicitly check for that thought.
573 * FIXME: when reducing VRAM size align new size on power of 2.
575 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
577 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
579 mc->vram_start = base;
580 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
581 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
582 mc->real_vram_size = mc->aper_size;
583 mc->mc_vram_size = mc->aper_size;
585 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
586 if (limit && limit < mc->real_vram_size)
587 mc->real_vram_size = limit;
588 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
589 mc->mc_vram_size >> 20, mc->vram_start,
590 mc->vram_end, mc->real_vram_size >> 20);
594 * amdgpu_gtt_location - try to find GTT location
595 * @adev: amdgpu device structure holding all necessary informations
596 * @mc: memory controller structure holding memory informations
598 * Function will place try to place GTT before or after VRAM.
600 * If GTT size is bigger than space left then we ajust GTT size.
601 * Thus function will never fails.
603 * FIXME: when reducing GTT size align new size on power of 2.
605 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
607 u64 size_af, size_bf;
609 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
610 size_bf = mc->vram_start & ~mc->gtt_base_align;
611 if (size_bf > size_af) {
612 if (mc->gtt_size > size_bf) {
613 dev_warn(adev->dev, "limiting GTT\n");
614 mc->gtt_size = size_bf;
616 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
618 if (mc->gtt_size > size_af) {
619 dev_warn(adev->dev, "limiting GTT\n");
620 mc->gtt_size = size_af;
622 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
624 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
625 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
626 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
630 * GPU helpers function.
633 * amdgpu_card_posted - check if the hw has already been initialized
635 * @adev: amdgpu_device pointer
637 * Check if the asic has been initialized (all asics).
638 * Used at driver startup.
639 * Returns true if initialized or false if not.
641 bool amdgpu_card_posted(struct amdgpu_device *adev)
645 /* then check MEM_SIZE, in case the crtcs are off */
646 reg = RREG32(mmCONFIG_MEMSIZE);
655 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
657 if (amdgpu_sriov_vf(adev))
660 if (amdgpu_passthrough(adev)) {
661 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
662 * some old smc fw still need driver do vPost otherwise gpu hang, while
663 * those smc fw version above 22.15 doesn't have this flaw, so we force
664 * vpost executed for smc version below 22.15
666 if (adev->asic_type == CHIP_FIJI) {
669 err = reject_firmware(&adev->pm.fw, "/*(DEBLOBBED)*/", adev->dev);
670 /* force vPost if error occured */
674 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
675 if (fw_ver < 0x00160e00)
679 return !amdgpu_card_posted(adev);
683 * amdgpu_dummy_page_init - init dummy page used by the driver
685 * @adev: amdgpu_device pointer
687 * Allocate the dummy page used by the driver (all asics).
688 * This dummy page is used by the driver as a filler for gart entries
689 * when pages are taken out of the GART
690 * Returns 0 on sucess, -ENOMEM on failure.
692 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
694 if (adev->dummy_page.page)
696 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
697 if (adev->dummy_page.page == NULL)
699 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
700 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
701 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
702 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
703 __free_page(adev->dummy_page.page);
704 adev->dummy_page.page = NULL;
711 * amdgpu_dummy_page_fini - free dummy page used by the driver
713 * @adev: amdgpu_device pointer
715 * Frees the dummy page used by the driver (all asics).
717 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
719 if (adev->dummy_page.page == NULL)
721 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
722 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
723 __free_page(adev->dummy_page.page);
724 adev->dummy_page.page = NULL;
728 /* ATOM accessor methods */
730 * ATOM is an interpreted byte code stored in tables in the vbios. The
731 * driver registers callbacks to access registers and the interpreter
732 * in the driver parses the tables and executes then to program specific
733 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
734 * atombios.h, and atom.c
738 * cail_pll_read - read PLL register
740 * @info: atom card_info pointer
741 * @reg: PLL register offset
743 * Provides a PLL register accessor for the atom interpreter (r4xx+).
744 * Returns the value of the PLL register.
746 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
752 * cail_pll_write - write PLL register
754 * @info: atom card_info pointer
755 * @reg: PLL register offset
756 * @val: value to write to the pll register
758 * Provides a PLL register accessor for the atom interpreter (r4xx+).
760 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
766 * cail_mc_read - read MC (Memory Controller) register
768 * @info: atom card_info pointer
769 * @reg: MC register offset
771 * Provides an MC register accessor for the atom interpreter (r4xx+).
772 * Returns the value of the MC register.
774 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
780 * cail_mc_write - write MC (Memory Controller) register
782 * @info: atom card_info pointer
783 * @reg: MC register offset
784 * @val: value to write to the pll register
786 * Provides a MC register accessor for the atom interpreter (r4xx+).
788 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
794 * cail_reg_write - write MMIO register
796 * @info: atom card_info pointer
797 * @reg: MMIO register offset
798 * @val: value to write to the pll register
800 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
802 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
804 struct amdgpu_device *adev = info->dev->dev_private;
810 * cail_reg_read - read MMIO register
812 * @info: atom card_info pointer
813 * @reg: MMIO register offset
815 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
816 * Returns the value of the MMIO register.
818 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
820 struct amdgpu_device *adev = info->dev->dev_private;
828 * cail_ioreg_write - write IO register
830 * @info: atom card_info pointer
831 * @reg: IO register offset
832 * @val: value to write to the pll register
834 * Provides a IO register accessor for the atom interpreter (r4xx+).
836 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
838 struct amdgpu_device *adev = info->dev->dev_private;
844 * cail_ioreg_read - read IO register
846 * @info: atom card_info pointer
847 * @reg: IO register offset
849 * Provides an IO register accessor for the atom interpreter (r4xx+).
850 * Returns the value of the IO register.
852 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
854 struct amdgpu_device *adev = info->dev->dev_private;
862 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
864 * @adev: amdgpu_device pointer
866 * Frees the driver info and register access callbacks for the ATOM
867 * interpreter (r4xx+).
868 * Called at driver shutdown.
870 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
872 if (adev->mode_info.atom_context) {
873 kfree(adev->mode_info.atom_context->scratch);
874 kfree(adev->mode_info.atom_context->iio);
876 kfree(adev->mode_info.atom_context);
877 adev->mode_info.atom_context = NULL;
878 kfree(adev->mode_info.atom_card_info);
879 adev->mode_info.atom_card_info = NULL;
883 * amdgpu_atombios_init - init the driver info and callbacks for atombios
885 * @adev: amdgpu_device pointer
887 * Initializes the driver info and register access callbacks for the
888 * ATOM interpreter (r4xx+).
889 * Returns 0 on sucess, -ENOMEM on failure.
890 * Called at driver startup.
892 static int amdgpu_atombios_init(struct amdgpu_device *adev)
894 struct card_info *atom_card_info =
895 kzalloc(sizeof(struct card_info), GFP_KERNEL);
900 adev->mode_info.atom_card_info = atom_card_info;
901 atom_card_info->dev = adev->ddev;
902 atom_card_info->reg_read = cail_reg_read;
903 atom_card_info->reg_write = cail_reg_write;
904 /* needed for iio ops */
906 atom_card_info->ioreg_read = cail_ioreg_read;
907 atom_card_info->ioreg_write = cail_ioreg_write;
909 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
910 atom_card_info->ioreg_read = cail_reg_read;
911 atom_card_info->ioreg_write = cail_reg_write;
913 atom_card_info->mc_read = cail_mc_read;
914 atom_card_info->mc_write = cail_mc_write;
915 atom_card_info->pll_read = cail_pll_read;
916 atom_card_info->pll_write = cail_pll_write;
918 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
919 if (!adev->mode_info.atom_context) {
920 amdgpu_atombios_fini(adev);
924 mutex_init(&adev->mode_info.atom_context->mutex);
925 amdgpu_atombios_scratch_regs_init(adev);
926 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
930 /* if we get transitioned to only one device, take VGA back */
932 * amdgpu_vga_set_decode - enable/disable vga decode
934 * @cookie: amdgpu_device pointer
935 * @state: enable/disable vga decode
937 * Enable/disable vga decode (all asics).
938 * Returns VGA resource flags.
940 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
942 struct amdgpu_device *adev = cookie;
943 amdgpu_asic_set_vga_state(adev, state);
945 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
946 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
948 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
952 * amdgpu_check_pot_argument - check that argument is a power of two
954 * @arg: value to check
956 * Validates that a certain argument is a power of two (all asics).
957 * Returns true if argument is valid.
959 static bool amdgpu_check_pot_argument(int arg)
961 return (arg & (arg - 1)) == 0;
965 * amdgpu_check_arguments - validate module params
967 * @adev: amdgpu_device pointer
969 * Validates certain module parameters and updates
970 * the associated values used by the driver (all asics).
972 static void amdgpu_check_arguments(struct amdgpu_device *adev)
974 if (amdgpu_sched_jobs < 4) {
975 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
977 amdgpu_sched_jobs = 4;
978 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
979 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
981 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
984 if (amdgpu_gart_size != -1) {
985 /* gtt size must be greater or equal to 32M */
986 if (amdgpu_gart_size < 32) {
987 dev_warn(adev->dev, "gart size (%d) too small\n",
989 amdgpu_gart_size = -1;
993 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
994 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
999 if (amdgpu_vm_size < 1) {
1000 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1006 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1008 if (amdgpu_vm_size > 1024) {
1009 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1014 /* defines number of bits in page table versus page directory,
1015 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1016 * page table and the remaining bits are in the page directory */
1017 if (amdgpu_vm_block_size == -1) {
1019 /* Total bits covered by PD + PTs */
1020 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1022 /* Make sure the PD is 4K in size up to 8GB address space.
1023 Above that split equal between PD and PTs */
1024 if (amdgpu_vm_size <= 8)
1025 amdgpu_vm_block_size = bits - 9;
1027 amdgpu_vm_block_size = (bits + 3) / 2;
1029 } else if (amdgpu_vm_block_size < 9) {
1030 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1031 amdgpu_vm_block_size);
1032 amdgpu_vm_block_size = 9;
1035 if (amdgpu_vm_block_size > 24 ||
1036 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1037 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1038 amdgpu_vm_block_size);
1039 amdgpu_vm_block_size = 9;
1044 * amdgpu_switcheroo_set_state - set switcheroo state
1046 * @pdev: pci dev pointer
1047 * @state: vga_switcheroo state
1049 * Callback for the switcheroo driver. Suspends or resumes the
1050 * the asics before or after it is powered up using ACPI methods.
1052 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1054 struct drm_device *dev = pci_get_drvdata(pdev);
1056 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1059 if (state == VGA_SWITCHEROO_ON) {
1060 unsigned d3_delay = dev->pdev->d3_delay;
1062 printk(KERN_INFO "amdgpu: switched on\n");
1063 /* don't suspend or resume card normally */
1064 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1066 amdgpu_device_resume(dev, true, true);
1068 dev->pdev->d3_delay = d3_delay;
1070 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1071 drm_kms_helper_poll_enable(dev);
1073 printk(KERN_INFO "amdgpu: switched off\n");
1074 drm_kms_helper_poll_disable(dev);
1075 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1076 amdgpu_device_suspend(dev, true, true);
1077 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1082 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1084 * @pdev: pci dev pointer
1086 * Callback for the switcheroo driver. Check of the switcheroo
1087 * state can be changed.
1088 * Returns true if the state can be changed, false if not.
1090 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1092 struct drm_device *dev = pci_get_drvdata(pdev);
1095 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1096 * locking inversion with the driver load path. And the access here is
1097 * completely racy anyway. So don't bother with locking for now.
1099 return dev->open_count == 0;
1102 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1103 .set_gpu_state = amdgpu_switcheroo_set_state,
1105 .can_switch = amdgpu_switcheroo_can_switch,
1108 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1109 enum amd_ip_block_type block_type,
1110 enum amd_clockgating_state state)
1114 for (i = 0; i < adev->num_ip_blocks; i++) {
1115 if (!adev->ip_block_status[i].valid)
1117 if (adev->ip_blocks[i].type == block_type) {
1118 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1128 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1129 enum amd_ip_block_type block_type,
1130 enum amd_powergating_state state)
1134 for (i = 0; i < adev->num_ip_blocks; i++) {
1135 if (!adev->ip_block_status[i].valid)
1137 if (adev->ip_blocks[i].type == block_type) {
1138 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1148 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1149 enum amd_ip_block_type block_type)
1153 for (i = 0; i < adev->num_ip_blocks; i++) {
1154 if (!adev->ip_block_status[i].valid)
1156 if (adev->ip_blocks[i].type == block_type) {
1157 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1167 bool amdgpu_is_idle(struct amdgpu_device *adev,
1168 enum amd_ip_block_type block_type)
1172 for (i = 0; i < adev->num_ip_blocks; i++) {
1173 if (!adev->ip_block_status[i].valid)
1175 if (adev->ip_blocks[i].type == block_type)
1176 return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1182 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1183 struct amdgpu_device *adev,
1184 enum amd_ip_block_type type)
1188 for (i = 0; i < adev->num_ip_blocks; i++)
1189 if (adev->ip_blocks[i].type == type)
1190 return &adev->ip_blocks[i];
1196 * amdgpu_ip_block_version_cmp
1198 * @adev: amdgpu_device pointer
1199 * @type: enum amd_ip_block_type
1200 * @major: major version
1201 * @minor: minor version
1203 * return 0 if equal or greater
1204 * return 1 if smaller or the ip_block doesn't exist
1206 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1207 enum amd_ip_block_type type,
1208 u32 major, u32 minor)
1210 const struct amdgpu_ip_block_version *ip_block;
1211 ip_block = amdgpu_get_ip_block(adev, type);
1213 if (ip_block && ((ip_block->major > major) ||
1214 ((ip_block->major == major) &&
1215 (ip_block->minor >= minor))))
1221 static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev)
1223 adev->enable_virtual_display = false;
1225 if (amdgpu_virtual_display) {
1226 struct drm_device *ddev = adev->ddev;
1227 const char *pci_address_name = pci_name(ddev->pdev);
1228 char *pciaddstr, *pciaddstr_tmp, *pciaddname;
1230 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1231 pciaddstr_tmp = pciaddstr;
1232 while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) {
1233 if (!strcmp(pci_address_name, pciaddname)) {
1234 adev->enable_virtual_display = true;
1239 DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n",
1240 amdgpu_virtual_display, pci_address_name,
1241 adev->enable_virtual_display);
1247 static int amdgpu_early_init(struct amdgpu_device *adev)
1251 amdgpu_whether_enable_virtual_display(adev);
1253 switch (adev->asic_type) {
1257 case CHIP_POLARIS11:
1258 case CHIP_POLARIS10:
1261 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1262 adev->family = AMDGPU_FAMILY_CZ;
1264 adev->family = AMDGPU_FAMILY_VI;
1266 r = vi_set_ip_blocks(adev);
1270 #ifdef CONFIG_DRM_AMDGPU_SI
1276 adev->family = AMDGPU_FAMILY_SI;
1277 r = si_set_ip_blocks(adev);
1282 #ifdef CONFIG_DRM_AMDGPU_CIK
1288 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1289 adev->family = AMDGPU_FAMILY_CI;
1291 adev->family = AMDGPU_FAMILY_KV;
1293 r = cik_set_ip_blocks(adev);
1299 /* FIXME: not supported yet */
1303 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1304 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1305 if (adev->ip_block_status == NULL)
1308 if (adev->ip_blocks == NULL) {
1309 DRM_ERROR("No IP blocks found!\n");
1313 for (i = 0; i < adev->num_ip_blocks; i++) {
1314 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1315 DRM_ERROR("disabled ip block: %d\n", i);
1316 adev->ip_block_status[i].valid = false;
1318 if (adev->ip_blocks[i].funcs->early_init) {
1319 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1321 adev->ip_block_status[i].valid = false;
1323 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1326 adev->ip_block_status[i].valid = true;
1329 adev->ip_block_status[i].valid = true;
1334 adev->cg_flags &= amdgpu_cg_mask;
1335 adev->pg_flags &= amdgpu_pg_mask;
1340 static int amdgpu_init(struct amdgpu_device *adev)
1344 for (i = 0; i < adev->num_ip_blocks; i++) {
1345 if (!adev->ip_block_status[i].valid)
1347 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1349 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1352 adev->ip_block_status[i].sw = true;
1353 /* need to do gmc hw init early so we can allocate gpu mem */
1354 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1355 r = amdgpu_vram_scratch_init(adev);
1357 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1360 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1362 DRM_ERROR("hw_init %d failed %d\n", i, r);
1365 r = amdgpu_wb_init(adev);
1367 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1370 adev->ip_block_status[i].hw = true;
1374 for (i = 0; i < adev->num_ip_blocks; i++) {
1375 if (!adev->ip_block_status[i].sw)
1377 /* gmc hw init is done early */
1378 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1380 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1382 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1385 adev->ip_block_status[i].hw = true;
1391 static int amdgpu_late_init(struct amdgpu_device *adev)
1395 for (i = 0; i < adev->num_ip_blocks; i++) {
1396 if (!adev->ip_block_status[i].valid)
1398 if (adev->ip_blocks[i].funcs->late_init) {
1399 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1401 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1404 adev->ip_block_status[i].late_initialized = true;
1406 /* skip CG for VCE/UVD, it's handled specially */
1407 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1408 adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1409 /* enable clockgating to save power */
1410 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1413 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1414 adev->ip_blocks[i].funcs->name, r);
1423 static int amdgpu_fini(struct amdgpu_device *adev)
1427 /* need to disable SMC first */
1428 for (i = 0; i < adev->num_ip_blocks; i++) {
1429 if (!adev->ip_block_status[i].hw)
1431 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
1432 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1433 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1434 AMD_CG_STATE_UNGATE);
1436 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1437 adev->ip_blocks[i].funcs->name, r);
1440 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1441 /* XXX handle errors */
1443 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1444 adev->ip_blocks[i].funcs->name, r);
1446 adev->ip_block_status[i].hw = false;
1451 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1452 if (!adev->ip_block_status[i].hw)
1454 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1455 amdgpu_wb_fini(adev);
1456 amdgpu_vram_scratch_fini(adev);
1458 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1459 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1460 AMD_CG_STATE_UNGATE);
1462 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1465 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1466 /* XXX handle errors */
1468 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1470 adev->ip_block_status[i].hw = false;
1473 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1474 if (!adev->ip_block_status[i].sw)
1476 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1477 /* XXX handle errors */
1479 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1481 adev->ip_block_status[i].sw = false;
1482 adev->ip_block_status[i].valid = false;
1485 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1486 if (!adev->ip_block_status[i].late_initialized)
1488 if (adev->ip_blocks[i].funcs->late_fini)
1489 adev->ip_blocks[i].funcs->late_fini((void *)adev);
1490 adev->ip_block_status[i].late_initialized = false;
1496 int amdgpu_suspend(struct amdgpu_device *adev)
1500 /* ungate SMC block first */
1501 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1502 AMD_CG_STATE_UNGATE);
1504 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1507 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1508 if (!adev->ip_block_status[i].valid)
1510 /* ungate blocks so that suspend can properly shut them down */
1511 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1512 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1513 AMD_CG_STATE_UNGATE);
1515 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1518 /* XXX handle errors */
1519 r = adev->ip_blocks[i].funcs->suspend(adev);
1520 /* XXX handle errors */
1522 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1529 static int amdgpu_resume(struct amdgpu_device *adev)
1533 for (i = 0; i < adev->num_ip_blocks; i++) {
1534 if (!adev->ip_block_status[i].valid)
1536 r = adev->ip_blocks[i].funcs->resume(adev);
1538 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1546 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1548 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1549 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1553 * amdgpu_device_init - initialize the driver
1555 * @adev: amdgpu_device pointer
1556 * @pdev: drm dev pointer
1557 * @pdev: pci dev pointer
1558 * @flags: driver flags
1560 * Initializes the driver info and hw (all asics).
1561 * Returns 0 for success or an error on failure.
1562 * Called at driver startup.
1564 int amdgpu_device_init(struct amdgpu_device *adev,
1565 struct drm_device *ddev,
1566 struct pci_dev *pdev,
1570 bool runtime = false;
1573 adev->shutdown = false;
1574 adev->dev = &pdev->dev;
1577 adev->flags = flags;
1578 adev->asic_type = flags & AMD_ASIC_MASK;
1579 adev->is_atom_bios = false;
1580 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1581 adev->mc.gtt_size = 512 * 1024 * 1024;
1582 adev->accel_working = false;
1583 adev->num_rings = 0;
1584 adev->mman.buffer_funcs = NULL;
1585 adev->mman.buffer_funcs_ring = NULL;
1586 adev->vm_manager.vm_pte_funcs = NULL;
1587 adev->vm_manager.vm_pte_num_rings = 0;
1588 adev->gart.gart_funcs = NULL;
1589 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1591 adev->smc_rreg = &amdgpu_invalid_rreg;
1592 adev->smc_wreg = &amdgpu_invalid_wreg;
1593 adev->pcie_rreg = &amdgpu_invalid_rreg;
1594 adev->pcie_wreg = &amdgpu_invalid_wreg;
1595 adev->pciep_rreg = &amdgpu_invalid_rreg;
1596 adev->pciep_wreg = &amdgpu_invalid_wreg;
1597 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1598 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1599 adev->didt_rreg = &amdgpu_invalid_rreg;
1600 adev->didt_wreg = &amdgpu_invalid_wreg;
1601 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1602 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1603 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1604 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1607 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1608 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1609 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1611 /* mutex initialization are all done here so we
1612 * can recall function without having locking issues */
1613 mutex_init(&adev->vm_manager.lock);
1614 atomic_set(&adev->irq.ih.lock, 0);
1615 mutex_init(&adev->pm.mutex);
1616 mutex_init(&adev->gfx.gpu_clock_mutex);
1617 mutex_init(&adev->srbm_mutex);
1618 mutex_init(&adev->grbm_idx_mutex);
1619 mutex_init(&adev->mn_lock);
1620 hash_init(adev->mn_hash);
1622 amdgpu_check_arguments(adev);
1624 /* Registers mapping */
1625 /* TODO: block userspace mapping of io register */
1626 spin_lock_init(&adev->mmio_idx_lock);
1627 spin_lock_init(&adev->smc_idx_lock);
1628 spin_lock_init(&adev->pcie_idx_lock);
1629 spin_lock_init(&adev->uvd_ctx_idx_lock);
1630 spin_lock_init(&adev->didt_idx_lock);
1631 spin_lock_init(&adev->gc_cac_idx_lock);
1632 spin_lock_init(&adev->audio_endpt_idx_lock);
1633 spin_lock_init(&adev->mm_stats.lock);
1635 INIT_LIST_HEAD(&adev->shadow_list);
1636 mutex_init(&adev->shadow_list_lock);
1638 INIT_LIST_HEAD(&adev->gtt_list);
1639 spin_lock_init(&adev->gtt_list_lock);
1641 if (adev->asic_type >= CHIP_BONAIRE) {
1642 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1643 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1645 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1646 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1649 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1650 if (adev->rmmio == NULL) {
1653 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1654 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1656 if (adev->asic_type >= CHIP_BONAIRE)
1657 /* doorbell bar mapping */
1658 amdgpu_doorbell_init(adev);
1660 /* io port mapping */
1661 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1662 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1663 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1664 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1668 if (adev->rio_mem == NULL)
1669 DRM_ERROR("Unable to find PCI I/O BAR\n");
1671 /* early init functions */
1672 r = amdgpu_early_init(adev);
1676 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1677 /* this will fail for cards that aren't VGA class devices, just
1679 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1681 if (amdgpu_device_is_px(ddev))
1683 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1685 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1688 if (!amdgpu_get_bios(adev)) {
1692 /* Must be an ATOMBIOS */
1693 if (!adev->is_atom_bios) {
1694 dev_err(adev->dev, "Expecting atombios for GPU\n");
1698 r = amdgpu_atombios_init(adev);
1700 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1704 /* detect if we are with an SRIOV vbios */
1705 amdgpu_device_detect_sriov_bios(adev);
1707 /* Post card if necessary */
1708 if (amdgpu_vpost_needed(adev)) {
1710 dev_err(adev->dev, "no vBIOS found\n");
1714 DRM_INFO("GPU posting now...\n");
1715 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1717 dev_err(adev->dev, "gpu post error!\n");
1721 DRM_INFO("GPU post is not needed\n");
1724 /* Initialize clocks */
1725 r = amdgpu_atombios_get_clock_info(adev);
1727 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1730 /* init i2c buses */
1731 amdgpu_atombios_i2c_init(adev);
1734 r = amdgpu_fence_driver_init(adev);
1736 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1740 /* init the mode config */
1741 drm_mode_config_init(adev->ddev);
1743 r = amdgpu_init(adev);
1745 dev_err(adev->dev, "amdgpu_init failed\n");
1750 adev->accel_working = true;
1752 /* Initialize the buffer migration limit. */
1753 if (amdgpu_moverate >= 0)
1754 max_MBps = amdgpu_moverate;
1756 max_MBps = 8; /* Allow 8 MB/s. */
1757 /* Get a log2 for easy divisions. */
1758 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1760 amdgpu_fbdev_init(adev);
1762 r = amdgpu_ib_pool_init(adev);
1764 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1768 r = amdgpu_ib_ring_tests(adev);
1770 DRM_ERROR("ib ring test failed (%d).\n", r);
1772 r = amdgpu_gem_debugfs_init(adev);
1774 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1777 r = amdgpu_debugfs_regs_init(adev);
1779 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1782 r = amdgpu_debugfs_firmware_init(adev);
1784 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1788 if ((amdgpu_testing & 1)) {
1789 if (adev->accel_working)
1790 amdgpu_test_moves(adev);
1792 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1794 if ((amdgpu_testing & 2)) {
1795 if (adev->accel_working)
1796 amdgpu_test_syncing(adev);
1798 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1800 if (amdgpu_benchmarking) {
1801 if (adev->accel_working)
1802 amdgpu_benchmark(adev, amdgpu_benchmarking);
1804 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1807 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1808 * explicit gating rather than handling it automatically.
1810 r = amdgpu_late_init(adev);
1812 dev_err(adev->dev, "amdgpu_late_init failed\n");
1820 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1824 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1827 * amdgpu_device_fini - tear down the driver
1829 * @adev: amdgpu_device pointer
1831 * Tear down the driver info (all asics).
1832 * Called at driver shutdown.
1834 void amdgpu_device_fini(struct amdgpu_device *adev)
1838 DRM_INFO("amdgpu: finishing device.\n");
1839 adev->shutdown = true;
1840 drm_crtc_force_disable_all(adev->ddev);
1841 /* evict vram memory */
1842 amdgpu_bo_evict_vram(adev);
1843 amdgpu_ib_pool_fini(adev);
1844 amdgpu_fence_driver_fini(adev);
1845 amdgpu_fbdev_fini(adev);
1846 r = amdgpu_fini(adev);
1847 kfree(adev->ip_block_status);
1848 adev->ip_block_status = NULL;
1849 adev->accel_working = false;
1850 /* free i2c buses */
1851 amdgpu_i2c_fini(adev);
1852 amdgpu_atombios_fini(adev);
1855 vga_switcheroo_unregister_client(adev->pdev);
1856 if (adev->flags & AMD_IS_PX)
1857 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1858 vga_client_register(adev->pdev, NULL, NULL, NULL);
1860 pci_iounmap(adev->pdev, adev->rio_mem);
1861 adev->rio_mem = NULL;
1862 iounmap(adev->rmmio);
1864 if (adev->asic_type >= CHIP_BONAIRE)
1865 amdgpu_doorbell_fini(adev);
1866 amdgpu_debugfs_regs_cleanup(adev);
1867 amdgpu_debugfs_remove_files(adev);
1875 * amdgpu_device_suspend - initiate device suspend
1877 * @pdev: drm dev pointer
1878 * @state: suspend state
1880 * Puts the hw in the suspend state (all asics).
1881 * Returns 0 for success or an error on failure.
1882 * Called at driver suspend.
1884 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1886 struct amdgpu_device *adev;
1887 struct drm_crtc *crtc;
1888 struct drm_connector *connector;
1891 if (dev == NULL || dev->dev_private == NULL) {
1895 adev = dev->dev_private;
1897 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1900 drm_kms_helper_poll_disable(dev);
1902 /* turn off display hw */
1903 drm_modeset_lock_all(dev);
1904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1905 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1907 drm_modeset_unlock_all(dev);
1909 /* unpin the front buffers and cursors */
1910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1911 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1912 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1913 struct amdgpu_bo *robj;
1915 if (amdgpu_crtc->cursor_bo) {
1916 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1917 r = amdgpu_bo_reserve(aobj, false);
1919 amdgpu_bo_unpin(aobj);
1920 amdgpu_bo_unreserve(aobj);
1924 if (rfb == NULL || rfb->obj == NULL) {
1927 robj = gem_to_amdgpu_bo(rfb->obj);
1928 /* don't unpin kernel fb objects */
1929 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1930 r = amdgpu_bo_reserve(robj, false);
1932 amdgpu_bo_unpin(robj);
1933 amdgpu_bo_unreserve(robj);
1937 /* evict vram memory */
1938 amdgpu_bo_evict_vram(adev);
1940 amdgpu_fence_driver_suspend(adev);
1942 r = amdgpu_suspend(adev);
1944 /* evict remaining vram memory */
1945 amdgpu_bo_evict_vram(adev);
1947 amdgpu_atombios_scratch_regs_save(adev);
1948 pci_save_state(dev->pdev);
1950 /* Shut down the device */
1951 pci_disable_device(dev->pdev);
1952 pci_set_power_state(dev->pdev, PCI_D3hot);
1954 r = amdgpu_asic_reset(adev);
1956 DRM_ERROR("amdgpu asic reset failed\n");
1961 amdgpu_fbdev_set_suspend(adev, 1);
1968 * amdgpu_device_resume - initiate device resume
1970 * @pdev: drm dev pointer
1972 * Bring the hw back to operating state (all asics).
1973 * Returns 0 for success or an error on failure.
1974 * Called at driver resume.
1976 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
1978 struct drm_connector *connector;
1979 struct amdgpu_device *adev = dev->dev_private;
1980 struct drm_crtc *crtc;
1983 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1990 pci_set_power_state(dev->pdev, PCI_D0);
1991 pci_restore_state(dev->pdev);
1992 r = pci_enable_device(dev->pdev);
1999 amdgpu_atombios_scratch_regs_restore(adev);
2002 if (!amdgpu_card_posted(adev) || !resume) {
2003 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2005 DRM_ERROR("amdgpu asic init failed\n");
2008 r = amdgpu_resume(adev);
2010 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2012 amdgpu_fence_driver_resume(adev);
2015 r = amdgpu_ib_ring_tests(adev);
2017 DRM_ERROR("ib ring test failed (%d).\n", r);
2020 r = amdgpu_late_init(adev);
2028 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2029 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2031 if (amdgpu_crtc->cursor_bo) {
2032 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2033 r = amdgpu_bo_reserve(aobj, false);
2035 r = amdgpu_bo_pin(aobj,
2036 AMDGPU_GEM_DOMAIN_VRAM,
2037 &amdgpu_crtc->cursor_addr);
2039 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2040 amdgpu_bo_unreserve(aobj);
2045 /* blat the mode back in */
2047 drm_helper_resume_force_mode(dev);
2048 /* turn on display hw */
2049 drm_modeset_lock_all(dev);
2050 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2051 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2053 drm_modeset_unlock_all(dev);
2056 drm_kms_helper_poll_enable(dev);
2059 * Most of the connector probing functions try to acquire runtime pm
2060 * refs to ensure that the GPU is powered on when connector polling is
2061 * performed. Since we're calling this from a runtime PM callback,
2062 * trying to acquire rpm refs will cause us to deadlock.
2064 * Since we're guaranteed to be holding the rpm lock, it's safe to
2065 * temporarily disable the rpm helpers so this doesn't deadlock us.
2068 dev->dev->power.disable_depth++;
2070 drm_helper_hpd_irq_event(dev);
2072 dev->dev->power.disable_depth--;
2076 amdgpu_fbdev_set_suspend(adev, 0);
2083 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2086 bool asic_hang = false;
2088 for (i = 0; i < adev->num_ip_blocks; i++) {
2089 if (!adev->ip_block_status[i].valid)
2091 if (adev->ip_blocks[i].funcs->check_soft_reset)
2092 adev->ip_block_status[i].hang =
2093 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2094 if (adev->ip_block_status[i].hang) {
2095 DRM_INFO("IP block:%d is hang!\n", i);
2102 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2106 for (i = 0; i < adev->num_ip_blocks; i++) {
2107 if (!adev->ip_block_status[i].valid)
2109 if (adev->ip_block_status[i].hang &&
2110 adev->ip_blocks[i].funcs->pre_soft_reset) {
2111 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2120 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2124 for (i = 0; i < adev->num_ip_blocks; i++) {
2125 if (!adev->ip_block_status[i].valid)
2127 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2128 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2129 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2130 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2131 if (adev->ip_block_status[i].hang) {
2132 DRM_INFO("Some block need full reset!\n");
2140 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2144 for (i = 0; i < adev->num_ip_blocks; i++) {
2145 if (!adev->ip_block_status[i].valid)
2147 if (adev->ip_block_status[i].hang &&
2148 adev->ip_blocks[i].funcs->soft_reset) {
2149 r = adev->ip_blocks[i].funcs->soft_reset(adev);
2158 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2162 for (i = 0; i < adev->num_ip_blocks; i++) {
2163 if (!adev->ip_block_status[i].valid)
2165 if (adev->ip_block_status[i].hang &&
2166 adev->ip_blocks[i].funcs->post_soft_reset)
2167 r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2175 bool amdgpu_need_backup(struct amdgpu_device *adev)
2177 if (adev->flags & AMD_IS_APU)
2180 return amdgpu_lockup_timeout > 0 ? true : false;
2183 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2184 struct amdgpu_ring *ring,
2185 struct amdgpu_bo *bo,
2186 struct fence **fence)
2194 r = amdgpu_bo_reserve(bo, false);
2197 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2198 /* if bo has been evicted, then no need to recover */
2199 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2200 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2203 DRM_ERROR("recover page table failed!\n");
2208 amdgpu_bo_unreserve(bo);
2213 * amdgpu_gpu_reset - reset the asic
2215 * @adev: amdgpu device pointer
2217 * Attempt the reset the GPU if it has hung (all asics).
2218 * Returns 0 for success or an error on failure.
2220 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2224 bool need_full_reset;
2226 if (!amdgpu_check_soft_reset(adev)) {
2227 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2231 atomic_inc(&adev->gpu_reset_counter);
2234 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2236 /* block scheduler */
2237 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2238 struct amdgpu_ring *ring = adev->rings[i];
2240 if (!ring || !ring->sched.thread)
2242 kthread_park(ring->sched.thread);
2243 amd_sched_hw_job_reset(&ring->sched);
2245 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2246 amdgpu_fence_driver_force_completion(adev);
2248 need_full_reset = amdgpu_need_full_reset(adev);
2250 if (!need_full_reset) {
2251 amdgpu_pre_soft_reset(adev);
2252 r = amdgpu_soft_reset(adev);
2253 amdgpu_post_soft_reset(adev);
2254 if (r || amdgpu_check_soft_reset(adev)) {
2255 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2256 need_full_reset = true;
2260 if (need_full_reset) {
2261 r = amdgpu_suspend(adev);
2264 /* Disable fb access */
2265 if (adev->mode_info.num_crtc) {
2266 struct amdgpu_mode_mc_save save;
2267 amdgpu_display_stop_mc_access(adev, &save);
2268 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2270 amdgpu_atombios_scratch_regs_save(adev);
2271 r = amdgpu_asic_reset(adev);
2272 amdgpu_atombios_scratch_regs_restore(adev);
2274 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2277 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2278 r = amdgpu_resume(adev);
2282 amdgpu_irq_gpu_reset_resume_helper(adev);
2283 if (need_full_reset && amdgpu_need_backup(adev)) {
2284 r = amdgpu_ttm_recover_gart(adev);
2286 DRM_ERROR("gart recovery failed!!!\n");
2288 r = amdgpu_ib_ring_tests(adev);
2290 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2291 r = amdgpu_suspend(adev);
2292 need_full_reset = true;
2296 * recovery vm page tables, since we cannot depend on VRAM is
2297 * consistent after gpu full reset.
2299 if (need_full_reset && amdgpu_need_backup(adev)) {
2300 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2301 struct amdgpu_bo *bo, *tmp;
2302 struct fence *fence = NULL, *next = NULL;
2304 DRM_INFO("recover vram bo from shadow\n");
2305 mutex_lock(&adev->shadow_list_lock);
2306 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2307 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2309 r = fence_wait(fence, false);
2311 WARN(r, "recovery from shadow isn't comleted\n");
2319 mutex_unlock(&adev->shadow_list_lock);
2321 r = fence_wait(fence, false);
2323 WARN(r, "recovery from shadow isn't comleted\n");
2327 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2328 struct amdgpu_ring *ring = adev->rings[i];
2330 if (!ring || !ring->sched.thread)
2333 amd_sched_job_recovery(&ring->sched);
2334 kthread_unpark(ring->sched.thread);
2337 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2338 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2339 if (adev->rings[i] && adev->rings[i]->sched.thread) {
2340 kthread_unpark(adev->rings[i]->sched.thread);
2345 drm_helper_resume_force_mode(adev->ddev);
2347 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2349 /* bad news, how to tell it to userspace ? */
2350 dev_info(adev->dev, "GPU reset failed\n");
2356 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2361 if (amdgpu_pcie_gen_cap)
2362 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2364 if (amdgpu_pcie_lane_cap)
2365 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2367 /* covers APUs as well */
2368 if (pci_is_root_bus(adev->pdev->bus)) {
2369 if (adev->pm.pcie_gen_mask == 0)
2370 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2371 if (adev->pm.pcie_mlw_mask == 0)
2372 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2376 if (adev->pm.pcie_gen_mask == 0) {
2377 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2379 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2380 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2381 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2383 if (mask & DRM_PCIE_SPEED_25)
2384 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2385 if (mask & DRM_PCIE_SPEED_50)
2386 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2387 if (mask & DRM_PCIE_SPEED_80)
2388 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2390 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2393 if (adev->pm.pcie_mlw_mask == 0) {
2394 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2398 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2399 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2400 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2401 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2402 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2403 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2404 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2407 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2408 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2409 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2410 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2411 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2412 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2415 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2416 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2417 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2418 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2419 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2422 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2423 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2424 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2425 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2428 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2429 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2430 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2433 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2434 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2437 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2443 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2451 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2452 const struct drm_info_list *files,
2457 for (i = 0; i < adev->debugfs_count; i++) {
2458 if (adev->debugfs[i].files == files) {
2459 /* Already registered */
2464 i = adev->debugfs_count + 1;
2465 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2466 DRM_ERROR("Reached maximum number of debugfs components.\n");
2467 DRM_ERROR("Report so we increase "
2468 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2471 adev->debugfs[adev->debugfs_count].files = files;
2472 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2473 adev->debugfs_count = i;
2474 #if defined(CONFIG_DEBUG_FS)
2475 drm_debugfs_create_files(files, nfiles,
2476 adev->ddev->control->debugfs_root,
2477 adev->ddev->control);
2478 drm_debugfs_create_files(files, nfiles,
2479 adev->ddev->primary->debugfs_root,
2480 adev->ddev->primary);
2485 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2487 #if defined(CONFIG_DEBUG_FS)
2490 for (i = 0; i < adev->debugfs_count; i++) {
2491 drm_debugfs_remove_files(adev->debugfs[i].files,
2492 adev->debugfs[i].num_files,
2493 adev->ddev->control);
2494 drm_debugfs_remove_files(adev->debugfs[i].files,
2495 adev->debugfs[i].num_files,
2496 adev->ddev->primary);
2501 #if defined(CONFIG_DEBUG_FS)
2503 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2504 size_t size, loff_t *pos)
2506 struct amdgpu_device *adev = f->f_inode->i_private;
2509 bool pm_pg_lock, use_bank;
2510 unsigned instance_bank, sh_bank, se_bank;
2512 if (size & 0x3 || *pos & 0x3)
2515 /* are we reading registers for which a PG lock is necessary? */
2516 pm_pg_lock = (*pos >> 23) & 1;
2518 if (*pos & (1ULL << 62)) {
2519 se_bank = (*pos >> 24) & 0x3FF;
2520 sh_bank = (*pos >> 34) & 0x3FF;
2521 instance_bank = (*pos >> 44) & 0x3FF;
2530 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2531 se_bank >= adev->gfx.config.max_shader_engines)
2533 mutex_lock(&adev->grbm_idx_mutex);
2534 amdgpu_gfx_select_se_sh(adev, se_bank,
2535 sh_bank, instance_bank);
2539 mutex_lock(&adev->pm.mutex);
2544 if (*pos > adev->rmmio_size)
2547 value = RREG32(*pos >> 2);
2548 r = put_user(value, (uint32_t *)buf);
2562 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2563 mutex_unlock(&adev->grbm_idx_mutex);
2567 mutex_unlock(&adev->pm.mutex);
2572 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2573 size_t size, loff_t *pos)
2575 struct amdgpu_device *adev = f->f_inode->i_private;
2579 if (size & 0x3 || *pos & 0x3)
2585 if (*pos > adev->rmmio_size)
2588 r = get_user(value, (uint32_t *)buf);
2592 WREG32(*pos >> 2, value);
2603 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2604 size_t size, loff_t *pos)
2606 struct amdgpu_device *adev = f->f_inode->i_private;
2610 if (size & 0x3 || *pos & 0x3)
2616 value = RREG32_PCIE(*pos >> 2);
2617 r = put_user(value, (uint32_t *)buf);
2630 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2631 size_t size, loff_t *pos)
2633 struct amdgpu_device *adev = f->f_inode->i_private;
2637 if (size & 0x3 || *pos & 0x3)
2643 r = get_user(value, (uint32_t *)buf);
2647 WREG32_PCIE(*pos >> 2, value);
2658 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2659 size_t size, loff_t *pos)
2661 struct amdgpu_device *adev = f->f_inode->i_private;
2665 if (size & 0x3 || *pos & 0x3)
2671 value = RREG32_DIDT(*pos >> 2);
2672 r = put_user(value, (uint32_t *)buf);
2685 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2686 size_t size, loff_t *pos)
2688 struct amdgpu_device *adev = f->f_inode->i_private;
2692 if (size & 0x3 || *pos & 0x3)
2698 r = get_user(value, (uint32_t *)buf);
2702 WREG32_DIDT(*pos >> 2, value);
2713 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2714 size_t size, loff_t *pos)
2716 struct amdgpu_device *adev = f->f_inode->i_private;
2720 if (size & 0x3 || *pos & 0x3)
2726 value = RREG32_SMC(*pos);
2727 r = put_user(value, (uint32_t *)buf);
2740 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2741 size_t size, loff_t *pos)
2743 struct amdgpu_device *adev = f->f_inode->i_private;
2747 if (size & 0x3 || *pos & 0x3)
2753 r = get_user(value, (uint32_t *)buf);
2757 WREG32_SMC(*pos, value);
2768 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2769 size_t size, loff_t *pos)
2771 struct amdgpu_device *adev = f->f_inode->i_private;
2774 uint32_t *config, no_regs = 0;
2776 if (size & 0x3 || *pos & 0x3)
2779 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2783 /* version, increment each time something is added */
2784 config[no_regs++] = 2;
2785 config[no_regs++] = adev->gfx.config.max_shader_engines;
2786 config[no_regs++] = adev->gfx.config.max_tile_pipes;
2787 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2788 config[no_regs++] = adev->gfx.config.max_sh_per_se;
2789 config[no_regs++] = adev->gfx.config.max_backends_per_se;
2790 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2791 config[no_regs++] = adev->gfx.config.max_gprs;
2792 config[no_regs++] = adev->gfx.config.max_gs_threads;
2793 config[no_regs++] = adev->gfx.config.max_hw_contexts;
2794 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2795 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2796 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2797 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2798 config[no_regs++] = adev->gfx.config.num_tile_pipes;
2799 config[no_regs++] = adev->gfx.config.backend_enable_mask;
2800 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2801 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2802 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2803 config[no_regs++] = adev->gfx.config.num_gpus;
2804 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2805 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2806 config[no_regs++] = adev->gfx.config.gb_addr_config;
2807 config[no_regs++] = adev->gfx.config.num_rbs;
2810 config[no_regs++] = adev->rev_id;
2811 config[no_regs++] = adev->pg_flags;
2812 config[no_regs++] = adev->cg_flags;
2815 config[no_regs++] = adev->family;
2816 config[no_regs++] = adev->external_rev_id;
2818 while (size && (*pos < no_regs * 4)) {
2821 value = config[*pos >> 2];
2822 r = put_user(value, (uint32_t *)buf);
2838 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2839 size_t size, loff_t *pos)
2841 struct amdgpu_device *adev = f->f_inode->i_private;
2845 if (size != 4 || *pos & 0x3)
2848 /* convert offset to sensor number */
2851 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2852 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2857 r = put_user(value, (int32_t *)buf);
2862 static const struct file_operations amdgpu_debugfs_regs_fops = {
2863 .owner = THIS_MODULE,
2864 .read = amdgpu_debugfs_regs_read,
2865 .write = amdgpu_debugfs_regs_write,
2866 .llseek = default_llseek
2868 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2869 .owner = THIS_MODULE,
2870 .read = amdgpu_debugfs_regs_didt_read,
2871 .write = amdgpu_debugfs_regs_didt_write,
2872 .llseek = default_llseek
2874 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2875 .owner = THIS_MODULE,
2876 .read = amdgpu_debugfs_regs_pcie_read,
2877 .write = amdgpu_debugfs_regs_pcie_write,
2878 .llseek = default_llseek
2880 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2881 .owner = THIS_MODULE,
2882 .read = amdgpu_debugfs_regs_smc_read,
2883 .write = amdgpu_debugfs_regs_smc_write,
2884 .llseek = default_llseek
2887 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2888 .owner = THIS_MODULE,
2889 .read = amdgpu_debugfs_gca_config_read,
2890 .llseek = default_llseek
2893 static const struct file_operations amdgpu_debugfs_sensors_fops = {
2894 .owner = THIS_MODULE,
2895 .read = amdgpu_debugfs_sensor_read,
2896 .llseek = default_llseek
2899 static const struct file_operations *debugfs_regs[] = {
2900 &amdgpu_debugfs_regs_fops,
2901 &amdgpu_debugfs_regs_didt_fops,
2902 &amdgpu_debugfs_regs_pcie_fops,
2903 &amdgpu_debugfs_regs_smc_fops,
2904 &amdgpu_debugfs_gca_config_fops,
2905 &amdgpu_debugfs_sensors_fops,
2908 static const char *debugfs_regs_names[] = {
2913 "amdgpu_gca_config",
2917 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2919 struct drm_minor *minor = adev->ddev->primary;
2920 struct dentry *ent, *root = minor->debugfs_root;
2923 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2924 ent = debugfs_create_file(debugfs_regs_names[i],
2925 S_IFREG | S_IRUGO, root,
2926 adev, debugfs_regs[i]);
2928 for (j = 0; j < i; j++) {
2929 debugfs_remove(adev->debugfs_regs[i]);
2930 adev->debugfs_regs[i] = NULL;
2932 return PTR_ERR(ent);
2936 i_size_write(ent->d_inode, adev->rmmio_size);
2937 adev->debugfs_regs[i] = ent;
2943 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2947 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2948 if (adev->debugfs_regs[i]) {
2949 debugfs_remove(adev->debugfs_regs[i]);
2950 adev->debugfs_regs[i] = NULL;
2955 int amdgpu_debugfs_init(struct drm_minor *minor)
2960 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2964 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2968 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }