2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_edid.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/amdgpu_drm.h>
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
38 #include <linux/pm_runtime.h>
40 void amdgpu_connector_hotplug(struct drm_connector *connector)
42 struct drm_device *dev = connector->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
46 /* bail if the connector does not have hpd pin, e.g.,
49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
54 /* if the connector is already off, don't turn it back on */
55 if (connector->dpms != DRM_MODE_DPMS_ON)
58 /* just deal with DP (not eDP) here. */
59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60 struct amdgpu_connector_atom_dig *dig_connector =
61 amdgpu_connector->con_priv;
63 /* if existing sink type was not DP no need to retrain */
64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
67 /* first get sink type as it may be reset after (un)plug */
68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor
72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 /* Don't start link training before we have the DPCD */
76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
79 /* Turn the connector off and back on immediately, which
80 * will trigger link training
82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
90 struct drm_crtc *crtc = encoder->crtc;
92 if (crtc && crtc->enabled) {
93 drm_crtc_helper_set_mode(crtc, &crtc->mode,
94 crtc->x, crtc->y, crtc->primary->fb);
98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
101 struct amdgpu_connector_atom_dig *dig_connector;
103 unsigned mode_clock, max_tmds_clock;
105 switch (connector->connector_type) {
106 case DRM_MODE_CONNECTOR_DVII:
107 case DRM_MODE_CONNECTOR_HDMIB:
108 if (amdgpu_connector->use_digital) {
109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
110 if (connector->display_info.bpc)
111 bpc = connector->display_info.bpc;
115 case DRM_MODE_CONNECTOR_DVID:
116 case DRM_MODE_CONNECTOR_HDMIA:
117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
118 if (connector->display_info.bpc)
119 bpc = connector->display_info.bpc;
122 case DRM_MODE_CONNECTOR_DisplayPort:
123 dig_connector = amdgpu_connector->con_priv;
124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
127 if (connector->display_info.bpc)
128 bpc = connector->display_info.bpc;
131 case DRM_MODE_CONNECTOR_eDP:
132 case DRM_MODE_CONNECTOR_LVDS:
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
136 const struct drm_connector_helper_funcs *connector_funcs =
137 connector->helper_private;
138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
154 * 12 bpc is always supported on hdmi deep color sinks, as this is
155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
159 connector->name, bpc);
163 /* Any defined maximum tmds clock limit we must not exceed? */
164 if (connector->display_info.max_tmds_clock > 0) {
165 /* mode_clock is clock in kHz for mode to be modeset on this connector */
166 mode_clock = amdgpu_connector->pixelclock_for_modeset;
168 /* Maximum allowable input clock in kHz */
169 max_tmds_clock = connector->display_info.max_tmds_clock;
171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
172 connector->name, mode_clock, max_tmds_clock);
174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
177 (mode_clock * 5/4 <= max_tmds_clock))
182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
183 connector->name, bpc);
186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
189 connector->name, bpc);
191 } else if (bpc > 8) {
192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
199 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
206 connector->name, connector->display_info.bpc, bpc);
212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
213 enum drm_connector_status status)
215 struct drm_encoder *best_encoder;
216 struct drm_encoder *encoder;
217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221 best_encoder = connector_funcs->best_encoder(connector);
223 drm_connector_for_each_possible_encoder(connector, encoder, i) {
224 if ((encoder == best_encoder) && (status == connector_status_connected))
229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
233 static struct drm_encoder *
234 amdgpu_connector_find_encoder(struct drm_connector *connector,
237 struct drm_encoder *encoder;
240 drm_connector_for_each_possible_encoder(connector, encoder, i) {
241 if (encoder->encoder_type == encoder_type)
248 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
253 if (amdgpu_connector->edid) {
254 return amdgpu_connector->edid;
255 } else if (edid_blob) {
256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
258 amdgpu_connector->edid = edid;
260 return amdgpu_connector->edid;
264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
268 if (adev->mode_info.bios_hardcoded_edid) {
269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
271 memcpy((unsigned char *)edid,
272 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
273 adev->mode_info.bios_hardcoded_edid_size);
280 static void amdgpu_connector_get_edid(struct drm_connector *connector)
282 struct drm_device *dev = connector->dev;
283 struct amdgpu_device *adev = dev->dev_private;
284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
286 if (amdgpu_connector->edid)
289 /* on hw with routers, select right port */
290 if (amdgpu_connector->router.ddc_valid)
291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
294 ENCODER_OBJECT_ID_NONE) &&
295 amdgpu_connector->ddc_bus->has_aux) {
296 amdgpu_connector->edid = drm_get_edid(connector,
297 &amdgpu_connector->ddc_bus->aux.ddc);
298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
304 amdgpu_connector->ddc_bus->has_aux)
305 amdgpu_connector->edid = drm_get_edid(connector,
306 &amdgpu_connector->ddc_bus->aux.ddc);
307 else if (amdgpu_connector->ddc_bus)
308 amdgpu_connector->edid = drm_get_edid(connector,
309 &amdgpu_connector->ddc_bus->adapter);
310 } else if (amdgpu_connector->ddc_bus) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->adapter);
315 if (!amdgpu_connector->edid) {
316 /* some laptops provide a hardcoded edid in rom for LCDs */
317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
323 static void amdgpu_connector_free_edid(struct drm_connector *connector)
325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
327 kfree(amdgpu_connector->edid);
328 amdgpu_connector->edid = NULL;
331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
336 if (amdgpu_connector->edid) {
337 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
341 drm_connector_update_edid_property(connector, NULL);
345 static struct drm_encoder *
346 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
348 struct drm_encoder *encoder;
351 /* pick the first one */
352 drm_connector_for_each_possible_encoder(connector, encoder, i)
358 static void amdgpu_get_native_mode(struct drm_connector *connector)
360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
361 struct amdgpu_encoder *amdgpu_encoder;
366 amdgpu_encoder = to_amdgpu_encoder(encoder);
368 if (!list_empty(&connector->probed_modes)) {
369 struct drm_display_mode *preferred_mode =
370 list_first_entry(&connector->probed_modes,
371 struct drm_display_mode, head);
373 amdgpu_encoder->native_mode = *preferred_mode;
375 amdgpu_encoder->native_mode.clock = 0;
379 static struct drm_display_mode *
380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
382 struct drm_device *dev = encoder->dev;
383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
384 struct drm_display_mode *mode = NULL;
385 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
387 if (native_mode->hdisplay != 0 &&
388 native_mode->vdisplay != 0 &&
389 native_mode->clock != 0) {
390 mode = drm_mode_duplicate(dev, native_mode);
394 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
395 drm_mode_set_name(mode);
397 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
398 } else if (native_mode->hdisplay != 0 &&
399 native_mode->vdisplay != 0) {
400 /* mac laptops without an edid */
401 /* Note that this is not necessarily the exact panel mode,
402 * but an approximation based on the cvt formula. For these
403 * systems we should ideally read the mode info out of the
404 * registers or add a mode table, but this works and is much
407 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
411 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
412 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
417 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
418 struct drm_connector *connector)
420 struct drm_device *dev = encoder->dev;
421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
422 struct drm_display_mode *mode = NULL;
423 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
425 static const struct mode_size {
428 } common_modes[17] = {
448 for (i = 0; i < 17; i++) {
449 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
450 if (common_modes[i].w > 1024 ||
451 common_modes[i].h > 768)
454 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
455 if (common_modes[i].w > native_mode->hdisplay ||
456 common_modes[i].h > native_mode->vdisplay ||
457 (common_modes[i].w == native_mode->hdisplay &&
458 common_modes[i].h == native_mode->vdisplay))
461 if (common_modes[i].w < 320 || common_modes[i].h < 200)
464 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
465 drm_mode_probed_add(connector, mode);
469 static int amdgpu_connector_set_property(struct drm_connector *connector,
470 struct drm_property *property,
473 struct drm_device *dev = connector->dev;
474 struct amdgpu_device *adev = dev->dev_private;
475 struct drm_encoder *encoder;
476 struct amdgpu_encoder *amdgpu_encoder;
478 if (property == adev->mode_info.coherent_mode_property) {
479 struct amdgpu_encoder_atom_dig *dig;
480 bool new_coherent_mode;
482 /* need to find digital encoder on connector */
483 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
487 amdgpu_encoder = to_amdgpu_encoder(encoder);
489 if (!amdgpu_encoder->enc_priv)
492 dig = amdgpu_encoder->enc_priv;
493 new_coherent_mode = val ? true : false;
494 if (dig->coherent_mode != new_coherent_mode) {
495 dig->coherent_mode = new_coherent_mode;
496 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
500 if (property == adev->mode_info.audio_property) {
501 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
502 /* need to find digital encoder on connector */
503 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
507 amdgpu_encoder = to_amdgpu_encoder(encoder);
509 if (amdgpu_connector->audio != val) {
510 amdgpu_connector->audio = val;
511 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
515 if (property == adev->mode_info.dither_property) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517 /* need to find digital encoder on connector */
518 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
522 amdgpu_encoder = to_amdgpu_encoder(encoder);
524 if (amdgpu_connector->dither != val) {
525 amdgpu_connector->dither = val;
526 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
530 if (property == adev->mode_info.underscan_property) {
531 /* need to find digital encoder on connector */
532 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
536 amdgpu_encoder = to_amdgpu_encoder(encoder);
538 if (amdgpu_encoder->underscan_type != val) {
539 amdgpu_encoder->underscan_type = val;
540 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
544 if (property == adev->mode_info.underscan_hborder_property) {
545 /* need to find digital encoder on connector */
546 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
550 amdgpu_encoder = to_amdgpu_encoder(encoder);
552 if (amdgpu_encoder->underscan_hborder != val) {
553 amdgpu_encoder->underscan_hborder = val;
554 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
558 if (property == adev->mode_info.underscan_vborder_property) {
559 /* need to find digital encoder on connector */
560 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
564 amdgpu_encoder = to_amdgpu_encoder(encoder);
566 if (amdgpu_encoder->underscan_vborder != val) {
567 amdgpu_encoder->underscan_vborder = val;
568 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
572 if (property == adev->mode_info.load_detect_property) {
573 struct amdgpu_connector *amdgpu_connector =
574 to_amdgpu_connector(connector);
577 amdgpu_connector->dac_load_detect = false;
579 amdgpu_connector->dac_load_detect = true;
582 if (property == dev->mode_config.scaling_mode_property) {
583 enum amdgpu_rmx_type rmx_type;
585 if (connector->encoder) {
586 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
588 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
589 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
594 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
595 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
596 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
597 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
599 if (amdgpu_encoder->rmx_type == rmx_type)
602 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
603 (amdgpu_encoder->native_mode.clock == 0))
606 amdgpu_encoder->rmx_type = rmx_type;
608 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
615 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
616 struct drm_connector *connector)
618 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
619 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
620 struct drm_display_mode *t, *mode;
622 /* If the EDID preferred mode doesn't match the native mode, use it */
623 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
624 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
625 if (mode->hdisplay != native_mode->hdisplay ||
626 mode->vdisplay != native_mode->vdisplay)
627 memcpy(native_mode, mode, sizeof(*mode));
631 /* Try to get native mode details from EDID if necessary */
632 if (!native_mode->clock) {
633 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
634 if (mode->hdisplay == native_mode->hdisplay &&
635 mode->vdisplay == native_mode->vdisplay) {
636 *native_mode = *mode;
637 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
638 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
644 if (!native_mode->clock) {
645 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
646 amdgpu_encoder->rmx_type = RMX_OFF;
650 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
652 struct drm_encoder *encoder;
654 struct drm_display_mode *mode;
656 amdgpu_connector_get_edid(connector);
657 ret = amdgpu_connector_ddc_get_modes(connector);
659 encoder = amdgpu_connector_best_single_encoder(connector);
661 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
662 /* add scaled modes */
663 amdgpu_connector_add_common_modes(encoder, connector);
668 encoder = amdgpu_connector_best_single_encoder(connector);
672 /* we have no EDID modes */
673 mode = amdgpu_connector_lcd_native_mode(encoder);
676 drm_mode_probed_add(connector, mode);
677 /* add the width/height from vbios tables if available */
678 connector->display_info.width_mm = mode->width_mm;
679 connector->display_info.height_mm = mode->height_mm;
680 /* add scaled modes */
681 amdgpu_connector_add_common_modes(encoder, connector);
687 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
688 struct drm_display_mode *mode)
690 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
692 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
697 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
699 /* AVIVO hardware supports downscaling modes larger than the panel
700 * to the panel size, but I'm not sure this is desirable.
702 if ((mode->hdisplay > native_mode->hdisplay) ||
703 (mode->vdisplay > native_mode->vdisplay))
706 /* if scaling is disabled, block non-native modes */
707 if (amdgpu_encoder->rmx_type == RMX_OFF) {
708 if ((mode->hdisplay != native_mode->hdisplay) ||
709 (mode->vdisplay != native_mode->vdisplay))
717 static enum drm_connector_status
718 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
720 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
721 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
722 enum drm_connector_status ret = connector_status_disconnected;
725 if (!drm_kms_helper_is_poll_worker()) {
726 r = pm_runtime_get_sync(connector->dev->dev);
728 pm_runtime_put_autosuspend(connector->dev->dev);
729 return connector_status_disconnected;
734 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
735 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
737 /* check if panel is valid */
738 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
739 ret = connector_status_connected;
743 /* check for edid as well */
744 amdgpu_connector_get_edid(connector);
745 if (amdgpu_connector->edid)
746 ret = connector_status_connected;
747 /* check acpi lid status ??? */
749 amdgpu_connector_update_scratch_regs(connector, ret);
751 if (!drm_kms_helper_is_poll_worker()) {
752 pm_runtime_mark_last_busy(connector->dev->dev);
753 pm_runtime_put_autosuspend(connector->dev->dev);
759 static void amdgpu_connector_unregister(struct drm_connector *connector)
761 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
763 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
764 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
765 amdgpu_connector->ddc_bus->has_aux = false;
769 static void amdgpu_connector_destroy(struct drm_connector *connector)
771 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
773 amdgpu_connector_free_edid(connector);
774 kfree(amdgpu_connector->con_priv);
775 drm_connector_unregister(connector);
776 drm_connector_cleanup(connector);
780 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
781 struct drm_property *property,
784 struct drm_device *dev = connector->dev;
785 struct amdgpu_encoder *amdgpu_encoder;
786 enum amdgpu_rmx_type rmx_type;
789 if (property != dev->mode_config.scaling_mode_property)
792 if (connector->encoder)
793 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
795 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
796 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
800 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
801 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
802 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
804 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
806 if (amdgpu_encoder->rmx_type == rmx_type)
809 amdgpu_encoder->rmx_type = rmx_type;
811 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
816 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
817 .get_modes = amdgpu_connector_lvds_get_modes,
818 .mode_valid = amdgpu_connector_lvds_mode_valid,
819 .best_encoder = amdgpu_connector_best_single_encoder,
822 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
823 .dpms = drm_helper_connector_dpms,
824 .detect = amdgpu_connector_lvds_detect,
825 .fill_modes = drm_helper_probe_single_connector_modes,
826 .early_unregister = amdgpu_connector_unregister,
827 .destroy = amdgpu_connector_destroy,
828 .set_property = amdgpu_connector_set_lcd_property,
831 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
835 amdgpu_connector_get_edid(connector);
836 ret = amdgpu_connector_ddc_get_modes(connector);
837 amdgpu_get_native_mode(connector);
842 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
843 struct drm_display_mode *mode)
845 struct drm_device *dev = connector->dev;
846 struct amdgpu_device *adev = dev->dev_private;
848 /* XXX check mode bandwidth */
850 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
851 return MODE_CLOCK_HIGH;
856 static enum drm_connector_status
857 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
859 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
860 struct drm_encoder *encoder;
861 const struct drm_encoder_helper_funcs *encoder_funcs;
863 enum drm_connector_status ret = connector_status_disconnected;
866 if (!drm_kms_helper_is_poll_worker()) {
867 r = pm_runtime_get_sync(connector->dev->dev);
869 pm_runtime_put_autosuspend(connector->dev->dev);
870 return connector_status_disconnected;
874 encoder = amdgpu_connector_best_single_encoder(connector);
876 ret = connector_status_disconnected;
878 if (amdgpu_connector->ddc_bus)
879 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
881 amdgpu_connector->detected_by_load = false;
882 amdgpu_connector_free_edid(connector);
883 amdgpu_connector_get_edid(connector);
885 if (!amdgpu_connector->edid) {
886 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
888 ret = connector_status_connected;
890 amdgpu_connector->use_digital =
891 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
893 /* some oems have boards with separate digital and analog connectors
894 * with a shared ddc line (often vga + hdmi)
896 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
897 amdgpu_connector_free_edid(connector);
898 ret = connector_status_disconnected;
900 ret = connector_status_connected;
905 /* if we aren't forcing don't do destructive polling */
907 /* only return the previous status if we last
908 * detected a monitor via load.
910 if (amdgpu_connector->detected_by_load)
911 ret = connector->status;
915 if (amdgpu_connector->dac_load_detect && encoder) {
916 encoder_funcs = encoder->helper_private;
917 ret = encoder_funcs->detect(encoder, connector);
918 if (ret != connector_status_disconnected)
919 amdgpu_connector->detected_by_load = true;
923 amdgpu_connector_update_scratch_regs(connector, ret);
926 if (!drm_kms_helper_is_poll_worker()) {
927 pm_runtime_mark_last_busy(connector->dev->dev);
928 pm_runtime_put_autosuspend(connector->dev->dev);
934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
935 .get_modes = amdgpu_connector_vga_get_modes,
936 .mode_valid = amdgpu_connector_vga_mode_valid,
937 .best_encoder = amdgpu_connector_best_single_encoder,
940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
941 .dpms = drm_helper_connector_dpms,
942 .detect = amdgpu_connector_vga_detect,
943 .fill_modes = drm_helper_probe_single_connector_modes,
944 .early_unregister = amdgpu_connector_unregister,
945 .destroy = amdgpu_connector_destroy,
946 .set_property = amdgpu_connector_set_property,
950 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
952 struct drm_device *dev = connector->dev;
953 struct amdgpu_device *adev = dev->dev_private;
954 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
955 enum drm_connector_status status;
957 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
958 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
959 status = connector_status_connected;
961 status = connector_status_disconnected;
962 if (connector->status == status)
971 * Do a DDC probe, if DDC probe passes, get the full EDID so
972 * we can do analog/digital monitor detection at this point.
973 * If the monitor is an analog monitor or we got no DDC,
974 * we need to find the DAC encoder object for this connector.
975 * If we got no DDC, we do load detection on the DAC encoder object.
976 * If we got analog DDC or load detection passes on the DAC encoder
977 * we have to check if this analog encoder is shared with anyone else (TV)
978 * if its shared we have to set the other connector to disconnected.
980 static enum drm_connector_status
981 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
983 struct drm_device *dev = connector->dev;
984 struct amdgpu_device *adev = dev->dev_private;
985 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
986 const struct drm_encoder_helper_funcs *encoder_funcs;
988 enum drm_connector_status ret = connector_status_disconnected;
989 bool dret = false, broken_edid = false;
991 if (!drm_kms_helper_is_poll_worker()) {
992 r = pm_runtime_get_sync(connector->dev->dev);
994 pm_runtime_put_autosuspend(connector->dev->dev);
995 return connector_status_disconnected;
999 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1000 ret = connector->status;
1004 if (amdgpu_connector->ddc_bus)
1005 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1007 amdgpu_connector->detected_by_load = false;
1008 amdgpu_connector_free_edid(connector);
1009 amdgpu_connector_get_edid(connector);
1011 if (!amdgpu_connector->edid) {
1012 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1014 ret = connector_status_connected;
1015 broken_edid = true; /* defer use_digital to later */
1017 amdgpu_connector->use_digital =
1018 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1020 /* some oems have boards with separate digital and analog connectors
1021 * with a shared ddc line (often vga + hdmi)
1023 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1024 amdgpu_connector_free_edid(connector);
1025 ret = connector_status_disconnected;
1027 ret = connector_status_connected;
1030 /* This gets complicated. We have boards with VGA + HDMI with a
1031 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1032 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1033 * you don't really know what's connected to which port as both are digital.
1035 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1036 struct drm_connector *list_connector;
1037 struct amdgpu_connector *list_amdgpu_connector;
1038 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1039 if (connector == list_connector)
1041 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1042 if (list_amdgpu_connector->shared_ddc &&
1043 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1044 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1045 /* cases where both connectors are digital */
1046 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1047 /* hpd is our only option in this case */
1048 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1049 amdgpu_connector_free_edid(connector);
1050 ret = connector_status_disconnected;
1059 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1062 /* DVI-D and HDMI-A are digital only */
1063 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1064 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1067 /* if we aren't forcing don't do destructive polling */
1069 /* only return the previous status if we last
1070 * detected a monitor via load.
1072 if (amdgpu_connector->detected_by_load)
1073 ret = connector->status;
1077 /* find analog encoder */
1078 if (amdgpu_connector->dac_load_detect) {
1079 struct drm_encoder *encoder;
1082 drm_connector_for_each_possible_encoder(connector, encoder, i) {
1083 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1084 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1087 encoder_funcs = encoder->helper_private;
1088 if (encoder_funcs->detect) {
1090 if (ret != connector_status_connected) {
1091 /* deal with analog monitors without DDC */
1092 ret = encoder_funcs->detect(encoder, connector);
1093 if (ret == connector_status_connected) {
1094 amdgpu_connector->use_digital = false;
1096 if (ret != connector_status_disconnected)
1097 amdgpu_connector->detected_by_load = true;
1100 enum drm_connector_status lret;
1101 /* assume digital unless load detected otherwise */
1102 amdgpu_connector->use_digital = true;
1103 lret = encoder_funcs->detect(encoder, connector);
1104 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1105 if (lret == connector_status_connected)
1106 amdgpu_connector->use_digital = false;
1114 /* updated in get modes as well since we need to know if it's analog or digital */
1115 amdgpu_connector_update_scratch_regs(connector, ret);
1118 if (!drm_kms_helper_is_poll_worker()) {
1119 pm_runtime_mark_last_busy(connector->dev->dev);
1120 pm_runtime_put_autosuspend(connector->dev->dev);
1126 /* okay need to be smart in here about which encoder to pick */
1127 static struct drm_encoder *
1128 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1130 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1131 struct drm_encoder *encoder;
1134 drm_connector_for_each_possible_encoder(connector, encoder, i) {
1135 if (amdgpu_connector->use_digital == true) {
1136 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1139 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1140 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1145 /* see if we have a default encoder TODO */
1147 /* then check use digitial */
1148 /* pick the first one */
1149 drm_connector_for_each_possible_encoder(connector, encoder, i)
1155 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1157 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1158 if (connector->force == DRM_FORCE_ON)
1159 amdgpu_connector->use_digital = false;
1160 if (connector->force == DRM_FORCE_ON_DIGITAL)
1161 amdgpu_connector->use_digital = true;
1164 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1165 struct drm_display_mode *mode)
1167 struct drm_device *dev = connector->dev;
1168 struct amdgpu_device *adev = dev->dev_private;
1169 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1171 /* XXX check mode bandwidth */
1173 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1174 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1175 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1176 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1178 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1179 /* HDMI 1.3+ supports max clock of 340 Mhz */
1180 if (mode->clock > 340000)
1181 return MODE_CLOCK_HIGH;
1185 return MODE_CLOCK_HIGH;
1189 /* check against the max pixel clock */
1190 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1191 return MODE_CLOCK_HIGH;
1196 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1197 .get_modes = amdgpu_connector_vga_get_modes,
1198 .mode_valid = amdgpu_connector_dvi_mode_valid,
1199 .best_encoder = amdgpu_connector_dvi_encoder,
1202 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1203 .dpms = drm_helper_connector_dpms,
1204 .detect = amdgpu_connector_dvi_detect,
1205 .fill_modes = drm_helper_probe_single_connector_modes,
1206 .set_property = amdgpu_connector_set_property,
1207 .early_unregister = amdgpu_connector_unregister,
1208 .destroy = amdgpu_connector_destroy,
1209 .force = amdgpu_connector_dvi_force,
1212 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1214 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1215 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1216 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1219 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1220 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1221 struct drm_display_mode *mode;
1223 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1224 if (!amdgpu_dig_connector->edp_on)
1225 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1226 ATOM_TRANSMITTER_ACTION_POWER_ON);
1227 amdgpu_connector_get_edid(connector);
1228 ret = amdgpu_connector_ddc_get_modes(connector);
1229 if (!amdgpu_dig_connector->edp_on)
1230 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1231 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1233 /* need to setup ddc on the bridge */
1234 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1235 ENCODER_OBJECT_ID_NONE) {
1237 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1239 amdgpu_connector_get_edid(connector);
1240 ret = amdgpu_connector_ddc_get_modes(connector);
1245 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1246 /* add scaled modes */
1247 amdgpu_connector_add_common_modes(encoder, connector);
1255 /* we have no EDID modes */
1256 mode = amdgpu_connector_lcd_native_mode(encoder);
1259 drm_mode_probed_add(connector, mode);
1260 /* add the width/height from vbios tables if available */
1261 connector->display_info.width_mm = mode->width_mm;
1262 connector->display_info.height_mm = mode->height_mm;
1263 /* add scaled modes */
1264 amdgpu_connector_add_common_modes(encoder, connector);
1267 /* need to setup ddc on the bridge */
1268 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1269 ENCODER_OBJECT_ID_NONE) {
1271 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1273 amdgpu_connector_get_edid(connector);
1274 ret = amdgpu_connector_ddc_get_modes(connector);
1276 amdgpu_get_native_mode(connector);
1282 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1284 struct drm_encoder *encoder;
1285 struct amdgpu_encoder *amdgpu_encoder;
1288 drm_connector_for_each_possible_encoder(connector, encoder, i) {
1289 amdgpu_encoder = to_amdgpu_encoder(encoder);
1291 switch (amdgpu_encoder->encoder_id) {
1292 case ENCODER_OBJECT_ID_TRAVIS:
1293 case ENCODER_OBJECT_ID_NUTMEG:
1294 return amdgpu_encoder->encoder_id;
1300 return ENCODER_OBJECT_ID_NONE;
1303 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1305 struct drm_encoder *encoder;
1306 struct amdgpu_encoder *amdgpu_encoder;
1310 drm_connector_for_each_possible_encoder(connector, encoder, i) {
1311 amdgpu_encoder = to_amdgpu_encoder(encoder);
1312 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1319 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1321 struct drm_device *dev = connector->dev;
1322 struct amdgpu_device *adev = dev->dev_private;
1324 if ((adev->clock.default_dispclk >= 53900) &&
1325 amdgpu_connector_encoder_is_hbr2(connector)) {
1332 static enum drm_connector_status
1333 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1335 struct drm_device *dev = connector->dev;
1336 struct amdgpu_device *adev = dev->dev_private;
1337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1338 enum drm_connector_status ret = connector_status_disconnected;
1339 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1340 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1343 if (!drm_kms_helper_is_poll_worker()) {
1344 r = pm_runtime_get_sync(connector->dev->dev);
1346 pm_runtime_put_autosuspend(connector->dev->dev);
1347 return connector_status_disconnected;
1351 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1352 ret = connector->status;
1356 amdgpu_connector_free_edid(connector);
1358 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1359 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1361 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1362 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1364 /* check if panel is valid */
1365 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1366 ret = connector_status_connected;
1368 /* eDP is always DP */
1369 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1370 if (!amdgpu_dig_connector->edp_on)
1371 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1372 ATOM_TRANSMITTER_ACTION_POWER_ON);
1373 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1374 ret = connector_status_connected;
1375 if (!amdgpu_dig_connector->edp_on)
1376 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1377 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1378 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1379 ENCODER_OBJECT_ID_NONE) {
1380 /* DP bridges are always DP */
1381 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1382 /* get the DPCD from the bridge */
1383 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1386 /* setup ddc on the bridge */
1387 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1388 /* bridge chips are always aux */
1390 if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1391 ret = connector_status_connected;
1392 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1393 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1394 ret = encoder_funcs->detect(encoder, connector);
1398 amdgpu_dig_connector->dp_sink_type =
1399 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1400 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1401 ret = connector_status_connected;
1402 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1403 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1405 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1406 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1407 ret = connector_status_connected;
1409 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1410 if (amdgpu_display_ddc_probe(amdgpu_connector,
1412 ret = connector_status_connected;
1417 amdgpu_connector_update_scratch_regs(connector, ret);
1419 if (!drm_kms_helper_is_poll_worker()) {
1420 pm_runtime_mark_last_busy(connector->dev->dev);
1421 pm_runtime_put_autosuspend(connector->dev->dev);
1427 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1428 struct drm_display_mode *mode)
1430 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1431 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1433 /* XXX check mode bandwidth */
1435 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1436 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1437 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1439 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1444 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1446 /* AVIVO hardware supports downscaling modes larger than the panel
1447 * to the panel size, but I'm not sure this is desirable.
1449 if ((mode->hdisplay > native_mode->hdisplay) ||
1450 (mode->vdisplay > native_mode->vdisplay))
1453 /* if scaling is disabled, block non-native modes */
1454 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1455 if ((mode->hdisplay != native_mode->hdisplay) ||
1456 (mode->vdisplay != native_mode->vdisplay))
1462 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1463 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1464 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1466 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1467 /* HDMI 1.3+ supports max clock of 340 Mhz */
1468 if (mode->clock > 340000)
1469 return MODE_CLOCK_HIGH;
1471 if (mode->clock > 165000)
1472 return MODE_CLOCK_HIGH;
1480 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1481 .get_modes = amdgpu_connector_dp_get_modes,
1482 .mode_valid = amdgpu_connector_dp_mode_valid,
1483 .best_encoder = amdgpu_connector_dvi_encoder,
1486 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1487 .dpms = drm_helper_connector_dpms,
1488 .detect = amdgpu_connector_dp_detect,
1489 .fill_modes = drm_helper_probe_single_connector_modes,
1490 .set_property = amdgpu_connector_set_property,
1491 .early_unregister = amdgpu_connector_unregister,
1492 .destroy = amdgpu_connector_destroy,
1493 .force = amdgpu_connector_dvi_force,
1496 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1497 .dpms = drm_helper_connector_dpms,
1498 .detect = amdgpu_connector_dp_detect,
1499 .fill_modes = drm_helper_probe_single_connector_modes,
1500 .set_property = amdgpu_connector_set_lcd_property,
1501 .early_unregister = amdgpu_connector_unregister,
1502 .destroy = amdgpu_connector_destroy,
1503 .force = amdgpu_connector_dvi_force,
1507 amdgpu_connector_add(struct amdgpu_device *adev,
1508 uint32_t connector_id,
1509 uint32_t supported_device,
1511 struct amdgpu_i2c_bus_rec *i2c_bus,
1512 uint16_t connector_object_id,
1513 struct amdgpu_hpd *hpd,
1514 struct amdgpu_router *router)
1516 struct drm_device *dev = adev->ddev;
1517 struct drm_connector *connector;
1518 struct amdgpu_connector *amdgpu_connector;
1519 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1520 struct drm_encoder *encoder;
1521 struct amdgpu_encoder *amdgpu_encoder;
1522 uint32_t subpixel_order = SubPixelNone;
1523 bool shared_ddc = false;
1524 bool is_dp_bridge = false;
1525 bool has_aux = false;
1527 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1530 /* see if we already added it */
1531 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1532 amdgpu_connector = to_amdgpu_connector(connector);
1533 if (amdgpu_connector->connector_id == connector_id) {
1534 amdgpu_connector->devices |= supported_device;
1537 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1538 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1539 amdgpu_connector->shared_ddc = true;
1542 if (amdgpu_connector->router_bus && router->ddc_valid &&
1543 (amdgpu_connector->router.router_id == router->router_id)) {
1544 amdgpu_connector->shared_ddc = false;
1550 /* check if it's a dp bridge */
1551 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1552 amdgpu_encoder = to_amdgpu_encoder(encoder);
1553 if (amdgpu_encoder->devices & supported_device) {
1554 switch (amdgpu_encoder->encoder_id) {
1555 case ENCODER_OBJECT_ID_TRAVIS:
1556 case ENCODER_OBJECT_ID_NUTMEG:
1557 is_dp_bridge = true;
1565 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1566 if (!amdgpu_connector)
1569 connector = &amdgpu_connector->base;
1571 amdgpu_connector->connector_id = connector_id;
1572 amdgpu_connector->devices = supported_device;
1573 amdgpu_connector->shared_ddc = shared_ddc;
1574 amdgpu_connector->connector_object_id = connector_object_id;
1575 amdgpu_connector->hpd = *hpd;
1577 amdgpu_connector->router = *router;
1578 if (router->ddc_valid || router->cd_valid) {
1579 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1580 if (!amdgpu_connector->router_bus)
1581 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1585 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1586 if (!amdgpu_dig_connector)
1588 amdgpu_connector->con_priv = amdgpu_dig_connector;
1589 if (i2c_bus->valid) {
1590 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1591 if (amdgpu_connector->ddc_bus)
1594 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1596 switch (connector_type) {
1597 case DRM_MODE_CONNECTOR_VGA:
1598 case DRM_MODE_CONNECTOR_DVIA:
1600 drm_connector_init(dev, &amdgpu_connector->base,
1601 &amdgpu_connector_dp_funcs, connector_type);
1602 drm_connector_helper_add(&amdgpu_connector->base,
1603 &amdgpu_connector_dp_helper_funcs);
1604 connector->interlace_allowed = true;
1605 connector->doublescan_allowed = true;
1606 amdgpu_connector->dac_load_detect = true;
1607 drm_object_attach_property(&amdgpu_connector->base.base,
1608 adev->mode_info.load_detect_property,
1610 drm_object_attach_property(&amdgpu_connector->base.base,
1611 dev->mode_config.scaling_mode_property,
1612 DRM_MODE_SCALE_NONE);
1614 case DRM_MODE_CONNECTOR_DVII:
1615 case DRM_MODE_CONNECTOR_DVID:
1616 case DRM_MODE_CONNECTOR_HDMIA:
1617 case DRM_MODE_CONNECTOR_HDMIB:
1618 case DRM_MODE_CONNECTOR_DisplayPort:
1619 drm_connector_init(dev, &amdgpu_connector->base,
1620 &amdgpu_connector_dp_funcs, connector_type);
1621 drm_connector_helper_add(&amdgpu_connector->base,
1622 &amdgpu_connector_dp_helper_funcs);
1623 drm_object_attach_property(&amdgpu_connector->base.base,
1624 adev->mode_info.underscan_property,
1626 drm_object_attach_property(&amdgpu_connector->base.base,
1627 adev->mode_info.underscan_hborder_property,
1629 drm_object_attach_property(&amdgpu_connector->base.base,
1630 adev->mode_info.underscan_vborder_property,
1633 drm_object_attach_property(&amdgpu_connector->base.base,
1634 dev->mode_config.scaling_mode_property,
1635 DRM_MODE_SCALE_NONE);
1637 drm_object_attach_property(&amdgpu_connector->base.base,
1638 adev->mode_info.dither_property,
1639 AMDGPU_FMT_DITHER_DISABLE);
1641 if (amdgpu_audio != 0) {
1642 drm_object_attach_property(&amdgpu_connector->base.base,
1643 adev->mode_info.audio_property,
1645 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1648 subpixel_order = SubPixelHorizontalRGB;
1649 connector->interlace_allowed = true;
1650 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1651 connector->doublescan_allowed = true;
1653 connector->doublescan_allowed = false;
1654 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1655 amdgpu_connector->dac_load_detect = true;
1656 drm_object_attach_property(&amdgpu_connector->base.base,
1657 adev->mode_info.load_detect_property,
1661 case DRM_MODE_CONNECTOR_LVDS:
1662 case DRM_MODE_CONNECTOR_eDP:
1663 drm_connector_init(dev, &amdgpu_connector->base,
1664 &amdgpu_connector_edp_funcs, connector_type);
1665 drm_connector_helper_add(&amdgpu_connector->base,
1666 &amdgpu_connector_dp_helper_funcs);
1667 drm_object_attach_property(&amdgpu_connector->base.base,
1668 dev->mode_config.scaling_mode_property,
1669 DRM_MODE_SCALE_FULLSCREEN);
1670 subpixel_order = SubPixelHorizontalRGB;
1671 connector->interlace_allowed = false;
1672 connector->doublescan_allowed = false;
1676 switch (connector_type) {
1677 case DRM_MODE_CONNECTOR_VGA:
1678 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1679 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1680 if (i2c_bus->valid) {
1681 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1682 if (!amdgpu_connector->ddc_bus)
1683 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1685 amdgpu_connector->dac_load_detect = true;
1686 drm_object_attach_property(&amdgpu_connector->base.base,
1687 adev->mode_info.load_detect_property,
1689 drm_object_attach_property(&amdgpu_connector->base.base,
1690 dev->mode_config.scaling_mode_property,
1691 DRM_MODE_SCALE_NONE);
1692 /* no HPD on analog connectors */
1693 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1694 connector->interlace_allowed = true;
1695 connector->doublescan_allowed = true;
1697 case DRM_MODE_CONNECTOR_DVIA:
1698 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1699 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1700 if (i2c_bus->valid) {
1701 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1702 if (!amdgpu_connector->ddc_bus)
1703 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1705 amdgpu_connector->dac_load_detect = true;
1706 drm_object_attach_property(&amdgpu_connector->base.base,
1707 adev->mode_info.load_detect_property,
1709 drm_object_attach_property(&amdgpu_connector->base.base,
1710 dev->mode_config.scaling_mode_property,
1711 DRM_MODE_SCALE_NONE);
1712 /* no HPD on analog connectors */
1713 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1714 connector->interlace_allowed = true;
1715 connector->doublescan_allowed = true;
1717 case DRM_MODE_CONNECTOR_DVII:
1718 case DRM_MODE_CONNECTOR_DVID:
1719 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1720 if (!amdgpu_dig_connector)
1722 amdgpu_connector->con_priv = amdgpu_dig_connector;
1723 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1724 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1725 if (i2c_bus->valid) {
1726 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1727 if (!amdgpu_connector->ddc_bus)
1728 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1730 subpixel_order = SubPixelHorizontalRGB;
1731 drm_object_attach_property(&amdgpu_connector->base.base,
1732 adev->mode_info.coherent_mode_property,
1734 drm_object_attach_property(&amdgpu_connector->base.base,
1735 adev->mode_info.underscan_property,
1737 drm_object_attach_property(&amdgpu_connector->base.base,
1738 adev->mode_info.underscan_hborder_property,
1740 drm_object_attach_property(&amdgpu_connector->base.base,
1741 adev->mode_info.underscan_vborder_property,
1743 drm_object_attach_property(&amdgpu_connector->base.base,
1744 dev->mode_config.scaling_mode_property,
1745 DRM_MODE_SCALE_NONE);
1747 if (amdgpu_audio != 0) {
1748 drm_object_attach_property(&amdgpu_connector->base.base,
1749 adev->mode_info.audio_property,
1751 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1753 drm_object_attach_property(&amdgpu_connector->base.base,
1754 adev->mode_info.dither_property,
1755 AMDGPU_FMT_DITHER_DISABLE);
1756 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1757 amdgpu_connector->dac_load_detect = true;
1758 drm_object_attach_property(&amdgpu_connector->base.base,
1759 adev->mode_info.load_detect_property,
1762 connector->interlace_allowed = true;
1763 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1764 connector->doublescan_allowed = true;
1766 connector->doublescan_allowed = false;
1768 case DRM_MODE_CONNECTOR_HDMIA:
1769 case DRM_MODE_CONNECTOR_HDMIB:
1770 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1771 if (!amdgpu_dig_connector)
1773 amdgpu_connector->con_priv = amdgpu_dig_connector;
1774 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1775 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1776 if (i2c_bus->valid) {
1777 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1778 if (!amdgpu_connector->ddc_bus)
1779 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1781 drm_object_attach_property(&amdgpu_connector->base.base,
1782 adev->mode_info.coherent_mode_property,
1784 drm_object_attach_property(&amdgpu_connector->base.base,
1785 adev->mode_info.underscan_property,
1787 drm_object_attach_property(&amdgpu_connector->base.base,
1788 adev->mode_info.underscan_hborder_property,
1790 drm_object_attach_property(&amdgpu_connector->base.base,
1791 adev->mode_info.underscan_vborder_property,
1793 drm_object_attach_property(&amdgpu_connector->base.base,
1794 dev->mode_config.scaling_mode_property,
1795 DRM_MODE_SCALE_NONE);
1796 if (amdgpu_audio != 0) {
1797 drm_object_attach_property(&amdgpu_connector->base.base,
1798 adev->mode_info.audio_property,
1800 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1802 drm_object_attach_property(&amdgpu_connector->base.base,
1803 adev->mode_info.dither_property,
1804 AMDGPU_FMT_DITHER_DISABLE);
1805 subpixel_order = SubPixelHorizontalRGB;
1806 connector->interlace_allowed = true;
1807 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1808 connector->doublescan_allowed = true;
1810 connector->doublescan_allowed = false;
1812 case DRM_MODE_CONNECTOR_DisplayPort:
1813 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1814 if (!amdgpu_dig_connector)
1816 amdgpu_connector->con_priv = amdgpu_dig_connector;
1817 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1818 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1819 if (i2c_bus->valid) {
1820 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1821 if (amdgpu_connector->ddc_bus)
1824 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1826 subpixel_order = SubPixelHorizontalRGB;
1827 drm_object_attach_property(&amdgpu_connector->base.base,
1828 adev->mode_info.coherent_mode_property,
1830 drm_object_attach_property(&amdgpu_connector->base.base,
1831 adev->mode_info.underscan_property,
1833 drm_object_attach_property(&amdgpu_connector->base.base,
1834 adev->mode_info.underscan_hborder_property,
1836 drm_object_attach_property(&amdgpu_connector->base.base,
1837 adev->mode_info.underscan_vborder_property,
1839 drm_object_attach_property(&amdgpu_connector->base.base,
1840 dev->mode_config.scaling_mode_property,
1841 DRM_MODE_SCALE_NONE);
1842 if (amdgpu_audio != 0) {
1843 drm_object_attach_property(&amdgpu_connector->base.base,
1844 adev->mode_info.audio_property,
1846 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1848 drm_object_attach_property(&amdgpu_connector->base.base,
1849 adev->mode_info.dither_property,
1850 AMDGPU_FMT_DITHER_DISABLE);
1851 connector->interlace_allowed = true;
1852 /* in theory with a DP to VGA converter... */
1853 connector->doublescan_allowed = false;
1855 case DRM_MODE_CONNECTOR_eDP:
1856 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1857 if (!amdgpu_dig_connector)
1859 amdgpu_connector->con_priv = amdgpu_dig_connector;
1860 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1861 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1862 if (i2c_bus->valid) {
1863 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1864 if (amdgpu_connector->ddc_bus)
1867 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1869 drm_object_attach_property(&amdgpu_connector->base.base,
1870 dev->mode_config.scaling_mode_property,
1871 DRM_MODE_SCALE_FULLSCREEN);
1872 subpixel_order = SubPixelHorizontalRGB;
1873 connector->interlace_allowed = false;
1874 connector->doublescan_allowed = false;
1876 case DRM_MODE_CONNECTOR_LVDS:
1877 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1878 if (!amdgpu_dig_connector)
1880 amdgpu_connector->con_priv = amdgpu_dig_connector;
1881 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1882 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1883 if (i2c_bus->valid) {
1884 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1885 if (!amdgpu_connector->ddc_bus)
1886 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1888 drm_object_attach_property(&amdgpu_connector->base.base,
1889 dev->mode_config.scaling_mode_property,
1890 DRM_MODE_SCALE_FULLSCREEN);
1891 subpixel_order = SubPixelHorizontalRGB;
1892 connector->interlace_allowed = false;
1893 connector->doublescan_allowed = false;
1898 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1899 if (i2c_bus->valid) {
1900 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1901 DRM_CONNECTOR_POLL_DISCONNECT;
1904 connector->polled = DRM_CONNECTOR_POLL_HPD;
1906 connector->display_info.subpixel_order = subpixel_order;
1907 drm_connector_register(connector);
1910 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1915 drm_connector_cleanup(connector);