2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_edid.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/amdgpu_drm.h>
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
38 #include <linux/pm_runtime.h>
40 void amdgpu_connector_hotplug(struct drm_connector *connector)
42 struct drm_device *dev = connector->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
46 /* bail if the connector does not have hpd pin, e.g.,
49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
54 /* if the connector is already off, don't turn it back on */
55 if (connector->dpms != DRM_MODE_DPMS_ON)
58 /* just deal with DP (not eDP) here. */
59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60 struct amdgpu_connector_atom_dig *dig_connector =
61 amdgpu_connector->con_priv;
63 /* if existing sink type was not DP no need to retrain */
64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
67 /* first get sink type as it may be reset after (un)plug */
68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor
72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 /* Don't start link training before we have the DPCD */
76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
79 /* Turn the connector off and back on immediately, which
80 * will trigger link training
82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
90 struct drm_crtc *crtc = encoder->crtc;
92 if (crtc && crtc->enabled) {
93 drm_crtc_helper_set_mode(crtc, &crtc->mode,
94 crtc->x, crtc->y, crtc->primary->fb);
98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
101 struct amdgpu_connector_atom_dig *dig_connector;
103 unsigned mode_clock, max_tmds_clock;
105 switch (connector->connector_type) {
106 case DRM_MODE_CONNECTOR_DVII:
107 case DRM_MODE_CONNECTOR_HDMIB:
108 if (amdgpu_connector->use_digital) {
109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
110 if (connector->display_info.bpc)
111 bpc = connector->display_info.bpc;
115 case DRM_MODE_CONNECTOR_DVID:
116 case DRM_MODE_CONNECTOR_HDMIA:
117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
118 if (connector->display_info.bpc)
119 bpc = connector->display_info.bpc;
122 case DRM_MODE_CONNECTOR_DisplayPort:
123 dig_connector = amdgpu_connector->con_priv;
124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
127 if (connector->display_info.bpc)
128 bpc = connector->display_info.bpc;
131 case DRM_MODE_CONNECTOR_eDP:
132 case DRM_MODE_CONNECTOR_LVDS:
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
136 const struct drm_connector_helper_funcs *connector_funcs =
137 connector->helper_private;
138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
154 * 12 bpc is always supported on hdmi deep color sinks, as this is
155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
159 connector->name, bpc);
163 /* Any defined maximum tmds clock limit we must not exceed? */
164 if (connector->display_info.max_tmds_clock > 0) {
165 /* mode_clock is clock in kHz for mode to be modeset on this connector */
166 mode_clock = amdgpu_connector->pixelclock_for_modeset;
168 /* Maximum allowable input clock in kHz */
169 max_tmds_clock = connector->display_info.max_tmds_clock;
171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
172 connector->name, mode_clock, max_tmds_clock);
174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
177 (mode_clock * 5/4 <= max_tmds_clock))
182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
183 connector->name, bpc);
186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
189 connector->name, bpc);
191 } else if (bpc > 8) {
192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
199 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
206 connector->name, connector->display_info.bpc, bpc);
212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
213 enum drm_connector_status status)
215 struct drm_encoder *best_encoder = NULL;
216 struct drm_encoder *encoder = NULL;
217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221 best_encoder = connector_funcs->best_encoder(connector);
223 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
224 if (connector->encoder_ids[i] == 0)
227 encoder = drm_encoder_find(connector->dev,
228 connector->encoder_ids[i]);
232 if ((encoder == best_encoder) && (status == connector_status_connected))
237 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
242 static struct drm_encoder *
243 amdgpu_connector_find_encoder(struct drm_connector *connector,
246 struct drm_encoder *encoder;
249 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
250 if (connector->encoder_ids[i] == 0)
252 encoder = drm_encoder_find(connector->dev,
253 connector->encoder_ids[i]);
257 if (encoder->encoder_type == encoder_type)
263 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
265 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
266 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
268 if (amdgpu_connector->edid) {
269 return amdgpu_connector->edid;
270 } else if (edid_blob) {
271 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
273 amdgpu_connector->edid = edid;
275 return amdgpu_connector->edid;
279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
283 if (adev->mode_info.bios_hardcoded_edid) {
284 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
286 memcpy((unsigned char *)edid,
287 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
288 adev->mode_info.bios_hardcoded_edid_size);
295 static void amdgpu_connector_get_edid(struct drm_connector *connector)
297 struct drm_device *dev = connector->dev;
298 struct amdgpu_device *adev = dev->dev_private;
299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
301 if (amdgpu_connector->edid)
304 /* on hw with routers, select right port */
305 if (amdgpu_connector->router.ddc_valid)
306 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
308 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309 ENCODER_OBJECT_ID_NONE) &&
310 amdgpu_connector->ddc_bus->has_aux) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->aux.ddc);
313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319 amdgpu_connector->ddc_bus->has_aux)
320 amdgpu_connector->edid = drm_get_edid(connector,
321 &amdgpu_connector->ddc_bus->aux.ddc);
322 else if (amdgpu_connector->ddc_bus)
323 amdgpu_connector->edid = drm_get_edid(connector,
324 &amdgpu_connector->ddc_bus->adapter);
325 } else if (amdgpu_connector->ddc_bus) {
326 amdgpu_connector->edid = drm_get_edid(connector,
327 &amdgpu_connector->ddc_bus->adapter);
330 if (!amdgpu_connector->edid) {
331 /* some laptops provide a hardcoded edid in rom for LCDs */
332 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
333 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
334 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
338 static void amdgpu_connector_free_edid(struct drm_connector *connector)
340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
342 if (amdgpu_connector->edid) {
343 kfree(amdgpu_connector->edid);
344 amdgpu_connector->edid = NULL;
348 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
350 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
353 if (amdgpu_connector->edid) {
354 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
355 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
356 drm_edid_to_eld(connector, amdgpu_connector->edid);
359 drm_mode_connector_update_edid_property(connector, NULL);
363 static struct drm_encoder *
364 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
366 int enc_id = connector->encoder_ids[0];
368 /* pick the encoder ids */
370 return drm_encoder_find(connector->dev, enc_id);
374 static void amdgpu_get_native_mode(struct drm_connector *connector)
376 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
377 struct amdgpu_encoder *amdgpu_encoder;
382 amdgpu_encoder = to_amdgpu_encoder(encoder);
384 if (!list_empty(&connector->probed_modes)) {
385 struct drm_display_mode *preferred_mode =
386 list_first_entry(&connector->probed_modes,
387 struct drm_display_mode, head);
389 amdgpu_encoder->native_mode = *preferred_mode;
391 amdgpu_encoder->native_mode.clock = 0;
395 static struct drm_display_mode *
396 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
398 struct drm_device *dev = encoder->dev;
399 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
400 struct drm_display_mode *mode = NULL;
401 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
403 if (native_mode->hdisplay != 0 &&
404 native_mode->vdisplay != 0 &&
405 native_mode->clock != 0) {
406 mode = drm_mode_duplicate(dev, native_mode);
410 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
411 drm_mode_set_name(mode);
413 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
414 } else if (native_mode->hdisplay != 0 &&
415 native_mode->vdisplay != 0) {
416 /* mac laptops without an edid */
417 /* Note that this is not necessarily the exact panel mode,
418 * but an approximation based on the cvt formula. For these
419 * systems we should ideally read the mode info out of the
420 * registers or add a mode table, but this works and is much
423 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
427 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
428 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
433 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
434 struct drm_connector *connector)
436 struct drm_device *dev = encoder->dev;
437 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
438 struct drm_display_mode *mode = NULL;
439 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
441 static const struct mode_size {
444 } common_modes[17] = {
464 for (i = 0; i < 17; i++) {
465 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
466 if (common_modes[i].w > 1024 ||
467 common_modes[i].h > 768)
470 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
471 if (common_modes[i].w > native_mode->hdisplay ||
472 common_modes[i].h > native_mode->vdisplay ||
473 (common_modes[i].w == native_mode->hdisplay &&
474 common_modes[i].h == native_mode->vdisplay))
477 if (common_modes[i].w < 320 || common_modes[i].h < 200)
480 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
481 drm_mode_probed_add(connector, mode);
485 static int amdgpu_connector_set_property(struct drm_connector *connector,
486 struct drm_property *property,
489 struct drm_device *dev = connector->dev;
490 struct amdgpu_device *adev = dev->dev_private;
491 struct drm_encoder *encoder;
492 struct amdgpu_encoder *amdgpu_encoder;
494 if (property == adev->mode_info.coherent_mode_property) {
495 struct amdgpu_encoder_atom_dig *dig;
496 bool new_coherent_mode;
498 /* need to find digital encoder on connector */
499 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
503 amdgpu_encoder = to_amdgpu_encoder(encoder);
505 if (!amdgpu_encoder->enc_priv)
508 dig = amdgpu_encoder->enc_priv;
509 new_coherent_mode = val ? true : false;
510 if (dig->coherent_mode != new_coherent_mode) {
511 dig->coherent_mode = new_coherent_mode;
512 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
516 if (property == adev->mode_info.audio_property) {
517 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
518 /* need to find digital encoder on connector */
519 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
523 amdgpu_encoder = to_amdgpu_encoder(encoder);
525 if (amdgpu_connector->audio != val) {
526 amdgpu_connector->audio = val;
527 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
531 if (property == adev->mode_info.dither_property) {
532 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
533 /* need to find digital encoder on connector */
534 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
538 amdgpu_encoder = to_amdgpu_encoder(encoder);
540 if (amdgpu_connector->dither != val) {
541 amdgpu_connector->dither = val;
542 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
546 if (property == adev->mode_info.underscan_property) {
547 /* need to find digital encoder on connector */
548 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
552 amdgpu_encoder = to_amdgpu_encoder(encoder);
554 if (amdgpu_encoder->underscan_type != val) {
555 amdgpu_encoder->underscan_type = val;
556 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
560 if (property == adev->mode_info.underscan_hborder_property) {
561 /* need to find digital encoder on connector */
562 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
566 amdgpu_encoder = to_amdgpu_encoder(encoder);
568 if (amdgpu_encoder->underscan_hborder != val) {
569 amdgpu_encoder->underscan_hborder = val;
570 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
574 if (property == adev->mode_info.underscan_vborder_property) {
575 /* need to find digital encoder on connector */
576 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
580 amdgpu_encoder = to_amdgpu_encoder(encoder);
582 if (amdgpu_encoder->underscan_vborder != val) {
583 amdgpu_encoder->underscan_vborder = val;
584 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
588 if (property == adev->mode_info.load_detect_property) {
589 struct amdgpu_connector *amdgpu_connector =
590 to_amdgpu_connector(connector);
593 amdgpu_connector->dac_load_detect = false;
595 amdgpu_connector->dac_load_detect = true;
598 if (property == dev->mode_config.scaling_mode_property) {
599 enum amdgpu_rmx_type rmx_type;
601 if (connector->encoder) {
602 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
604 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
605 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
610 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
611 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
612 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
613 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
615 if (amdgpu_encoder->rmx_type == rmx_type)
618 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
619 (amdgpu_encoder->native_mode.clock == 0))
622 amdgpu_encoder->rmx_type = rmx_type;
624 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
631 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
632 struct drm_connector *connector)
634 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
635 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
636 struct drm_display_mode *t, *mode;
638 /* If the EDID preferred mode doesn't match the native mode, use it */
639 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
640 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
641 if (mode->hdisplay != native_mode->hdisplay ||
642 mode->vdisplay != native_mode->vdisplay)
643 memcpy(native_mode, mode, sizeof(*mode));
647 /* Try to get native mode details from EDID if necessary */
648 if (!native_mode->clock) {
649 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
650 if (mode->hdisplay == native_mode->hdisplay &&
651 mode->vdisplay == native_mode->vdisplay) {
652 *native_mode = *mode;
653 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
654 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
660 if (!native_mode->clock) {
661 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
662 amdgpu_encoder->rmx_type = RMX_OFF;
666 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
668 struct drm_encoder *encoder;
670 struct drm_display_mode *mode;
672 amdgpu_connector_get_edid(connector);
673 ret = amdgpu_connector_ddc_get_modes(connector);
675 encoder = amdgpu_connector_best_single_encoder(connector);
677 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
678 /* add scaled modes */
679 amdgpu_connector_add_common_modes(encoder, connector);
684 encoder = amdgpu_connector_best_single_encoder(connector);
688 /* we have no EDID modes */
689 mode = amdgpu_connector_lcd_native_mode(encoder);
692 drm_mode_probed_add(connector, mode);
693 /* add the width/height from vbios tables if available */
694 connector->display_info.width_mm = mode->width_mm;
695 connector->display_info.height_mm = mode->height_mm;
696 /* add scaled modes */
697 amdgpu_connector_add_common_modes(encoder, connector);
703 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
704 struct drm_display_mode *mode)
706 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
708 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
713 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
715 /* AVIVO hardware supports downscaling modes larger than the panel
716 * to the panel size, but I'm not sure this is desirable.
718 if ((mode->hdisplay > native_mode->hdisplay) ||
719 (mode->vdisplay > native_mode->vdisplay))
722 /* if scaling is disabled, block non-native modes */
723 if (amdgpu_encoder->rmx_type == RMX_OFF) {
724 if ((mode->hdisplay != native_mode->hdisplay) ||
725 (mode->vdisplay != native_mode->vdisplay))
733 static enum drm_connector_status
734 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
736 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
737 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
738 enum drm_connector_status ret = connector_status_disconnected;
741 if (!drm_kms_helper_is_poll_worker()) {
742 r = pm_runtime_get_sync(connector->dev->dev);
744 pm_runtime_put_autosuspend(connector->dev->dev);
745 return connector_status_disconnected;
750 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
751 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
753 /* check if panel is valid */
754 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
755 ret = connector_status_connected;
759 /* check for edid as well */
760 amdgpu_connector_get_edid(connector);
761 if (amdgpu_connector->edid)
762 ret = connector_status_connected;
763 /* check acpi lid status ??? */
765 amdgpu_connector_update_scratch_regs(connector, ret);
767 if (!drm_kms_helper_is_poll_worker()) {
768 pm_runtime_mark_last_busy(connector->dev->dev);
769 pm_runtime_put_autosuspend(connector->dev->dev);
775 static void amdgpu_connector_unregister(struct drm_connector *connector)
777 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
779 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
780 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
781 amdgpu_connector->ddc_bus->has_aux = false;
785 static void amdgpu_connector_destroy(struct drm_connector *connector)
787 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
789 amdgpu_connector_free_edid(connector);
790 kfree(amdgpu_connector->con_priv);
791 drm_connector_unregister(connector);
792 drm_connector_cleanup(connector);
796 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
797 struct drm_property *property,
800 struct drm_device *dev = connector->dev;
801 struct amdgpu_encoder *amdgpu_encoder;
802 enum amdgpu_rmx_type rmx_type;
805 if (property != dev->mode_config.scaling_mode_property)
808 if (connector->encoder)
809 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
811 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
812 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
816 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
817 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
818 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
820 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
822 if (amdgpu_encoder->rmx_type == rmx_type)
825 amdgpu_encoder->rmx_type = rmx_type;
827 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
832 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
833 .get_modes = amdgpu_connector_lvds_get_modes,
834 .mode_valid = amdgpu_connector_lvds_mode_valid,
835 .best_encoder = amdgpu_connector_best_single_encoder,
838 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
839 .dpms = drm_helper_connector_dpms,
840 .detect = amdgpu_connector_lvds_detect,
841 .fill_modes = drm_helper_probe_single_connector_modes,
842 .early_unregister = amdgpu_connector_unregister,
843 .destroy = amdgpu_connector_destroy,
844 .set_property = amdgpu_connector_set_lcd_property,
847 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
851 amdgpu_connector_get_edid(connector);
852 ret = amdgpu_connector_ddc_get_modes(connector);
853 amdgpu_get_native_mode(connector);
858 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
859 struct drm_display_mode *mode)
861 struct drm_device *dev = connector->dev;
862 struct amdgpu_device *adev = dev->dev_private;
864 /* XXX check mode bandwidth */
866 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
867 return MODE_CLOCK_HIGH;
872 static enum drm_connector_status
873 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
875 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
876 struct drm_encoder *encoder;
877 const struct drm_encoder_helper_funcs *encoder_funcs;
879 enum drm_connector_status ret = connector_status_disconnected;
882 if (!drm_kms_helper_is_poll_worker()) {
883 r = pm_runtime_get_sync(connector->dev->dev);
885 pm_runtime_put_autosuspend(connector->dev->dev);
886 return connector_status_disconnected;
890 encoder = amdgpu_connector_best_single_encoder(connector);
892 ret = connector_status_disconnected;
894 if (amdgpu_connector->ddc_bus)
895 dret = amdgpu_ddc_probe(amdgpu_connector, false);
897 amdgpu_connector->detected_by_load = false;
898 amdgpu_connector_free_edid(connector);
899 amdgpu_connector_get_edid(connector);
901 if (!amdgpu_connector->edid) {
902 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
904 ret = connector_status_connected;
906 amdgpu_connector->use_digital =
907 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
909 /* some oems have boards with separate digital and analog connectors
910 * with a shared ddc line (often vga + hdmi)
912 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
913 amdgpu_connector_free_edid(connector);
914 ret = connector_status_disconnected;
916 ret = connector_status_connected;
921 /* if we aren't forcing don't do destructive polling */
923 /* only return the previous status if we last
924 * detected a monitor via load.
926 if (amdgpu_connector->detected_by_load)
927 ret = connector->status;
931 if (amdgpu_connector->dac_load_detect && encoder) {
932 encoder_funcs = encoder->helper_private;
933 ret = encoder_funcs->detect(encoder, connector);
934 if (ret != connector_status_disconnected)
935 amdgpu_connector->detected_by_load = true;
939 amdgpu_connector_update_scratch_regs(connector, ret);
942 if (!drm_kms_helper_is_poll_worker()) {
943 pm_runtime_mark_last_busy(connector->dev->dev);
944 pm_runtime_put_autosuspend(connector->dev->dev);
950 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
951 .get_modes = amdgpu_connector_vga_get_modes,
952 .mode_valid = amdgpu_connector_vga_mode_valid,
953 .best_encoder = amdgpu_connector_best_single_encoder,
956 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
957 .dpms = drm_helper_connector_dpms,
958 .detect = amdgpu_connector_vga_detect,
959 .fill_modes = drm_helper_probe_single_connector_modes,
960 .early_unregister = amdgpu_connector_unregister,
961 .destroy = amdgpu_connector_destroy,
962 .set_property = amdgpu_connector_set_property,
966 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
968 struct drm_device *dev = connector->dev;
969 struct amdgpu_device *adev = dev->dev_private;
970 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
971 enum drm_connector_status status;
973 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
974 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
975 status = connector_status_connected;
977 status = connector_status_disconnected;
978 if (connector->status == status)
987 * Do a DDC probe, if DDC probe passes, get the full EDID so
988 * we can do analog/digital monitor detection at this point.
989 * If the monitor is an analog monitor or we got no DDC,
990 * we need to find the DAC encoder object for this connector.
991 * If we got no DDC, we do load detection on the DAC encoder object.
992 * If we got analog DDC or load detection passes on the DAC encoder
993 * we have to check if this analog encoder is shared with anyone else (TV)
994 * if its shared we have to set the other connector to disconnected.
996 static enum drm_connector_status
997 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
999 struct drm_device *dev = connector->dev;
1000 struct amdgpu_device *adev = dev->dev_private;
1001 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1002 struct drm_encoder *encoder = NULL;
1003 const struct drm_encoder_helper_funcs *encoder_funcs;
1005 enum drm_connector_status ret = connector_status_disconnected;
1006 bool dret = false, broken_edid = false;
1008 if (!drm_kms_helper_is_poll_worker()) {
1009 r = pm_runtime_get_sync(connector->dev->dev);
1011 pm_runtime_put_autosuspend(connector->dev->dev);
1012 return connector_status_disconnected;
1016 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1017 ret = connector->status;
1021 if (amdgpu_connector->ddc_bus)
1022 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1024 amdgpu_connector->detected_by_load = false;
1025 amdgpu_connector_free_edid(connector);
1026 amdgpu_connector_get_edid(connector);
1028 if (!amdgpu_connector->edid) {
1029 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1031 ret = connector_status_connected;
1032 broken_edid = true; /* defer use_digital to later */
1034 amdgpu_connector->use_digital =
1035 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1037 /* some oems have boards with separate digital and analog connectors
1038 * with a shared ddc line (often vga + hdmi)
1040 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1041 amdgpu_connector_free_edid(connector);
1042 ret = connector_status_disconnected;
1044 ret = connector_status_connected;
1047 /* This gets complicated. We have boards with VGA + HDMI with a
1048 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1049 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1050 * you don't really know what's connected to which port as both are digital.
1052 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1053 struct drm_connector *list_connector;
1054 struct amdgpu_connector *list_amdgpu_connector;
1055 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1056 if (connector == list_connector)
1058 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1059 if (list_amdgpu_connector->shared_ddc &&
1060 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1061 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1062 /* cases where both connectors are digital */
1063 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1064 /* hpd is our only option in this case */
1065 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1066 amdgpu_connector_free_edid(connector);
1067 ret = connector_status_disconnected;
1076 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1079 /* DVI-D and HDMI-A are digital only */
1080 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1081 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1084 /* if we aren't forcing don't do destructive polling */
1086 /* only return the previous status if we last
1087 * detected a monitor via load.
1089 if (amdgpu_connector->detected_by_load)
1090 ret = connector->status;
1094 /* find analog encoder */
1095 if (amdgpu_connector->dac_load_detect) {
1096 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1097 if (connector->encoder_ids[i] == 0)
1100 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1104 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1105 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1108 encoder_funcs = encoder->helper_private;
1109 if (encoder_funcs->detect) {
1111 if (ret != connector_status_connected) {
1112 /* deal with analog monitors without DDC */
1113 ret = encoder_funcs->detect(encoder, connector);
1114 if (ret == connector_status_connected) {
1115 amdgpu_connector->use_digital = false;
1117 if (ret != connector_status_disconnected)
1118 amdgpu_connector->detected_by_load = true;
1121 enum drm_connector_status lret;
1122 /* assume digital unless load detected otherwise */
1123 amdgpu_connector->use_digital = true;
1124 lret = encoder_funcs->detect(encoder, connector);
1125 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1126 if (lret == connector_status_connected)
1127 amdgpu_connector->use_digital = false;
1135 /* updated in get modes as well since we need to know if it's analog or digital */
1136 amdgpu_connector_update_scratch_regs(connector, ret);
1139 if (!drm_kms_helper_is_poll_worker()) {
1140 pm_runtime_mark_last_busy(connector->dev->dev);
1141 pm_runtime_put_autosuspend(connector->dev->dev);
1147 /* okay need to be smart in here about which encoder to pick */
1148 static struct drm_encoder *
1149 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1151 int enc_id = connector->encoder_ids[0];
1152 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1153 struct drm_encoder *encoder;
1155 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1156 if (connector->encoder_ids[i] == 0)
1159 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1163 if (amdgpu_connector->use_digital == true) {
1164 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1167 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1168 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1173 /* see if we have a default encoder TODO */
1175 /* then check use digitial */
1176 /* pick the first one */
1178 return drm_encoder_find(connector->dev, enc_id);
1182 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1184 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1185 if (connector->force == DRM_FORCE_ON)
1186 amdgpu_connector->use_digital = false;
1187 if (connector->force == DRM_FORCE_ON_DIGITAL)
1188 amdgpu_connector->use_digital = true;
1191 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1192 struct drm_display_mode *mode)
1194 struct drm_device *dev = connector->dev;
1195 struct amdgpu_device *adev = dev->dev_private;
1196 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1198 /* XXX check mode bandwidth */
1200 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1201 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1202 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1203 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1205 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1206 /* HDMI 1.3+ supports max clock of 340 Mhz */
1207 if (mode->clock > 340000)
1208 return MODE_CLOCK_HIGH;
1212 return MODE_CLOCK_HIGH;
1216 /* check against the max pixel clock */
1217 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1218 return MODE_CLOCK_HIGH;
1223 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1224 .get_modes = amdgpu_connector_vga_get_modes,
1225 .mode_valid = amdgpu_connector_dvi_mode_valid,
1226 .best_encoder = amdgpu_connector_dvi_encoder,
1229 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1230 .dpms = drm_helper_connector_dpms,
1231 .detect = amdgpu_connector_dvi_detect,
1232 .fill_modes = drm_helper_probe_single_connector_modes,
1233 .set_property = amdgpu_connector_set_property,
1234 .early_unregister = amdgpu_connector_unregister,
1235 .destroy = amdgpu_connector_destroy,
1236 .force = amdgpu_connector_dvi_force,
1239 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1241 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1242 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1243 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1246 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1247 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1248 struct drm_display_mode *mode;
1250 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1251 if (!amdgpu_dig_connector->edp_on)
1252 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1253 ATOM_TRANSMITTER_ACTION_POWER_ON);
1254 amdgpu_connector_get_edid(connector);
1255 ret = amdgpu_connector_ddc_get_modes(connector);
1256 if (!amdgpu_dig_connector->edp_on)
1257 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1258 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1260 /* need to setup ddc on the bridge */
1261 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1262 ENCODER_OBJECT_ID_NONE) {
1264 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1266 amdgpu_connector_get_edid(connector);
1267 ret = amdgpu_connector_ddc_get_modes(connector);
1272 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1273 /* add scaled modes */
1274 amdgpu_connector_add_common_modes(encoder, connector);
1282 /* we have no EDID modes */
1283 mode = amdgpu_connector_lcd_native_mode(encoder);
1286 drm_mode_probed_add(connector, mode);
1287 /* add the width/height from vbios tables if available */
1288 connector->display_info.width_mm = mode->width_mm;
1289 connector->display_info.height_mm = mode->height_mm;
1290 /* add scaled modes */
1291 amdgpu_connector_add_common_modes(encoder, connector);
1294 /* need to setup ddc on the bridge */
1295 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1296 ENCODER_OBJECT_ID_NONE) {
1298 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1300 amdgpu_connector_get_edid(connector);
1301 ret = amdgpu_connector_ddc_get_modes(connector);
1303 amdgpu_get_native_mode(connector);
1309 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1311 struct drm_encoder *encoder;
1312 struct amdgpu_encoder *amdgpu_encoder;
1315 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1316 if (connector->encoder_ids[i] == 0)
1319 encoder = drm_encoder_find(connector->dev,
1320 connector->encoder_ids[i]);
1324 amdgpu_encoder = to_amdgpu_encoder(encoder);
1326 switch (amdgpu_encoder->encoder_id) {
1327 case ENCODER_OBJECT_ID_TRAVIS:
1328 case ENCODER_OBJECT_ID_NUTMEG:
1329 return amdgpu_encoder->encoder_id;
1335 return ENCODER_OBJECT_ID_NONE;
1338 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1340 struct drm_encoder *encoder;
1341 struct amdgpu_encoder *amdgpu_encoder;
1345 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1346 if (connector->encoder_ids[i] == 0)
1348 encoder = drm_encoder_find(connector->dev,
1349 connector->encoder_ids[i]);
1353 amdgpu_encoder = to_amdgpu_encoder(encoder);
1354 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1361 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1363 struct drm_device *dev = connector->dev;
1364 struct amdgpu_device *adev = dev->dev_private;
1366 if ((adev->clock.default_dispclk >= 53900) &&
1367 amdgpu_connector_encoder_is_hbr2(connector)) {
1374 static enum drm_connector_status
1375 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1377 struct drm_device *dev = connector->dev;
1378 struct amdgpu_device *adev = dev->dev_private;
1379 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1380 enum drm_connector_status ret = connector_status_disconnected;
1381 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1382 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1385 if (!drm_kms_helper_is_poll_worker()) {
1386 r = pm_runtime_get_sync(connector->dev->dev);
1388 pm_runtime_put_autosuspend(connector->dev->dev);
1389 return connector_status_disconnected;
1393 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1394 ret = connector->status;
1398 amdgpu_connector_free_edid(connector);
1400 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1401 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1403 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1404 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1406 /* check if panel is valid */
1407 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1408 ret = connector_status_connected;
1410 /* eDP is always DP */
1411 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1412 if (!amdgpu_dig_connector->edp_on)
1413 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1414 ATOM_TRANSMITTER_ACTION_POWER_ON);
1415 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1416 ret = connector_status_connected;
1417 if (!amdgpu_dig_connector->edp_on)
1418 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1419 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1420 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1421 ENCODER_OBJECT_ID_NONE) {
1422 /* DP bridges are always DP */
1423 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1424 /* get the DPCD from the bridge */
1425 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1428 /* setup ddc on the bridge */
1429 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1430 /* bridge chips are always aux */
1431 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1432 ret = connector_status_connected;
1433 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1434 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1435 ret = encoder_funcs->detect(encoder, connector);
1439 amdgpu_dig_connector->dp_sink_type =
1440 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1441 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1442 ret = connector_status_connected;
1443 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1444 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1446 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1447 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1448 ret = connector_status_connected;
1450 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1451 if (amdgpu_ddc_probe(amdgpu_connector, false))
1452 ret = connector_status_connected;
1457 amdgpu_connector_update_scratch_regs(connector, ret);
1459 if (!drm_kms_helper_is_poll_worker()) {
1460 pm_runtime_mark_last_busy(connector->dev->dev);
1461 pm_runtime_put_autosuspend(connector->dev->dev);
1467 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1468 struct drm_display_mode *mode)
1470 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1471 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1473 /* XXX check mode bandwidth */
1475 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1476 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1477 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1479 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1483 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1484 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1486 /* AVIVO hardware supports downscaling modes larger than the panel
1487 * to the panel size, but I'm not sure this is desirable.
1489 if ((mode->hdisplay > native_mode->hdisplay) ||
1490 (mode->vdisplay > native_mode->vdisplay))
1493 /* if scaling is disabled, block non-native modes */
1494 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1495 if ((mode->hdisplay != native_mode->hdisplay) ||
1496 (mode->vdisplay != native_mode->vdisplay))
1502 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1503 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1504 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1506 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1507 /* HDMI 1.3+ supports max clock of 340 Mhz */
1508 if (mode->clock > 340000)
1509 return MODE_CLOCK_HIGH;
1511 if (mode->clock > 165000)
1512 return MODE_CLOCK_HIGH;
1520 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1521 .get_modes = amdgpu_connector_dp_get_modes,
1522 .mode_valid = amdgpu_connector_dp_mode_valid,
1523 .best_encoder = amdgpu_connector_dvi_encoder,
1526 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1527 .dpms = drm_helper_connector_dpms,
1528 .detect = amdgpu_connector_dp_detect,
1529 .fill_modes = drm_helper_probe_single_connector_modes,
1530 .set_property = amdgpu_connector_set_property,
1531 .early_unregister = amdgpu_connector_unregister,
1532 .destroy = amdgpu_connector_destroy,
1533 .force = amdgpu_connector_dvi_force,
1536 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1537 .dpms = drm_helper_connector_dpms,
1538 .detect = amdgpu_connector_dp_detect,
1539 .fill_modes = drm_helper_probe_single_connector_modes,
1540 .set_property = amdgpu_connector_set_lcd_property,
1541 .early_unregister = amdgpu_connector_unregister,
1542 .destroy = amdgpu_connector_destroy,
1543 .force = amdgpu_connector_dvi_force,
1547 amdgpu_connector_add(struct amdgpu_device *adev,
1548 uint32_t connector_id,
1549 uint32_t supported_device,
1551 struct amdgpu_i2c_bus_rec *i2c_bus,
1552 uint16_t connector_object_id,
1553 struct amdgpu_hpd *hpd,
1554 struct amdgpu_router *router)
1556 struct drm_device *dev = adev->ddev;
1557 struct drm_connector *connector;
1558 struct amdgpu_connector *amdgpu_connector;
1559 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1560 struct drm_encoder *encoder;
1561 struct amdgpu_encoder *amdgpu_encoder;
1562 uint32_t subpixel_order = SubPixelNone;
1563 bool shared_ddc = false;
1564 bool is_dp_bridge = false;
1565 bool has_aux = false;
1567 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1570 /* see if we already added it */
1571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1572 amdgpu_connector = to_amdgpu_connector(connector);
1573 if (amdgpu_connector->connector_id == connector_id) {
1574 amdgpu_connector->devices |= supported_device;
1577 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1578 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1579 amdgpu_connector->shared_ddc = true;
1582 if (amdgpu_connector->router_bus && router->ddc_valid &&
1583 (amdgpu_connector->router.router_id == router->router_id)) {
1584 amdgpu_connector->shared_ddc = false;
1590 /* check if it's a dp bridge */
1591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1592 amdgpu_encoder = to_amdgpu_encoder(encoder);
1593 if (amdgpu_encoder->devices & supported_device) {
1594 switch (amdgpu_encoder->encoder_id) {
1595 case ENCODER_OBJECT_ID_TRAVIS:
1596 case ENCODER_OBJECT_ID_NUTMEG:
1597 is_dp_bridge = true;
1605 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1606 if (!amdgpu_connector)
1609 connector = &amdgpu_connector->base;
1611 amdgpu_connector->connector_id = connector_id;
1612 amdgpu_connector->devices = supported_device;
1613 amdgpu_connector->shared_ddc = shared_ddc;
1614 amdgpu_connector->connector_object_id = connector_object_id;
1615 amdgpu_connector->hpd = *hpd;
1617 amdgpu_connector->router = *router;
1618 if (router->ddc_valid || router->cd_valid) {
1619 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1620 if (!amdgpu_connector->router_bus)
1621 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1625 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1626 if (!amdgpu_dig_connector)
1628 amdgpu_connector->con_priv = amdgpu_dig_connector;
1629 if (i2c_bus->valid) {
1630 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1631 if (amdgpu_connector->ddc_bus)
1634 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1636 switch (connector_type) {
1637 case DRM_MODE_CONNECTOR_VGA:
1638 case DRM_MODE_CONNECTOR_DVIA:
1640 drm_connector_init(dev, &amdgpu_connector->base,
1641 &amdgpu_connector_dp_funcs, connector_type);
1642 drm_connector_helper_add(&amdgpu_connector->base,
1643 &amdgpu_connector_dp_helper_funcs);
1644 connector->interlace_allowed = true;
1645 connector->doublescan_allowed = true;
1646 amdgpu_connector->dac_load_detect = true;
1647 drm_object_attach_property(&amdgpu_connector->base.base,
1648 adev->mode_info.load_detect_property,
1650 drm_object_attach_property(&amdgpu_connector->base.base,
1651 dev->mode_config.scaling_mode_property,
1652 DRM_MODE_SCALE_NONE);
1654 case DRM_MODE_CONNECTOR_DVII:
1655 case DRM_MODE_CONNECTOR_DVID:
1656 case DRM_MODE_CONNECTOR_HDMIA:
1657 case DRM_MODE_CONNECTOR_HDMIB:
1658 case DRM_MODE_CONNECTOR_DisplayPort:
1659 drm_connector_init(dev, &amdgpu_connector->base,
1660 &amdgpu_connector_dp_funcs, connector_type);
1661 drm_connector_helper_add(&amdgpu_connector->base,
1662 &amdgpu_connector_dp_helper_funcs);
1663 drm_object_attach_property(&amdgpu_connector->base.base,
1664 adev->mode_info.underscan_property,
1666 drm_object_attach_property(&amdgpu_connector->base.base,
1667 adev->mode_info.underscan_hborder_property,
1669 drm_object_attach_property(&amdgpu_connector->base.base,
1670 adev->mode_info.underscan_vborder_property,
1673 drm_object_attach_property(&amdgpu_connector->base.base,
1674 dev->mode_config.scaling_mode_property,
1675 DRM_MODE_SCALE_NONE);
1677 drm_object_attach_property(&amdgpu_connector->base.base,
1678 adev->mode_info.dither_property,
1679 AMDGPU_FMT_DITHER_DISABLE);
1681 if (amdgpu_audio != 0) {
1682 drm_object_attach_property(&amdgpu_connector->base.base,
1683 adev->mode_info.audio_property,
1685 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1688 subpixel_order = SubPixelHorizontalRGB;
1689 connector->interlace_allowed = true;
1690 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1691 connector->doublescan_allowed = true;
1693 connector->doublescan_allowed = false;
1694 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1695 amdgpu_connector->dac_load_detect = true;
1696 drm_object_attach_property(&amdgpu_connector->base.base,
1697 adev->mode_info.load_detect_property,
1701 case DRM_MODE_CONNECTOR_LVDS:
1702 case DRM_MODE_CONNECTOR_eDP:
1703 drm_connector_init(dev, &amdgpu_connector->base,
1704 &amdgpu_connector_edp_funcs, connector_type);
1705 drm_connector_helper_add(&amdgpu_connector->base,
1706 &amdgpu_connector_dp_helper_funcs);
1707 drm_object_attach_property(&amdgpu_connector->base.base,
1708 dev->mode_config.scaling_mode_property,
1709 DRM_MODE_SCALE_FULLSCREEN);
1710 subpixel_order = SubPixelHorizontalRGB;
1711 connector->interlace_allowed = false;
1712 connector->doublescan_allowed = false;
1716 switch (connector_type) {
1717 case DRM_MODE_CONNECTOR_VGA:
1718 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1719 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1720 if (i2c_bus->valid) {
1721 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1722 if (!amdgpu_connector->ddc_bus)
1723 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1725 amdgpu_connector->dac_load_detect = true;
1726 drm_object_attach_property(&amdgpu_connector->base.base,
1727 adev->mode_info.load_detect_property,
1729 drm_object_attach_property(&amdgpu_connector->base.base,
1730 dev->mode_config.scaling_mode_property,
1731 DRM_MODE_SCALE_NONE);
1732 /* no HPD on analog connectors */
1733 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1734 connector->interlace_allowed = true;
1735 connector->doublescan_allowed = true;
1737 case DRM_MODE_CONNECTOR_DVIA:
1738 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1739 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1740 if (i2c_bus->valid) {
1741 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1742 if (!amdgpu_connector->ddc_bus)
1743 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1745 amdgpu_connector->dac_load_detect = true;
1746 drm_object_attach_property(&amdgpu_connector->base.base,
1747 adev->mode_info.load_detect_property,
1749 drm_object_attach_property(&amdgpu_connector->base.base,
1750 dev->mode_config.scaling_mode_property,
1751 DRM_MODE_SCALE_NONE);
1752 /* no HPD on analog connectors */
1753 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1754 connector->interlace_allowed = true;
1755 connector->doublescan_allowed = true;
1757 case DRM_MODE_CONNECTOR_DVII:
1758 case DRM_MODE_CONNECTOR_DVID:
1759 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1760 if (!amdgpu_dig_connector)
1762 amdgpu_connector->con_priv = amdgpu_dig_connector;
1763 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1764 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1765 if (i2c_bus->valid) {
1766 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1767 if (!amdgpu_connector->ddc_bus)
1768 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1770 subpixel_order = SubPixelHorizontalRGB;
1771 drm_object_attach_property(&amdgpu_connector->base.base,
1772 adev->mode_info.coherent_mode_property,
1774 drm_object_attach_property(&amdgpu_connector->base.base,
1775 adev->mode_info.underscan_property,
1777 drm_object_attach_property(&amdgpu_connector->base.base,
1778 adev->mode_info.underscan_hborder_property,
1780 drm_object_attach_property(&amdgpu_connector->base.base,
1781 adev->mode_info.underscan_vborder_property,
1783 drm_object_attach_property(&amdgpu_connector->base.base,
1784 dev->mode_config.scaling_mode_property,
1785 DRM_MODE_SCALE_NONE);
1787 if (amdgpu_audio != 0) {
1788 drm_object_attach_property(&amdgpu_connector->base.base,
1789 adev->mode_info.audio_property,
1791 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1793 drm_object_attach_property(&amdgpu_connector->base.base,
1794 adev->mode_info.dither_property,
1795 AMDGPU_FMT_DITHER_DISABLE);
1796 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1797 amdgpu_connector->dac_load_detect = true;
1798 drm_object_attach_property(&amdgpu_connector->base.base,
1799 adev->mode_info.load_detect_property,
1802 connector->interlace_allowed = true;
1803 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1804 connector->doublescan_allowed = true;
1806 connector->doublescan_allowed = false;
1808 case DRM_MODE_CONNECTOR_HDMIA:
1809 case DRM_MODE_CONNECTOR_HDMIB:
1810 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1811 if (!amdgpu_dig_connector)
1813 amdgpu_connector->con_priv = amdgpu_dig_connector;
1814 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1815 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1816 if (i2c_bus->valid) {
1817 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1818 if (!amdgpu_connector->ddc_bus)
1819 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1821 drm_object_attach_property(&amdgpu_connector->base.base,
1822 adev->mode_info.coherent_mode_property,
1824 drm_object_attach_property(&amdgpu_connector->base.base,
1825 adev->mode_info.underscan_property,
1827 drm_object_attach_property(&amdgpu_connector->base.base,
1828 adev->mode_info.underscan_hborder_property,
1830 drm_object_attach_property(&amdgpu_connector->base.base,
1831 adev->mode_info.underscan_vborder_property,
1833 drm_object_attach_property(&amdgpu_connector->base.base,
1834 dev->mode_config.scaling_mode_property,
1835 DRM_MODE_SCALE_NONE);
1836 if (amdgpu_audio != 0) {
1837 drm_object_attach_property(&amdgpu_connector->base.base,
1838 adev->mode_info.audio_property,
1840 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1842 drm_object_attach_property(&amdgpu_connector->base.base,
1843 adev->mode_info.dither_property,
1844 AMDGPU_FMT_DITHER_DISABLE);
1845 subpixel_order = SubPixelHorizontalRGB;
1846 connector->interlace_allowed = true;
1847 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1848 connector->doublescan_allowed = true;
1850 connector->doublescan_allowed = false;
1852 case DRM_MODE_CONNECTOR_DisplayPort:
1853 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1854 if (!amdgpu_dig_connector)
1856 amdgpu_connector->con_priv = amdgpu_dig_connector;
1857 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1858 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1859 if (i2c_bus->valid) {
1860 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1861 if (amdgpu_connector->ddc_bus)
1864 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1866 subpixel_order = SubPixelHorizontalRGB;
1867 drm_object_attach_property(&amdgpu_connector->base.base,
1868 adev->mode_info.coherent_mode_property,
1870 drm_object_attach_property(&amdgpu_connector->base.base,
1871 adev->mode_info.underscan_property,
1873 drm_object_attach_property(&amdgpu_connector->base.base,
1874 adev->mode_info.underscan_hborder_property,
1876 drm_object_attach_property(&amdgpu_connector->base.base,
1877 adev->mode_info.underscan_vborder_property,
1879 drm_object_attach_property(&amdgpu_connector->base.base,
1880 dev->mode_config.scaling_mode_property,
1881 DRM_MODE_SCALE_NONE);
1882 if (amdgpu_audio != 0) {
1883 drm_object_attach_property(&amdgpu_connector->base.base,
1884 adev->mode_info.audio_property,
1886 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1888 drm_object_attach_property(&amdgpu_connector->base.base,
1889 adev->mode_info.dither_property,
1890 AMDGPU_FMT_DITHER_DISABLE);
1891 connector->interlace_allowed = true;
1892 /* in theory with a DP to VGA converter... */
1893 connector->doublescan_allowed = false;
1895 case DRM_MODE_CONNECTOR_eDP:
1896 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1897 if (!amdgpu_dig_connector)
1899 amdgpu_connector->con_priv = amdgpu_dig_connector;
1900 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1901 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1902 if (i2c_bus->valid) {
1903 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1904 if (amdgpu_connector->ddc_bus)
1907 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1909 drm_object_attach_property(&amdgpu_connector->base.base,
1910 dev->mode_config.scaling_mode_property,
1911 DRM_MODE_SCALE_FULLSCREEN);
1912 subpixel_order = SubPixelHorizontalRGB;
1913 connector->interlace_allowed = false;
1914 connector->doublescan_allowed = false;
1916 case DRM_MODE_CONNECTOR_LVDS:
1917 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1918 if (!amdgpu_dig_connector)
1920 amdgpu_connector->con_priv = amdgpu_dig_connector;
1921 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1922 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1923 if (i2c_bus->valid) {
1924 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1925 if (!amdgpu_connector->ddc_bus)
1926 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1928 drm_object_attach_property(&amdgpu_connector->base.base,
1929 dev->mode_config.scaling_mode_property,
1930 DRM_MODE_SCALE_FULLSCREEN);
1931 subpixel_order = SubPixelHorizontalRGB;
1932 connector->interlace_allowed = false;
1933 connector->doublescan_allowed = false;
1938 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1939 if (i2c_bus->valid) {
1940 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1941 DRM_CONNECTOR_POLL_DISCONNECT;
1944 connector->polled = DRM_CONNECTOR_POLL_HPD;
1946 connector->display_info.subpixel_order = subpixel_order;
1947 drm_connector_register(connector);
1950 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1955 drm_connector_cleanup(connector);