2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_edid.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/amdgpu_drm.h>
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
38 #include <linux/pm_runtime.h>
40 void amdgpu_connector_hotplug(struct drm_connector *connector)
42 struct drm_device *dev = connector->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
46 /* bail if the connector does not have hpd pin, e.g.,
49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
54 /* if the connector is already off, don't turn it back on */
55 if (connector->dpms != DRM_MODE_DPMS_ON)
58 /* just deal with DP (not eDP) here. */
59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60 struct amdgpu_connector_atom_dig *dig_connector =
61 amdgpu_connector->con_priv;
63 /* if existing sink type was not DP no need to retrain */
64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
67 /* first get sink type as it may be reset after (un)plug */
68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor
72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 /* Don't start link training before we have the DPCD */
76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
79 /* Turn the connector off and back on immediately, which
80 * will trigger link training
82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
90 struct drm_crtc *crtc = encoder->crtc;
92 if (crtc && crtc->enabled) {
93 drm_crtc_helper_set_mode(crtc, &crtc->mode,
94 crtc->x, crtc->y, crtc->primary->fb);
98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
101 struct amdgpu_connector_atom_dig *dig_connector;
103 unsigned mode_clock, max_tmds_clock;
105 switch (connector->connector_type) {
106 case DRM_MODE_CONNECTOR_DVII:
107 case DRM_MODE_CONNECTOR_HDMIB:
108 if (amdgpu_connector->use_digital) {
109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
110 if (connector->display_info.bpc)
111 bpc = connector->display_info.bpc;
115 case DRM_MODE_CONNECTOR_DVID:
116 case DRM_MODE_CONNECTOR_HDMIA:
117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
118 if (connector->display_info.bpc)
119 bpc = connector->display_info.bpc;
122 case DRM_MODE_CONNECTOR_DisplayPort:
123 dig_connector = amdgpu_connector->con_priv;
124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
127 if (connector->display_info.bpc)
128 bpc = connector->display_info.bpc;
131 case DRM_MODE_CONNECTOR_eDP:
132 case DRM_MODE_CONNECTOR_LVDS:
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
136 const struct drm_connector_helper_funcs *connector_funcs =
137 connector->helper_private;
138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
154 * 12 bpc is always supported on hdmi deep color sinks, as this is
155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
159 connector->name, bpc);
163 /* Any defined maximum tmds clock limit we must not exceed? */
164 if (connector->display_info.max_tmds_clock > 0) {
165 /* mode_clock is clock in kHz for mode to be modeset on this connector */
166 mode_clock = amdgpu_connector->pixelclock_for_modeset;
168 /* Maximum allowable input clock in kHz */
169 max_tmds_clock = connector->display_info.max_tmds_clock;
171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
172 connector->name, mode_clock, max_tmds_clock);
174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
177 (mode_clock * 5/4 <= max_tmds_clock))
182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
183 connector->name, bpc);
186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
189 connector->name, bpc);
191 } else if (bpc > 8) {
192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
199 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
206 connector->name, connector->display_info.bpc, bpc);
212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
213 enum drm_connector_status status)
215 struct drm_encoder *best_encoder = NULL;
216 struct drm_encoder *encoder = NULL;
217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221 best_encoder = connector_funcs->best_encoder(connector);
223 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
224 if (connector->encoder_ids[i] == 0)
227 encoder = drm_encoder_find(connector->dev,
228 connector->encoder_ids[i]);
232 if ((encoder == best_encoder) && (status == connector_status_connected))
237 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
242 static struct drm_encoder *
243 amdgpu_connector_find_encoder(struct drm_connector *connector,
246 struct drm_encoder *encoder;
249 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
250 if (connector->encoder_ids[i] == 0)
252 encoder = drm_encoder_find(connector->dev,
253 connector->encoder_ids[i]);
257 if (encoder->encoder_type == encoder_type)
263 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
265 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
266 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
268 if (amdgpu_connector->edid) {
269 return amdgpu_connector->edid;
270 } else if (edid_blob) {
271 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
273 amdgpu_connector->edid = edid;
275 return amdgpu_connector->edid;
279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
283 if (adev->mode_info.bios_hardcoded_edid) {
284 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
286 memcpy((unsigned char *)edid,
287 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
288 adev->mode_info.bios_hardcoded_edid_size);
295 static void amdgpu_connector_get_edid(struct drm_connector *connector)
297 struct drm_device *dev = connector->dev;
298 struct amdgpu_device *adev = dev->dev_private;
299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
301 if (amdgpu_connector->edid)
304 /* on hw with routers, select right port */
305 if (amdgpu_connector->router.ddc_valid)
306 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
308 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309 ENCODER_OBJECT_ID_NONE) &&
310 amdgpu_connector->ddc_bus->has_aux) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->aux.ddc);
313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319 amdgpu_connector->ddc_bus->has_aux)
320 amdgpu_connector->edid = drm_get_edid(connector,
321 &amdgpu_connector->ddc_bus->aux.ddc);
322 else if (amdgpu_connector->ddc_bus)
323 amdgpu_connector->edid = drm_get_edid(connector,
324 &amdgpu_connector->ddc_bus->adapter);
325 } else if (amdgpu_connector->ddc_bus) {
326 amdgpu_connector->edid = drm_get_edid(connector,
327 &amdgpu_connector->ddc_bus->adapter);
330 if (!amdgpu_connector->edid) {
331 /* some laptops provide a hardcoded edid in rom for LCDs */
332 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
333 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
334 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
338 static void amdgpu_connector_free_edid(struct drm_connector *connector)
340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
342 if (amdgpu_connector->edid) {
343 kfree(amdgpu_connector->edid);
344 amdgpu_connector->edid = NULL;
348 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
350 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
353 if (amdgpu_connector->edid) {
354 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
355 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
356 drm_edid_to_eld(connector, amdgpu_connector->edid);
359 drm_mode_connector_update_edid_property(connector, NULL);
363 static struct drm_encoder *
364 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
366 int enc_id = connector->encoder_ids[0];
368 /* pick the encoder ids */
370 return drm_encoder_find(connector->dev, enc_id);
374 static void amdgpu_get_native_mode(struct drm_connector *connector)
376 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
377 struct amdgpu_encoder *amdgpu_encoder;
382 amdgpu_encoder = to_amdgpu_encoder(encoder);
384 if (!list_empty(&connector->probed_modes)) {
385 struct drm_display_mode *preferred_mode =
386 list_first_entry(&connector->probed_modes,
387 struct drm_display_mode, head);
389 amdgpu_encoder->native_mode = *preferred_mode;
391 amdgpu_encoder->native_mode.clock = 0;
395 static struct drm_display_mode *
396 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
398 struct drm_device *dev = encoder->dev;
399 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
400 struct drm_display_mode *mode = NULL;
401 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
403 if (native_mode->hdisplay != 0 &&
404 native_mode->vdisplay != 0 &&
405 native_mode->clock != 0) {
406 mode = drm_mode_duplicate(dev, native_mode);
407 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
408 drm_mode_set_name(mode);
410 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
411 } else if (native_mode->hdisplay != 0 &&
412 native_mode->vdisplay != 0) {
413 /* mac laptops without an edid */
414 /* Note that this is not necessarily the exact panel mode,
415 * but an approximation based on the cvt formula. For these
416 * systems we should ideally read the mode info out of the
417 * registers or add a mode table, but this works and is much
420 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
421 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
422 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
427 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
428 struct drm_connector *connector)
430 struct drm_device *dev = encoder->dev;
431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
432 struct drm_display_mode *mode = NULL;
433 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
435 static const struct mode_size {
438 } common_modes[17] = {
458 for (i = 0; i < 17; i++) {
459 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
460 if (common_modes[i].w > 1024 ||
461 common_modes[i].h > 768)
464 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
465 if (common_modes[i].w > native_mode->hdisplay ||
466 common_modes[i].h > native_mode->vdisplay ||
467 (common_modes[i].w == native_mode->hdisplay &&
468 common_modes[i].h == native_mode->vdisplay))
471 if (common_modes[i].w < 320 || common_modes[i].h < 200)
474 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
475 drm_mode_probed_add(connector, mode);
479 static int amdgpu_connector_set_property(struct drm_connector *connector,
480 struct drm_property *property,
483 struct drm_device *dev = connector->dev;
484 struct amdgpu_device *adev = dev->dev_private;
485 struct drm_encoder *encoder;
486 struct amdgpu_encoder *amdgpu_encoder;
488 if (property == adev->mode_info.coherent_mode_property) {
489 struct amdgpu_encoder_atom_dig *dig;
490 bool new_coherent_mode;
492 /* need to find digital encoder on connector */
493 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
497 amdgpu_encoder = to_amdgpu_encoder(encoder);
499 if (!amdgpu_encoder->enc_priv)
502 dig = amdgpu_encoder->enc_priv;
503 new_coherent_mode = val ? true : false;
504 if (dig->coherent_mode != new_coherent_mode) {
505 dig->coherent_mode = new_coherent_mode;
506 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
510 if (property == adev->mode_info.audio_property) {
511 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
512 /* need to find digital encoder on connector */
513 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
517 amdgpu_encoder = to_amdgpu_encoder(encoder);
519 if (amdgpu_connector->audio != val) {
520 amdgpu_connector->audio = val;
521 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
525 if (property == adev->mode_info.dither_property) {
526 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
527 /* need to find digital encoder on connector */
528 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
532 amdgpu_encoder = to_amdgpu_encoder(encoder);
534 if (amdgpu_connector->dither != val) {
535 amdgpu_connector->dither = val;
536 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
540 if (property == adev->mode_info.underscan_property) {
541 /* need to find digital encoder on connector */
542 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
546 amdgpu_encoder = to_amdgpu_encoder(encoder);
548 if (amdgpu_encoder->underscan_type != val) {
549 amdgpu_encoder->underscan_type = val;
550 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
554 if (property == adev->mode_info.underscan_hborder_property) {
555 /* need to find digital encoder on connector */
556 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
560 amdgpu_encoder = to_amdgpu_encoder(encoder);
562 if (amdgpu_encoder->underscan_hborder != val) {
563 amdgpu_encoder->underscan_hborder = val;
564 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
568 if (property == adev->mode_info.underscan_vborder_property) {
569 /* need to find digital encoder on connector */
570 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
574 amdgpu_encoder = to_amdgpu_encoder(encoder);
576 if (amdgpu_encoder->underscan_vborder != val) {
577 amdgpu_encoder->underscan_vborder = val;
578 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
582 if (property == adev->mode_info.load_detect_property) {
583 struct amdgpu_connector *amdgpu_connector =
584 to_amdgpu_connector(connector);
587 amdgpu_connector->dac_load_detect = false;
589 amdgpu_connector->dac_load_detect = true;
592 if (property == dev->mode_config.scaling_mode_property) {
593 enum amdgpu_rmx_type rmx_type;
595 if (connector->encoder) {
596 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
598 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
599 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
604 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
605 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
606 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
607 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
609 if (amdgpu_encoder->rmx_type == rmx_type)
612 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
613 (amdgpu_encoder->native_mode.clock == 0))
616 amdgpu_encoder->rmx_type = rmx_type;
618 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
625 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
626 struct drm_connector *connector)
628 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
629 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
630 struct drm_display_mode *t, *mode;
632 /* If the EDID preferred mode doesn't match the native mode, use it */
633 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
634 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
635 if (mode->hdisplay != native_mode->hdisplay ||
636 mode->vdisplay != native_mode->vdisplay)
637 memcpy(native_mode, mode, sizeof(*mode));
641 /* Try to get native mode details from EDID if necessary */
642 if (!native_mode->clock) {
643 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
644 if (mode->hdisplay == native_mode->hdisplay &&
645 mode->vdisplay == native_mode->vdisplay) {
646 *native_mode = *mode;
647 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
648 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
654 if (!native_mode->clock) {
655 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
656 amdgpu_encoder->rmx_type = RMX_OFF;
660 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
662 struct drm_encoder *encoder;
664 struct drm_display_mode *mode;
666 amdgpu_connector_get_edid(connector);
667 ret = amdgpu_connector_ddc_get_modes(connector);
669 encoder = amdgpu_connector_best_single_encoder(connector);
671 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
672 /* add scaled modes */
673 amdgpu_connector_add_common_modes(encoder, connector);
678 encoder = amdgpu_connector_best_single_encoder(connector);
682 /* we have no EDID modes */
683 mode = amdgpu_connector_lcd_native_mode(encoder);
686 drm_mode_probed_add(connector, mode);
687 /* add the width/height from vbios tables if available */
688 connector->display_info.width_mm = mode->width_mm;
689 connector->display_info.height_mm = mode->height_mm;
690 /* add scaled modes */
691 amdgpu_connector_add_common_modes(encoder, connector);
697 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
698 struct drm_display_mode *mode)
700 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
702 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
706 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
707 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
709 /* AVIVO hardware supports downscaling modes larger than the panel
710 * to the panel size, but I'm not sure this is desirable.
712 if ((mode->hdisplay > native_mode->hdisplay) ||
713 (mode->vdisplay > native_mode->vdisplay))
716 /* if scaling is disabled, block non-native modes */
717 if (amdgpu_encoder->rmx_type == RMX_OFF) {
718 if ((mode->hdisplay != native_mode->hdisplay) ||
719 (mode->vdisplay != native_mode->vdisplay))
727 static enum drm_connector_status
728 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
730 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
731 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
732 enum drm_connector_status ret = connector_status_disconnected;
735 if (!drm_kms_helper_is_poll_worker()) {
736 r = pm_runtime_get_sync(connector->dev->dev);
738 pm_runtime_put_autosuspend(connector->dev->dev);
739 return connector_status_disconnected;
744 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
745 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
747 /* check if panel is valid */
748 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
749 ret = connector_status_connected;
753 /* check for edid as well */
754 amdgpu_connector_get_edid(connector);
755 if (amdgpu_connector->edid)
756 ret = connector_status_connected;
757 /* check acpi lid status ??? */
759 amdgpu_connector_update_scratch_regs(connector, ret);
761 if (!drm_kms_helper_is_poll_worker()) {
762 pm_runtime_mark_last_busy(connector->dev->dev);
763 pm_runtime_put_autosuspend(connector->dev->dev);
769 static void amdgpu_connector_unregister(struct drm_connector *connector)
771 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
773 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
774 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
775 amdgpu_connector->ddc_bus->has_aux = false;
779 static void amdgpu_connector_destroy(struct drm_connector *connector)
781 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
783 amdgpu_connector_free_edid(connector);
784 kfree(amdgpu_connector->con_priv);
785 drm_connector_unregister(connector);
786 drm_connector_cleanup(connector);
790 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
791 struct drm_property *property,
794 struct drm_device *dev = connector->dev;
795 struct amdgpu_encoder *amdgpu_encoder;
796 enum amdgpu_rmx_type rmx_type;
799 if (property != dev->mode_config.scaling_mode_property)
802 if (connector->encoder)
803 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
805 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
806 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
810 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
811 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
812 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
814 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
816 if (amdgpu_encoder->rmx_type == rmx_type)
819 amdgpu_encoder->rmx_type = rmx_type;
821 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
826 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
827 .get_modes = amdgpu_connector_lvds_get_modes,
828 .mode_valid = amdgpu_connector_lvds_mode_valid,
829 .best_encoder = amdgpu_connector_best_single_encoder,
832 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
833 .dpms = drm_helper_connector_dpms,
834 .detect = amdgpu_connector_lvds_detect,
835 .fill_modes = drm_helper_probe_single_connector_modes,
836 .early_unregister = amdgpu_connector_unregister,
837 .destroy = amdgpu_connector_destroy,
838 .set_property = amdgpu_connector_set_lcd_property,
841 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
845 amdgpu_connector_get_edid(connector);
846 ret = amdgpu_connector_ddc_get_modes(connector);
847 amdgpu_get_native_mode(connector);
852 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
853 struct drm_display_mode *mode)
855 struct drm_device *dev = connector->dev;
856 struct amdgpu_device *adev = dev->dev_private;
858 /* XXX check mode bandwidth */
860 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
861 return MODE_CLOCK_HIGH;
866 static enum drm_connector_status
867 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
869 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
870 struct drm_encoder *encoder;
871 const struct drm_encoder_helper_funcs *encoder_funcs;
873 enum drm_connector_status ret = connector_status_disconnected;
876 if (!drm_kms_helper_is_poll_worker()) {
877 r = pm_runtime_get_sync(connector->dev->dev);
879 pm_runtime_put_autosuspend(connector->dev->dev);
880 return connector_status_disconnected;
884 encoder = amdgpu_connector_best_single_encoder(connector);
886 ret = connector_status_disconnected;
888 if (amdgpu_connector->ddc_bus)
889 dret = amdgpu_ddc_probe(amdgpu_connector, false);
891 amdgpu_connector->detected_by_load = false;
892 amdgpu_connector_free_edid(connector);
893 amdgpu_connector_get_edid(connector);
895 if (!amdgpu_connector->edid) {
896 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
898 ret = connector_status_connected;
900 amdgpu_connector->use_digital =
901 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
903 /* some oems have boards with separate digital and analog connectors
904 * with a shared ddc line (often vga + hdmi)
906 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
907 amdgpu_connector_free_edid(connector);
908 ret = connector_status_disconnected;
910 ret = connector_status_connected;
915 /* if we aren't forcing don't do destructive polling */
917 /* only return the previous status if we last
918 * detected a monitor via load.
920 if (amdgpu_connector->detected_by_load)
921 ret = connector->status;
925 if (amdgpu_connector->dac_load_detect && encoder) {
926 encoder_funcs = encoder->helper_private;
927 ret = encoder_funcs->detect(encoder, connector);
928 if (ret != connector_status_disconnected)
929 amdgpu_connector->detected_by_load = true;
933 amdgpu_connector_update_scratch_regs(connector, ret);
936 if (!drm_kms_helper_is_poll_worker()) {
937 pm_runtime_mark_last_busy(connector->dev->dev);
938 pm_runtime_put_autosuspend(connector->dev->dev);
944 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
945 .get_modes = amdgpu_connector_vga_get_modes,
946 .mode_valid = amdgpu_connector_vga_mode_valid,
947 .best_encoder = amdgpu_connector_best_single_encoder,
950 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
951 .dpms = drm_helper_connector_dpms,
952 .detect = amdgpu_connector_vga_detect,
953 .fill_modes = drm_helper_probe_single_connector_modes,
954 .early_unregister = amdgpu_connector_unregister,
955 .destroy = amdgpu_connector_destroy,
956 .set_property = amdgpu_connector_set_property,
960 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
962 struct drm_device *dev = connector->dev;
963 struct amdgpu_device *adev = dev->dev_private;
964 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
965 enum drm_connector_status status;
967 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
968 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
969 status = connector_status_connected;
971 status = connector_status_disconnected;
972 if (connector->status == status)
981 * Do a DDC probe, if DDC probe passes, get the full EDID so
982 * we can do analog/digital monitor detection at this point.
983 * If the monitor is an analog monitor or we got no DDC,
984 * we need to find the DAC encoder object for this connector.
985 * If we got no DDC, we do load detection on the DAC encoder object.
986 * If we got analog DDC or load detection passes on the DAC encoder
987 * we have to check if this analog encoder is shared with anyone else (TV)
988 * if its shared we have to set the other connector to disconnected.
990 static enum drm_connector_status
991 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
993 struct drm_device *dev = connector->dev;
994 struct amdgpu_device *adev = dev->dev_private;
995 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
996 struct drm_encoder *encoder = NULL;
997 const struct drm_encoder_helper_funcs *encoder_funcs;
999 enum drm_connector_status ret = connector_status_disconnected;
1000 bool dret = false, broken_edid = false;
1002 if (!drm_kms_helper_is_poll_worker()) {
1003 r = pm_runtime_get_sync(connector->dev->dev);
1005 pm_runtime_put_autosuspend(connector->dev->dev);
1006 return connector_status_disconnected;
1010 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1011 ret = connector->status;
1015 if (amdgpu_connector->ddc_bus)
1016 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1018 amdgpu_connector->detected_by_load = false;
1019 amdgpu_connector_free_edid(connector);
1020 amdgpu_connector_get_edid(connector);
1022 if (!amdgpu_connector->edid) {
1023 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1025 ret = connector_status_connected;
1026 broken_edid = true; /* defer use_digital to later */
1028 amdgpu_connector->use_digital =
1029 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1031 /* some oems have boards with separate digital and analog connectors
1032 * with a shared ddc line (often vga + hdmi)
1034 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1035 amdgpu_connector_free_edid(connector);
1036 ret = connector_status_disconnected;
1038 ret = connector_status_connected;
1041 /* This gets complicated. We have boards with VGA + HDMI with a
1042 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1043 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1044 * you don't really know what's connected to which port as both are digital.
1046 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1047 struct drm_connector *list_connector;
1048 struct amdgpu_connector *list_amdgpu_connector;
1049 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1050 if (connector == list_connector)
1052 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1053 if (list_amdgpu_connector->shared_ddc &&
1054 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1055 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1056 /* cases where both connectors are digital */
1057 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1058 /* hpd is our only option in this case */
1059 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1060 amdgpu_connector_free_edid(connector);
1061 ret = connector_status_disconnected;
1070 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1073 /* DVI-D and HDMI-A are digital only */
1074 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1075 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1078 /* if we aren't forcing don't do destructive polling */
1080 /* only return the previous status if we last
1081 * detected a monitor via load.
1083 if (amdgpu_connector->detected_by_load)
1084 ret = connector->status;
1088 /* find analog encoder */
1089 if (amdgpu_connector->dac_load_detect) {
1090 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1091 if (connector->encoder_ids[i] == 0)
1094 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1098 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1099 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1102 encoder_funcs = encoder->helper_private;
1103 if (encoder_funcs->detect) {
1105 if (ret != connector_status_connected) {
1106 /* deal with analog monitors without DDC */
1107 ret = encoder_funcs->detect(encoder, connector);
1108 if (ret == connector_status_connected) {
1109 amdgpu_connector->use_digital = false;
1111 if (ret != connector_status_disconnected)
1112 amdgpu_connector->detected_by_load = true;
1115 enum drm_connector_status lret;
1116 /* assume digital unless load detected otherwise */
1117 amdgpu_connector->use_digital = true;
1118 lret = encoder_funcs->detect(encoder, connector);
1119 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1120 if (lret == connector_status_connected)
1121 amdgpu_connector->use_digital = false;
1129 /* updated in get modes as well since we need to know if it's analog or digital */
1130 amdgpu_connector_update_scratch_regs(connector, ret);
1133 if (!drm_kms_helper_is_poll_worker()) {
1134 pm_runtime_mark_last_busy(connector->dev->dev);
1135 pm_runtime_put_autosuspend(connector->dev->dev);
1141 /* okay need to be smart in here about which encoder to pick */
1142 static struct drm_encoder *
1143 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1145 int enc_id = connector->encoder_ids[0];
1146 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1147 struct drm_encoder *encoder;
1149 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1150 if (connector->encoder_ids[i] == 0)
1153 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1157 if (amdgpu_connector->use_digital == true) {
1158 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1161 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1162 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1167 /* see if we have a default encoder TODO */
1169 /* then check use digitial */
1170 /* pick the first one */
1172 return drm_encoder_find(connector->dev, enc_id);
1176 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1178 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1179 if (connector->force == DRM_FORCE_ON)
1180 amdgpu_connector->use_digital = false;
1181 if (connector->force == DRM_FORCE_ON_DIGITAL)
1182 amdgpu_connector->use_digital = true;
1185 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1186 struct drm_display_mode *mode)
1188 struct drm_device *dev = connector->dev;
1189 struct amdgpu_device *adev = dev->dev_private;
1190 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1192 /* XXX check mode bandwidth */
1194 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1195 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1196 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1197 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1199 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1200 /* HDMI 1.3+ supports max clock of 340 Mhz */
1201 if (mode->clock > 340000)
1202 return MODE_CLOCK_HIGH;
1206 return MODE_CLOCK_HIGH;
1210 /* check against the max pixel clock */
1211 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1212 return MODE_CLOCK_HIGH;
1217 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1218 .get_modes = amdgpu_connector_vga_get_modes,
1219 .mode_valid = amdgpu_connector_dvi_mode_valid,
1220 .best_encoder = amdgpu_connector_dvi_encoder,
1223 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1224 .dpms = drm_helper_connector_dpms,
1225 .detect = amdgpu_connector_dvi_detect,
1226 .fill_modes = drm_helper_probe_single_connector_modes,
1227 .set_property = amdgpu_connector_set_property,
1228 .early_unregister = amdgpu_connector_unregister,
1229 .destroy = amdgpu_connector_destroy,
1230 .force = amdgpu_connector_dvi_force,
1233 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1235 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1236 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1237 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1240 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1241 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1242 struct drm_display_mode *mode;
1244 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1245 if (!amdgpu_dig_connector->edp_on)
1246 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1247 ATOM_TRANSMITTER_ACTION_POWER_ON);
1248 amdgpu_connector_get_edid(connector);
1249 ret = amdgpu_connector_ddc_get_modes(connector);
1250 if (!amdgpu_dig_connector->edp_on)
1251 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1252 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1254 /* need to setup ddc on the bridge */
1255 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1256 ENCODER_OBJECT_ID_NONE) {
1258 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1260 amdgpu_connector_get_edid(connector);
1261 ret = amdgpu_connector_ddc_get_modes(connector);
1266 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1267 /* add scaled modes */
1268 amdgpu_connector_add_common_modes(encoder, connector);
1276 /* we have no EDID modes */
1277 mode = amdgpu_connector_lcd_native_mode(encoder);
1280 drm_mode_probed_add(connector, mode);
1281 /* add the width/height from vbios tables if available */
1282 connector->display_info.width_mm = mode->width_mm;
1283 connector->display_info.height_mm = mode->height_mm;
1284 /* add scaled modes */
1285 amdgpu_connector_add_common_modes(encoder, connector);
1288 /* need to setup ddc on the bridge */
1289 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1290 ENCODER_OBJECT_ID_NONE) {
1292 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1294 amdgpu_connector_get_edid(connector);
1295 ret = amdgpu_connector_ddc_get_modes(connector);
1297 amdgpu_get_native_mode(connector);
1303 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1305 struct drm_encoder *encoder;
1306 struct amdgpu_encoder *amdgpu_encoder;
1309 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1310 if (connector->encoder_ids[i] == 0)
1313 encoder = drm_encoder_find(connector->dev,
1314 connector->encoder_ids[i]);
1318 amdgpu_encoder = to_amdgpu_encoder(encoder);
1320 switch (amdgpu_encoder->encoder_id) {
1321 case ENCODER_OBJECT_ID_TRAVIS:
1322 case ENCODER_OBJECT_ID_NUTMEG:
1323 return amdgpu_encoder->encoder_id;
1329 return ENCODER_OBJECT_ID_NONE;
1332 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1334 struct drm_encoder *encoder;
1335 struct amdgpu_encoder *amdgpu_encoder;
1339 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1340 if (connector->encoder_ids[i] == 0)
1342 encoder = drm_encoder_find(connector->dev,
1343 connector->encoder_ids[i]);
1347 amdgpu_encoder = to_amdgpu_encoder(encoder);
1348 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1355 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1357 struct drm_device *dev = connector->dev;
1358 struct amdgpu_device *adev = dev->dev_private;
1360 if ((adev->clock.default_dispclk >= 53900) &&
1361 amdgpu_connector_encoder_is_hbr2(connector)) {
1368 static enum drm_connector_status
1369 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1371 struct drm_device *dev = connector->dev;
1372 struct amdgpu_device *adev = dev->dev_private;
1373 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1374 enum drm_connector_status ret = connector_status_disconnected;
1375 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1376 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1379 if (!drm_kms_helper_is_poll_worker()) {
1380 r = pm_runtime_get_sync(connector->dev->dev);
1382 pm_runtime_put_autosuspend(connector->dev->dev);
1383 return connector_status_disconnected;
1387 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1388 ret = connector->status;
1392 amdgpu_connector_free_edid(connector);
1394 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1395 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1398 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1400 /* check if panel is valid */
1401 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1402 ret = connector_status_connected;
1404 /* eDP is always DP */
1405 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1406 if (!amdgpu_dig_connector->edp_on)
1407 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1408 ATOM_TRANSMITTER_ACTION_POWER_ON);
1409 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1410 ret = connector_status_connected;
1411 if (!amdgpu_dig_connector->edp_on)
1412 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1413 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1414 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1415 ENCODER_OBJECT_ID_NONE) {
1416 /* DP bridges are always DP */
1417 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1418 /* get the DPCD from the bridge */
1419 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1422 /* setup ddc on the bridge */
1423 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1424 /* bridge chips are always aux */
1425 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1426 ret = connector_status_connected;
1427 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1428 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1429 ret = encoder_funcs->detect(encoder, connector);
1433 amdgpu_dig_connector->dp_sink_type =
1434 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1435 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1436 ret = connector_status_connected;
1437 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1438 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1440 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1441 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1442 ret = connector_status_connected;
1444 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1445 if (amdgpu_ddc_probe(amdgpu_connector, false))
1446 ret = connector_status_connected;
1451 amdgpu_connector_update_scratch_regs(connector, ret);
1453 if (!drm_kms_helper_is_poll_worker()) {
1454 pm_runtime_mark_last_busy(connector->dev->dev);
1455 pm_runtime_put_autosuspend(connector->dev->dev);
1461 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1462 struct drm_display_mode *mode)
1464 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1465 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1467 /* XXX check mode bandwidth */
1469 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1470 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1471 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1473 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1477 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1478 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1480 /* AVIVO hardware supports downscaling modes larger than the panel
1481 * to the panel size, but I'm not sure this is desirable.
1483 if ((mode->hdisplay > native_mode->hdisplay) ||
1484 (mode->vdisplay > native_mode->vdisplay))
1487 /* if scaling is disabled, block non-native modes */
1488 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1489 if ((mode->hdisplay != native_mode->hdisplay) ||
1490 (mode->vdisplay != native_mode->vdisplay))
1496 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1497 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1498 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1500 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1501 /* HDMI 1.3+ supports max clock of 340 Mhz */
1502 if (mode->clock > 340000)
1503 return MODE_CLOCK_HIGH;
1505 if (mode->clock > 165000)
1506 return MODE_CLOCK_HIGH;
1514 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1515 .get_modes = amdgpu_connector_dp_get_modes,
1516 .mode_valid = amdgpu_connector_dp_mode_valid,
1517 .best_encoder = amdgpu_connector_dvi_encoder,
1520 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1521 .dpms = drm_helper_connector_dpms,
1522 .detect = amdgpu_connector_dp_detect,
1523 .fill_modes = drm_helper_probe_single_connector_modes,
1524 .set_property = amdgpu_connector_set_property,
1525 .early_unregister = amdgpu_connector_unregister,
1526 .destroy = amdgpu_connector_destroy,
1527 .force = amdgpu_connector_dvi_force,
1530 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1531 .dpms = drm_helper_connector_dpms,
1532 .detect = amdgpu_connector_dp_detect,
1533 .fill_modes = drm_helper_probe_single_connector_modes,
1534 .set_property = amdgpu_connector_set_lcd_property,
1535 .early_unregister = amdgpu_connector_unregister,
1536 .destroy = amdgpu_connector_destroy,
1537 .force = amdgpu_connector_dvi_force,
1541 amdgpu_connector_add(struct amdgpu_device *adev,
1542 uint32_t connector_id,
1543 uint32_t supported_device,
1545 struct amdgpu_i2c_bus_rec *i2c_bus,
1546 uint16_t connector_object_id,
1547 struct amdgpu_hpd *hpd,
1548 struct amdgpu_router *router)
1550 struct drm_device *dev = adev->ddev;
1551 struct drm_connector *connector;
1552 struct amdgpu_connector *amdgpu_connector;
1553 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1554 struct drm_encoder *encoder;
1555 struct amdgpu_encoder *amdgpu_encoder;
1556 uint32_t subpixel_order = SubPixelNone;
1557 bool shared_ddc = false;
1558 bool is_dp_bridge = false;
1559 bool has_aux = false;
1561 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1564 /* see if we already added it */
1565 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1566 amdgpu_connector = to_amdgpu_connector(connector);
1567 if (amdgpu_connector->connector_id == connector_id) {
1568 amdgpu_connector->devices |= supported_device;
1571 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1572 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1573 amdgpu_connector->shared_ddc = true;
1576 if (amdgpu_connector->router_bus && router->ddc_valid &&
1577 (amdgpu_connector->router.router_id == router->router_id)) {
1578 amdgpu_connector->shared_ddc = false;
1584 /* check if it's a dp bridge */
1585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1586 amdgpu_encoder = to_amdgpu_encoder(encoder);
1587 if (amdgpu_encoder->devices & supported_device) {
1588 switch (amdgpu_encoder->encoder_id) {
1589 case ENCODER_OBJECT_ID_TRAVIS:
1590 case ENCODER_OBJECT_ID_NUTMEG:
1591 is_dp_bridge = true;
1599 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1600 if (!amdgpu_connector)
1603 connector = &amdgpu_connector->base;
1605 amdgpu_connector->connector_id = connector_id;
1606 amdgpu_connector->devices = supported_device;
1607 amdgpu_connector->shared_ddc = shared_ddc;
1608 amdgpu_connector->connector_object_id = connector_object_id;
1609 amdgpu_connector->hpd = *hpd;
1611 amdgpu_connector->router = *router;
1612 if (router->ddc_valid || router->cd_valid) {
1613 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1614 if (!amdgpu_connector->router_bus)
1615 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1619 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1620 if (!amdgpu_dig_connector)
1622 amdgpu_connector->con_priv = amdgpu_dig_connector;
1623 if (i2c_bus->valid) {
1624 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1625 if (amdgpu_connector->ddc_bus)
1628 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1630 switch (connector_type) {
1631 case DRM_MODE_CONNECTOR_VGA:
1632 case DRM_MODE_CONNECTOR_DVIA:
1634 drm_connector_init(dev, &amdgpu_connector->base,
1635 &amdgpu_connector_dp_funcs, connector_type);
1636 drm_connector_helper_add(&amdgpu_connector->base,
1637 &amdgpu_connector_dp_helper_funcs);
1638 connector->interlace_allowed = true;
1639 connector->doublescan_allowed = true;
1640 amdgpu_connector->dac_load_detect = true;
1641 drm_object_attach_property(&amdgpu_connector->base.base,
1642 adev->mode_info.load_detect_property,
1644 drm_object_attach_property(&amdgpu_connector->base.base,
1645 dev->mode_config.scaling_mode_property,
1646 DRM_MODE_SCALE_NONE);
1648 case DRM_MODE_CONNECTOR_DVII:
1649 case DRM_MODE_CONNECTOR_DVID:
1650 case DRM_MODE_CONNECTOR_HDMIA:
1651 case DRM_MODE_CONNECTOR_HDMIB:
1652 case DRM_MODE_CONNECTOR_DisplayPort:
1653 drm_connector_init(dev, &amdgpu_connector->base,
1654 &amdgpu_connector_dp_funcs, connector_type);
1655 drm_connector_helper_add(&amdgpu_connector->base,
1656 &amdgpu_connector_dp_helper_funcs);
1657 drm_object_attach_property(&amdgpu_connector->base.base,
1658 adev->mode_info.underscan_property,
1660 drm_object_attach_property(&amdgpu_connector->base.base,
1661 adev->mode_info.underscan_hborder_property,
1663 drm_object_attach_property(&amdgpu_connector->base.base,
1664 adev->mode_info.underscan_vborder_property,
1667 drm_object_attach_property(&amdgpu_connector->base.base,
1668 dev->mode_config.scaling_mode_property,
1669 DRM_MODE_SCALE_NONE);
1671 drm_object_attach_property(&amdgpu_connector->base.base,
1672 adev->mode_info.dither_property,
1673 AMDGPU_FMT_DITHER_DISABLE);
1675 if (amdgpu_audio != 0)
1676 drm_object_attach_property(&amdgpu_connector->base.base,
1677 adev->mode_info.audio_property,
1680 subpixel_order = SubPixelHorizontalRGB;
1681 connector->interlace_allowed = true;
1682 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1683 connector->doublescan_allowed = true;
1685 connector->doublescan_allowed = false;
1686 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1687 amdgpu_connector->dac_load_detect = true;
1688 drm_object_attach_property(&amdgpu_connector->base.base,
1689 adev->mode_info.load_detect_property,
1693 case DRM_MODE_CONNECTOR_LVDS:
1694 case DRM_MODE_CONNECTOR_eDP:
1695 drm_connector_init(dev, &amdgpu_connector->base,
1696 &amdgpu_connector_edp_funcs, connector_type);
1697 drm_connector_helper_add(&amdgpu_connector->base,
1698 &amdgpu_connector_dp_helper_funcs);
1699 drm_object_attach_property(&amdgpu_connector->base.base,
1700 dev->mode_config.scaling_mode_property,
1701 DRM_MODE_SCALE_FULLSCREEN);
1702 subpixel_order = SubPixelHorizontalRGB;
1703 connector->interlace_allowed = false;
1704 connector->doublescan_allowed = false;
1708 switch (connector_type) {
1709 case DRM_MODE_CONNECTOR_VGA:
1710 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1711 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1712 if (i2c_bus->valid) {
1713 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1714 if (!amdgpu_connector->ddc_bus)
1715 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1717 amdgpu_connector->dac_load_detect = true;
1718 drm_object_attach_property(&amdgpu_connector->base.base,
1719 adev->mode_info.load_detect_property,
1721 drm_object_attach_property(&amdgpu_connector->base.base,
1722 dev->mode_config.scaling_mode_property,
1723 DRM_MODE_SCALE_NONE);
1724 /* no HPD on analog connectors */
1725 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1726 connector->interlace_allowed = true;
1727 connector->doublescan_allowed = true;
1729 case DRM_MODE_CONNECTOR_DVIA:
1730 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1731 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1732 if (i2c_bus->valid) {
1733 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1734 if (!amdgpu_connector->ddc_bus)
1735 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1737 amdgpu_connector->dac_load_detect = true;
1738 drm_object_attach_property(&amdgpu_connector->base.base,
1739 adev->mode_info.load_detect_property,
1741 drm_object_attach_property(&amdgpu_connector->base.base,
1742 dev->mode_config.scaling_mode_property,
1743 DRM_MODE_SCALE_NONE);
1744 /* no HPD on analog connectors */
1745 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1746 connector->interlace_allowed = true;
1747 connector->doublescan_allowed = true;
1749 case DRM_MODE_CONNECTOR_DVII:
1750 case DRM_MODE_CONNECTOR_DVID:
1751 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1752 if (!amdgpu_dig_connector)
1754 amdgpu_connector->con_priv = amdgpu_dig_connector;
1755 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1756 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1757 if (i2c_bus->valid) {
1758 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1759 if (!amdgpu_connector->ddc_bus)
1760 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1762 subpixel_order = SubPixelHorizontalRGB;
1763 drm_object_attach_property(&amdgpu_connector->base.base,
1764 adev->mode_info.coherent_mode_property,
1766 drm_object_attach_property(&amdgpu_connector->base.base,
1767 adev->mode_info.underscan_property,
1769 drm_object_attach_property(&amdgpu_connector->base.base,
1770 adev->mode_info.underscan_hborder_property,
1772 drm_object_attach_property(&amdgpu_connector->base.base,
1773 adev->mode_info.underscan_vborder_property,
1775 drm_object_attach_property(&amdgpu_connector->base.base,
1776 dev->mode_config.scaling_mode_property,
1777 DRM_MODE_SCALE_NONE);
1779 if (amdgpu_audio != 0) {
1780 drm_object_attach_property(&amdgpu_connector->base.base,
1781 adev->mode_info.audio_property,
1784 drm_object_attach_property(&amdgpu_connector->base.base,
1785 adev->mode_info.dither_property,
1786 AMDGPU_FMT_DITHER_DISABLE);
1787 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1788 amdgpu_connector->dac_load_detect = true;
1789 drm_object_attach_property(&amdgpu_connector->base.base,
1790 adev->mode_info.load_detect_property,
1793 connector->interlace_allowed = true;
1794 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1795 connector->doublescan_allowed = true;
1797 connector->doublescan_allowed = false;
1799 case DRM_MODE_CONNECTOR_HDMIA:
1800 case DRM_MODE_CONNECTOR_HDMIB:
1801 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1802 if (!amdgpu_dig_connector)
1804 amdgpu_connector->con_priv = amdgpu_dig_connector;
1805 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1806 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1807 if (i2c_bus->valid) {
1808 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1809 if (!amdgpu_connector->ddc_bus)
1810 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1812 drm_object_attach_property(&amdgpu_connector->base.base,
1813 adev->mode_info.coherent_mode_property,
1815 drm_object_attach_property(&amdgpu_connector->base.base,
1816 adev->mode_info.underscan_property,
1818 drm_object_attach_property(&amdgpu_connector->base.base,
1819 adev->mode_info.underscan_hborder_property,
1821 drm_object_attach_property(&amdgpu_connector->base.base,
1822 adev->mode_info.underscan_vborder_property,
1824 drm_object_attach_property(&amdgpu_connector->base.base,
1825 dev->mode_config.scaling_mode_property,
1826 DRM_MODE_SCALE_NONE);
1827 if (amdgpu_audio != 0) {
1828 drm_object_attach_property(&amdgpu_connector->base.base,
1829 adev->mode_info.audio_property,
1832 drm_object_attach_property(&amdgpu_connector->base.base,
1833 adev->mode_info.dither_property,
1834 AMDGPU_FMT_DITHER_DISABLE);
1835 subpixel_order = SubPixelHorizontalRGB;
1836 connector->interlace_allowed = true;
1837 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1838 connector->doublescan_allowed = true;
1840 connector->doublescan_allowed = false;
1842 case DRM_MODE_CONNECTOR_DisplayPort:
1843 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1844 if (!amdgpu_dig_connector)
1846 amdgpu_connector->con_priv = amdgpu_dig_connector;
1847 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1848 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1849 if (i2c_bus->valid) {
1850 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1851 if (amdgpu_connector->ddc_bus)
1854 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1856 subpixel_order = SubPixelHorizontalRGB;
1857 drm_object_attach_property(&amdgpu_connector->base.base,
1858 adev->mode_info.coherent_mode_property,
1860 drm_object_attach_property(&amdgpu_connector->base.base,
1861 adev->mode_info.underscan_property,
1863 drm_object_attach_property(&amdgpu_connector->base.base,
1864 adev->mode_info.underscan_hborder_property,
1866 drm_object_attach_property(&amdgpu_connector->base.base,
1867 adev->mode_info.underscan_vborder_property,
1869 drm_object_attach_property(&amdgpu_connector->base.base,
1870 dev->mode_config.scaling_mode_property,
1871 DRM_MODE_SCALE_NONE);
1872 if (amdgpu_audio != 0) {
1873 drm_object_attach_property(&amdgpu_connector->base.base,
1874 adev->mode_info.audio_property,
1877 drm_object_attach_property(&amdgpu_connector->base.base,
1878 adev->mode_info.dither_property,
1879 AMDGPU_FMT_DITHER_DISABLE);
1880 connector->interlace_allowed = true;
1881 /* in theory with a DP to VGA converter... */
1882 connector->doublescan_allowed = false;
1884 case DRM_MODE_CONNECTOR_eDP:
1885 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1886 if (!amdgpu_dig_connector)
1888 amdgpu_connector->con_priv = amdgpu_dig_connector;
1889 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1890 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1891 if (i2c_bus->valid) {
1892 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1893 if (amdgpu_connector->ddc_bus)
1896 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1898 drm_object_attach_property(&amdgpu_connector->base.base,
1899 dev->mode_config.scaling_mode_property,
1900 DRM_MODE_SCALE_FULLSCREEN);
1901 subpixel_order = SubPixelHorizontalRGB;
1902 connector->interlace_allowed = false;
1903 connector->doublescan_allowed = false;
1905 case DRM_MODE_CONNECTOR_LVDS:
1906 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1907 if (!amdgpu_dig_connector)
1909 amdgpu_connector->con_priv = amdgpu_dig_connector;
1910 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1911 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1912 if (i2c_bus->valid) {
1913 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1914 if (!amdgpu_connector->ddc_bus)
1915 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1917 drm_object_attach_property(&amdgpu_connector->base.base,
1918 dev->mode_config.scaling_mode_property,
1919 DRM_MODE_SCALE_FULLSCREEN);
1920 subpixel_order = SubPixelHorizontalRGB;
1921 connector->interlace_allowed = false;
1922 connector->doublescan_allowed = false;
1927 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1928 if (i2c_bus->valid) {
1929 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1930 DRM_CONNECTOR_POLL_DISCONNECT;
1933 connector->polled = DRM_CONNECTOR_POLL_HPD;
1935 connector->display_info.subpixel_order = subpixel_order;
1936 drm_connector_register(connector);
1939 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1944 drm_connector_cleanup(connector);