drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_fb_helper.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "atom.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_i2c.h"
  37
  38 #include <linux/pm_runtime.h>
  39
  40 void amdgpu_connector_hotplug(struct drm_connector *connector)
  41 {
  42         struct drm_device *dev = connector->dev;
  43         struct amdgpu_device *adev = dev->dev_private;
  44         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  45
  46         /* bail if the connector does not have hpd pin, e.g.,
  47          * VGA, TV, etc.
  48          */
  49         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  50                 return;
  51
  52         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  53
  54         /* if the connector is already off, don't turn it back on */
  55         if (connector->dpms != DRM_MODE_DPMS_ON)
  56                 return;
  57
  58         /* just deal with DP (not eDP) here. */
  59         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  60                 struct amdgpu_connector_atom_dig *dig_connector =
  61                         amdgpu_connector->con_priv;
  62
  63                 /* if existing sink type was not DP no need to retrain */
  64                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  65                         return;
  66
  67                 /* first get sink type as it may be reset after (un)plug */
  68                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  69                 /* don't do anything if sink is not display port, i.e.,
  70                  * passive dp->(dvi|hdmi) adaptor
  71                  */
  72                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  73                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  74                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  75                         /* Don't start link training before we have the DPCD */
  76                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  77                                 return;
  78
  79                         /* Turn the connector off and back on immediately, which
  80                          * will trigger link training
  81                          */
  82                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  83                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  84                 }
  85         }
  86 }
  87
  88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  89 {
  90         struct drm_crtc *crtc = encoder->crtc;
  91
  92         if (crtc && crtc->enabled) {
  93                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  94                                          crtc->x, crtc->y, crtc->primary->fb);
  95         }
  96 }
  97
  98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
  99 {
 100         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 101         struct amdgpu_connector_atom_dig *dig_connector;
 102         int bpc = 8;
 103         unsigned mode_clock, max_tmds_clock;
 104
 105         switch (connector->connector_type) {
 106         case DRM_MODE_CONNECTOR_DVII:
 107         case DRM_MODE_CONNECTOR_HDMIB:
 108                 if (amdgpu_connector->use_digital) {
 109                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 110                                 if (connector->display_info.bpc)
 111                                         bpc = connector->display_info.bpc;
 112                         }
 113                 }
 114                 break;
 115         case DRM_MODE_CONNECTOR_DVID:
 116         case DRM_MODE_CONNECTOR_HDMIA:
 117                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 118                         if (connector->display_info.bpc)
 119                                 bpc = connector->display_info.bpc;
 120                 }
 121                 break;
 122         case DRM_MODE_CONNECTOR_DisplayPort:
 123                 dig_connector = amdgpu_connector->con_priv;
 124                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 125                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 126                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 127                         if (connector->display_info.bpc)
 128                                 bpc = connector->display_info.bpc;
 129                 }
 130                 break;
 131         case DRM_MODE_CONNECTOR_eDP:
 132         case DRM_MODE_CONNECTOR_LVDS:
 133                 if (connector->display_info.bpc)
 134                         bpc = connector->display_info.bpc;
 135                 else {
 136                         const struct drm_connector_helper_funcs *connector_funcs =
 137                                 connector->helper_private;
 138                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 139                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 140                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 141
 142                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 143                                 bpc = 6;
 144                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 145                                 bpc = 8;
 146                 }
 147                 break;
 148         }
 149
 150         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 151                 /*
 152                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 153                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 154                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 155                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 156                  */
 157                 if (bpc > 12) {
 158                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 159                                   connector->name, bpc);
 160                         bpc = 12;
 161                 }
 162
 163                 /* Any defined maximum tmds clock limit we must not exceed? */
 164                 if (connector->display_info.max_tmds_clock > 0) {
 165                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 166                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 167
 168                         /* Maximum allowable input clock in kHz */
 169                         max_tmds_clock = connector->display_info.max_tmds_clock;
 170
 171                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 172                                   connector->name, mode_clock, max_tmds_clock);
 173
 174                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 175                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 176                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 177                                     (mode_clock * 5/4 <= max_tmds_clock))
 178                                         bpc = 10;
 179                                 else
 180                                         bpc = 8;
 181
 182                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 183                                           connector->name, bpc);
 184                         }
 185
 186                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 187                                 bpc = 8;
 188                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 189                                           connector->name, bpc);
 190                         }
 191                 } else if (bpc > 8) {
 192                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 193                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 194                                   connector->name);
 195                         bpc = 8;
 196                 }
 197         }
 198
 199         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 200                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 201                           connector->name);
 202                 bpc = 8;
 203         }
 204
 205         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 206                   connector->name, connector->display_info.bpc, bpc);
 207
 208         return bpc;
 209 }
 210
 211 static void
 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 213                                       enum drm_connector_status status)
 214 {
 215         struct drm_encoder *best_encoder;
 216         struct drm_encoder *encoder;
 217         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 218         bool connected;
 219         int i;
 220
 221         best_encoder = connector_funcs->best_encoder(connector);
 222
 223         drm_connector_for_each_possible_encoder(connector, encoder, i) {
 224                 if ((encoder == best_encoder) && (status == connector_status_connected))
 225                         connected = true;
 226                 else
 227                         connected = false;
 228
 229                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 230         }
 231 }
 232
 233 static struct drm_encoder *
 234 amdgpu_connector_find_encoder(struct drm_connector *connector,
 235                                int encoder_type)
 236 {
 237         struct drm_encoder *encoder;
 238         int i;
 239
 240         drm_connector_for_each_possible_encoder(connector, encoder, i) {
 241                 if (encoder->encoder_type == encoder_type)
 242                         return encoder;
 243         }
 244
 245         return NULL;
 246 }
 247
 248 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 249 {
 250         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 251         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 252
 253         if (amdgpu_connector->edid) {
 254                 return amdgpu_connector->edid;
 255         } else if (edid_blob) {
 256                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 257                 if (edid)
 258                         amdgpu_connector->edid = edid;
 259         }
 260         return amdgpu_connector->edid;
 261 }
 262
 263 static struct edid *
 264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 265 {
 266         struct edid *edid;
 267
 268         if (adev->mode_info.bios_hardcoded_edid) {
 269                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 270                 if (edid) {
 271                         memcpy((unsigned char *)edid,
 272                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 273                                adev->mode_info.bios_hardcoded_edid_size);
 274                         return edid;
 275                 }
 276         }
 277         return NULL;
 278 }
 279
 280 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 281 {
 282         struct drm_device *dev = connector->dev;
 283         struct amdgpu_device *adev = dev->dev_private;
 284         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 285
 286         if (amdgpu_connector->edid)
 287                 return;
 288
 289         /* on hw with routers, select right port */
 290         if (amdgpu_connector->router.ddc_valid)
 291                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 292
 293         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 294              ENCODER_OBJECT_ID_NONE) &&
 295             amdgpu_connector->ddc_bus->has_aux) {
 296                 amdgpu_connector->edid = drm_get_edid(connector,
 297                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 298         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 299                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 300                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 301
 302                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 303                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 304                     amdgpu_connector->ddc_bus->has_aux)
 305                         amdgpu_connector->edid = drm_get_edid(connector,
 306                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 307                 else if (amdgpu_connector->ddc_bus)
 308                         amdgpu_connector->edid = drm_get_edid(connector,
 309                                                               &amdgpu_connector->ddc_bus->adapter);
 310         } else if (amdgpu_connector->ddc_bus) {
 311                 amdgpu_connector->edid = drm_get_edid(connector,
 312                                                       &amdgpu_connector->ddc_bus->adapter);
 313         }
 314
 315         if (!amdgpu_connector->edid) {
 316                 /* some laptops provide a hardcoded edid in rom for LCDs */
 317                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 318                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 319                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 320         }
 321 }
 322
 323 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 324 {
 325         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 326
 327         kfree(amdgpu_connector->edid);
 328         amdgpu_connector->edid = NULL;
 329 }
 330
 331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 332 {
 333         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 334         int ret;
 335
 336         if (amdgpu_connector->edid) {
 337                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 338                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 339                 return ret;
 340         }
 341         drm_connector_update_edid_property(connector, NULL);
 342         return 0;
 343 }
 344
 345 static struct drm_encoder *
 346 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 347 {
 348         struct drm_encoder *encoder;
 349         int i;
 350
 351         /* pick the first one */
 352         drm_connector_for_each_possible_encoder(connector, encoder, i)
 353                 return encoder;
 354
 355         return NULL;
 356 }
 357
 358 static void amdgpu_get_native_mode(struct drm_connector *connector)
 359 {
 360         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 361         struct amdgpu_encoder *amdgpu_encoder;
 362
 363         if (encoder == NULL)
 364                 return;
 365
 366         amdgpu_encoder = to_amdgpu_encoder(encoder);
 367
 368         if (!list_empty(&connector->probed_modes)) {
 369                 struct drm_display_mode *preferred_mode =
 370                         list_first_entry(&connector->probed_modes,
 371                                          struct drm_display_mode, head);
 372
 373                 amdgpu_encoder->native_mode = *preferred_mode;
 374         } else {
 375                 amdgpu_encoder->native_mode.clock = 0;
 376         }
 377 }
 378
 379 static struct drm_display_mode *
 380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 381 {
 382         struct drm_device *dev = encoder->dev;
 383         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 384         struct drm_display_mode *mode = NULL;
 385         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 386
 387         if (native_mode->hdisplay != 0 &&
 388             native_mode->vdisplay != 0 &&
 389             native_mode->clock != 0) {
 390                 mode = drm_mode_duplicate(dev, native_mode);
 391                 if (!mode)
 392                         return NULL;
 393
 394                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 395                 drm_mode_set_name(mode);
 396
 397                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 398         } else if (native_mode->hdisplay != 0 &&
 399                    native_mode->vdisplay != 0) {
 400                 /* mac laptops without an edid */
 401                 /* Note that this is not necessarily the exact panel mode,
 402                  * but an approximation based on the cvt formula.  For these
 403                  * systems we should ideally read the mode info out of the
 404                  * registers or add a mode table, but this works and is much
 405                  * simpler.
 406                  */
 407                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 408                 if (!mode)
 409                         return NULL;
 410
 411                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 412                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 413         }
 414         return mode;
 415 }
 416
 417 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 418                                                struct drm_connector *connector)
 419 {
 420         struct drm_device *dev = encoder->dev;
 421         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 422         struct drm_display_mode *mode = NULL;
 423         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 424         int i;
 425         static const struct mode_size {
 426                 int w;
 427                 int h;
 428         } common_modes[17] = {
 429                 { 640,  480},
 430                 { 720,  480},
 431                 { 800,  600},
 432                 { 848,  480},
 433                 {1024,  768},
 434                 {1152,  768},
 435                 {1280,  720},
 436                 {1280,  800},
 437                 {1280,  854},
 438                 {1280,  960},
 439                 {1280, 1024},
 440                 {1440,  900},
 441                 {1400, 1050},
 442                 {1680, 1050},
 443                 {1600, 1200},
 444                 {1920, 1080},
 445                 {1920, 1200}
 446         };
 447
 448         for (i = 0; i < 17; i++) {
 449                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 450                         if (common_modes[i].w > 1024 ||
 451                             common_modes[i].h > 768)
 452                                 continue;
 453                 }
 454                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 455                         if (common_modes[i].w > native_mode->hdisplay ||
 456                             common_modes[i].h > native_mode->vdisplay ||
 457                             (common_modes[i].w == native_mode->hdisplay &&
 458                              common_modes[i].h == native_mode->vdisplay))
 459                                 continue;
 460                 }
 461                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 462                         continue;
 463
 464                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 465                 drm_mode_probed_add(connector, mode);
 466         }
 467 }
 468
 469 static int amdgpu_connector_set_property(struct drm_connector *connector,
 470                                           struct drm_property *property,
 471                                           uint64_t val)
 472 {
 473         struct drm_device *dev = connector->dev;
 474         struct amdgpu_device *adev = dev->dev_private;
 475         struct drm_encoder *encoder;
 476         struct amdgpu_encoder *amdgpu_encoder;
 477
 478         if (property == adev->mode_info.coherent_mode_property) {
 479                 struct amdgpu_encoder_atom_dig *dig;
 480                 bool new_coherent_mode;
 481
 482                 /* need to find digital encoder on connector */
 483                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 484                 if (!encoder)
 485                         return 0;
 486
 487                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 488
 489                 if (!amdgpu_encoder->enc_priv)
 490                         return 0;
 491
 492                 dig = amdgpu_encoder->enc_priv;
 493                 new_coherent_mode = val ? true : false;
 494                 if (dig->coherent_mode != new_coherent_mode) {
 495                         dig->coherent_mode = new_coherent_mode;
 496                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 497                 }
 498         }
 499
 500         if (property == adev->mode_info.audio_property) {
 501                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 502                 /* need to find digital encoder on connector */
 503                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 504                 if (!encoder)
 505                         return 0;
 506
 507                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 508
 509                 if (amdgpu_connector->audio != val) {
 510                         amdgpu_connector->audio = val;
 511                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 512                 }
 513         }
 514
 515         if (property == adev->mode_info.dither_property) {
 516                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 517                 /* need to find digital encoder on connector */
 518                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 519                 if (!encoder)
 520                         return 0;
 521
 522                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 523
 524                 if (amdgpu_connector->dither != val) {
 525                         amdgpu_connector->dither = val;
 526                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 527                 }
 528         }
 529
 530         if (property == adev->mode_info.underscan_property) {
 531                 /* need to find digital encoder on connector */
 532                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 533                 if (!encoder)
 534                         return 0;
 535
 536                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 537
 538                 if (amdgpu_encoder->underscan_type != val) {
 539                         amdgpu_encoder->underscan_type = val;
 540                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 541                 }
 542         }
 543
 544         if (property == adev->mode_info.underscan_hborder_property) {
 545                 /* need to find digital encoder on connector */
 546                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 547                 if (!encoder)
 548                         return 0;
 549
 550                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 551
 552                 if (amdgpu_encoder->underscan_hborder != val) {
 553                         amdgpu_encoder->underscan_hborder = val;
 554                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 555                 }
 556         }
 557
 558         if (property == adev->mode_info.underscan_vborder_property) {
 559                 /* need to find digital encoder on connector */
 560                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 561                 if (!encoder)
 562                         return 0;
 563
 564                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 565
 566                 if (amdgpu_encoder->underscan_vborder != val) {
 567                         amdgpu_encoder->underscan_vborder = val;
 568                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 569                 }
 570         }
 571
 572         if (property == adev->mode_info.load_detect_property) {
 573                 struct amdgpu_connector *amdgpu_connector =
 574                         to_amdgpu_connector(connector);
 575
 576                 if (val == 0)
 577                         amdgpu_connector->dac_load_detect = false;
 578                 else
 579                         amdgpu_connector->dac_load_detect = true;
 580         }
 581
 582         if (property == dev->mode_config.scaling_mode_property) {
 583                 enum amdgpu_rmx_type rmx_type;
 584
 585                 if (connector->encoder) {
 586                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 587                 } else {
 588                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 589                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 590                 }
 591
 592                 switch (val) {
 593                 default:
 594                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 595                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 596                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 597                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 598                 }
 599                 if (amdgpu_encoder->rmx_type == rmx_type)
 600                         return 0;
 601
 602                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 603                     (amdgpu_encoder->native_mode.clock == 0))
 604                         return 0;
 605
 606                 amdgpu_encoder->rmx_type = rmx_type;
 607
 608                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 609         }
 610
 611         return 0;
 612 }
 613
 614 static void
 615 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 616                                         struct drm_connector *connector)
 617 {
 618         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 619         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 620         struct drm_display_mode *t, *mode;
 621
 622         /* If the EDID preferred mode doesn't match the native mode, use it */
 623         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 624                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 625                         if (mode->hdisplay != native_mode->hdisplay ||
 626                             mode->vdisplay != native_mode->vdisplay)
 627                                 memcpy(native_mode, mode, sizeof(*mode));
 628                 }
 629         }
 630
 631         /* Try to get native mode details from EDID if necessary */
 632         if (!native_mode->clock) {
 633                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 634                         if (mode->hdisplay == native_mode->hdisplay &&
 635                             mode->vdisplay == native_mode->vdisplay) {
 636                                 *native_mode = *mode;
 637                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 638                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 639                                 break;
 640                         }
 641                 }
 642         }
 643
 644         if (!native_mode->clock) {
 645                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 646                 amdgpu_encoder->rmx_type = RMX_OFF;
 647         }
 648 }
 649
 650 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 651 {
 652         struct drm_encoder *encoder;
 653         int ret = 0;
 654         struct drm_display_mode *mode;
 655
 656         amdgpu_connector_get_edid(connector);
 657         ret = amdgpu_connector_ddc_get_modes(connector);
 658         if (ret > 0) {
 659                 encoder = amdgpu_connector_best_single_encoder(connector);
 660                 if (encoder) {
 661                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 662                         /* add scaled modes */
 663                         amdgpu_connector_add_common_modes(encoder, connector);
 664                 }
 665                 return ret;
 666         }
 667
 668         encoder = amdgpu_connector_best_single_encoder(connector);
 669         if (!encoder)
 670                 return 0;
 671
 672         /* we have no EDID modes */
 673         mode = amdgpu_connector_lcd_native_mode(encoder);
 674         if (mode) {
 675                 ret = 1;
 676                 drm_mode_probed_add(connector, mode);
 677                 /* add the width/height from vbios tables if available */
 678                 connector->display_info.width_mm = mode->width_mm;
 679                 connector->display_info.height_mm = mode->height_mm;
 680                 /* add scaled modes */
 681                 amdgpu_connector_add_common_modes(encoder, connector);
 682         }
 683
 684         return ret;
 685 }
 686
 687 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 688                                              struct drm_display_mode *mode)
 689 {
 690         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 691
 692         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 693                 return MODE_PANEL;
 694
 695         if (encoder) {
 696                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 697                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 698
 699                 /* AVIVO hardware supports downscaling modes larger than the panel
 700                  * to the panel size, but I'm not sure this is desirable.
 701                  */
 702                 if ((mode->hdisplay > native_mode->hdisplay) ||
 703                     (mode->vdisplay > native_mode->vdisplay))
 704                         return MODE_PANEL;
 705
 706                 /* if scaling is disabled, block non-native modes */
 707                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 708                         if ((mode->hdisplay != native_mode->hdisplay) ||
 709                             (mode->vdisplay != native_mode->vdisplay))
 710                                 return MODE_PANEL;
 711                 }
 712         }
 713
 714         return MODE_OK;
 715 }
 716
 717 static enum drm_connector_status
 718 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 719 {
 720         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 721         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 722         enum drm_connector_status ret = connector_status_disconnected;
 723         int r;
 724
 725         if (!drm_kms_helper_is_poll_worker()) {
 726                 r = pm_runtime_get_sync(connector->dev->dev);
 727                 if (r < 0) {
 728                         pm_runtime_put_autosuspend(connector->dev->dev);
 729                         return connector_status_disconnected;
 730                 }
 731         }
 732
 733         if (encoder) {
 734                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 735                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 736
 737                 /* check if panel is valid */
 738                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 739                         ret = connector_status_connected;
 740
 741         }
 742
 743         /* check for edid as well */
 744         amdgpu_connector_get_edid(connector);
 745         if (amdgpu_connector->edid)
 746                 ret = connector_status_connected;
 747         /* check acpi lid status ??? */
 748
 749         amdgpu_connector_update_scratch_regs(connector, ret);
 750
 751         if (!drm_kms_helper_is_poll_worker()) {
 752                 pm_runtime_mark_last_busy(connector->dev->dev);
 753                 pm_runtime_put_autosuspend(connector->dev->dev);
 754         }
 755
 756         return ret;
 757 }
 758
 759 static void amdgpu_connector_unregister(struct drm_connector *connector)
 760 {
 761         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 762
 763         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 764                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 765                 amdgpu_connector->ddc_bus->has_aux = false;
 766         }
 767 }
 768
 769 static void amdgpu_connector_destroy(struct drm_connector *connector)
 770 {
 771         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 772
 773         amdgpu_connector_free_edid(connector);
 774         kfree(amdgpu_connector->con_priv);
 775         drm_connector_unregister(connector);
 776         drm_connector_cleanup(connector);
 777         kfree(connector);
 778 }
 779
 780 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 781                                               struct drm_property *property,
 782                                               uint64_t value)
 783 {
 784         struct drm_device *dev = connector->dev;
 785         struct amdgpu_encoder *amdgpu_encoder;
 786         enum amdgpu_rmx_type rmx_type;
 787
 788         DRM_DEBUG_KMS("\n");
 789         if (property != dev->mode_config.scaling_mode_property)
 790                 return 0;
 791
 792         if (connector->encoder)
 793                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 794         else {
 795                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 796                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 797         }
 798
 799         switch (value) {
 800         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 801         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 802         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 803         default:
 804         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 805         }
 806         if (amdgpu_encoder->rmx_type == rmx_type)
 807                 return 0;
 808
 809         amdgpu_encoder->rmx_type = rmx_type;
 810
 811         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 812         return 0;
 813 }
 814
 815
 816 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 817         .get_modes = amdgpu_connector_lvds_get_modes,
 818         .mode_valid = amdgpu_connector_lvds_mode_valid,
 819         .best_encoder = amdgpu_connector_best_single_encoder,
 820 };
 821
 822 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 823         .dpms = drm_helper_connector_dpms,
 824         .detect = amdgpu_connector_lvds_detect,
 825         .fill_modes = drm_helper_probe_single_connector_modes,
 826         .early_unregister = amdgpu_connector_unregister,
 827         .destroy = amdgpu_connector_destroy,
 828         .set_property = amdgpu_connector_set_lcd_property,
 829 };
 830
 831 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 832 {
 833         int ret;
 834
 835         amdgpu_connector_get_edid(connector);
 836         ret = amdgpu_connector_ddc_get_modes(connector);
 837         amdgpu_get_native_mode(connector);
 838
 839         return ret;
 840 }
 841
 842 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 843                                             struct drm_display_mode *mode)
 844 {
 845         struct drm_device *dev = connector->dev;
 846         struct amdgpu_device *adev = dev->dev_private;
 847
 848         /* XXX check mode bandwidth */
 849
 850         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 851                 return MODE_CLOCK_HIGH;
 852
 853         return MODE_OK;
 854 }
 855
 856 static enum drm_connector_status
 857 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 858 {
 859         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 860         struct drm_encoder *encoder;
 861         const struct drm_encoder_helper_funcs *encoder_funcs;
 862         bool dret = false;
 863         enum drm_connector_status ret = connector_status_disconnected;
 864         int r;
 865
 866         if (!drm_kms_helper_is_poll_worker()) {
 867                 r = pm_runtime_get_sync(connector->dev->dev);
 868                 if (r < 0) {
 869                         pm_runtime_put_autosuspend(connector->dev->dev);
 870                         return connector_status_disconnected;
 871                 }
 872         }
 873
 874         encoder = amdgpu_connector_best_single_encoder(connector);
 875         if (!encoder)
 876                 ret = connector_status_disconnected;
 877
 878         if (amdgpu_connector->ddc_bus)
 879                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 880         if (dret) {
 881                 amdgpu_connector->detected_by_load = false;
 882                 amdgpu_connector_free_edid(connector);
 883                 amdgpu_connector_get_edid(connector);
 884
 885                 if (!amdgpu_connector->edid) {
 886                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 887                                         connector->name);
 888                         ret = connector_status_connected;
 889                 } else {
 890                         amdgpu_connector->use_digital =
 891                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 892
 893                         /* some oems have boards with separate digital and analog connectors
 894                          * with a shared ddc line (often vga + hdmi)
 895                          */
 896                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 897                                 amdgpu_connector_free_edid(connector);
 898                                 ret = connector_status_disconnected;
 899                         } else {
 900                                 ret = connector_status_connected;
 901                         }
 902                 }
 903         } else {
 904
 905                 /* if we aren't forcing don't do destructive polling */
 906                 if (!force) {
 907                         /* only return the previous status if we last
 908                          * detected a monitor via load.
 909                          */
 910                         if (amdgpu_connector->detected_by_load)
 911                                 ret = connector->status;
 912                         goto out;
 913                 }
 914
 915                 if (amdgpu_connector->dac_load_detect && encoder) {
 916                         encoder_funcs = encoder->helper_private;
 917                         ret = encoder_funcs->detect(encoder, connector);
 918                         if (ret != connector_status_disconnected)
 919                                 amdgpu_connector->detected_by_load = true;
 920                 }
 921         }
 922
 923         amdgpu_connector_update_scratch_regs(connector, ret);
 924
 925 out:
 926         if (!drm_kms_helper_is_poll_worker()) {
 927                 pm_runtime_mark_last_busy(connector->dev->dev);
 928                 pm_runtime_put_autosuspend(connector->dev->dev);
 929         }
 930
 931         return ret;
 932 }
 933
 934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 935         .get_modes = amdgpu_connector_vga_get_modes,
 936         .mode_valid = amdgpu_connector_vga_mode_valid,
 937         .best_encoder = amdgpu_connector_best_single_encoder,
 938 };
 939
 940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 941         .dpms = drm_helper_connector_dpms,
 942         .detect = amdgpu_connector_vga_detect,
 943         .fill_modes = drm_helper_probe_single_connector_modes,
 944         .early_unregister = amdgpu_connector_unregister,
 945         .destroy = amdgpu_connector_destroy,
 946         .set_property = amdgpu_connector_set_property,
 947 };
 948
 949 static bool
 950 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 951 {
 952         struct drm_device *dev = connector->dev;
 953         struct amdgpu_device *adev = dev->dev_private;
 954         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 955         enum drm_connector_status status;
 956
 957         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 958                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 959                         status = connector_status_connected;
 960                 else
 961                         status = connector_status_disconnected;
 962                 if (connector->status == status)
 963                         return true;
 964         }
 965
 966         return false;
 967 }
 968
 969 /*
 970  * DVI is complicated
 971  * Do a DDC probe, if DDC probe passes, get the full EDID so
 972  * we can do analog/digital monitor detection at this point.
 973  * If the monitor is an analog monitor or we got no DDC,
 974  * we need to find the DAC encoder object for this connector.
 975  * If we got no DDC, we do load detection on the DAC encoder object.
 976  * If we got analog DDC or load detection passes on the DAC encoder
 977  * we have to check if this analog encoder is shared with anyone else (TV)
 978  * if its shared we have to set the other connector to disconnected.
 979  */
 980 static enum drm_connector_status
 981 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 982 {
 983         struct drm_device *dev = connector->dev;
 984         struct amdgpu_device *adev = dev->dev_private;
 985         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 986         const struct drm_encoder_helper_funcs *encoder_funcs;
 987         int r;
 988         enum drm_connector_status ret = connector_status_disconnected;
 989         bool dret = false, broken_edid = false;
 990
 991         if (!drm_kms_helper_is_poll_worker()) {
 992                 r = pm_runtime_get_sync(connector->dev->dev);
 993                 if (r < 0) {
 994                         pm_runtime_put_autosuspend(connector->dev->dev);
 995                         return connector_status_disconnected;
 996                 }
 997         }
 998
 999         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1000                 ret = connector->status;
1001                 goto exit;
1002         }
1003
1004         if (amdgpu_connector->ddc_bus)
1005                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1006         if (dret) {
1007                 amdgpu_connector->detected_by_load = false;
1008                 amdgpu_connector_free_edid(connector);
1009                 amdgpu_connector_get_edid(connector);
1010
1011                 if (!amdgpu_connector->edid) {
1012                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1013                                         connector->name);
1014                         ret = connector_status_connected;
1015                         broken_edid = true; /* defer use_digital to later */
1016                 } else {
1017                         amdgpu_connector->use_digital =
1018                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1019
1020                         /* some oems have boards with separate digital and analog connectors
1021                          * with a shared ddc line (often vga + hdmi)
1022                          */
1023                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1024                                 amdgpu_connector_free_edid(connector);
1025                                 ret = connector_status_disconnected;
1026                         } else {
1027                                 ret = connector_status_connected;
1028                         }
1029
1030                         /* This gets complicated.  We have boards with VGA + HDMI with a
1031                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1032                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1033                          * you don't really know what's connected to which port as both are digital.
1034                          */
1035                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1036                                 struct drm_connector *list_connector;
1037                                 struct amdgpu_connector *list_amdgpu_connector;
1038                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1039                                         if (connector == list_connector)
1040                                                 continue;
1041                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1042                                         if (list_amdgpu_connector->shared_ddc &&
1043                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1044                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1045                                                 /* cases where both connectors are digital */
1046                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1047                                                         /* hpd is our only option in this case */
1048                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1049                                                                 amdgpu_connector_free_edid(connector);
1050                                                                 ret = connector_status_disconnected;
1051                                                         }
1052                                                 }
1053                                         }
1054                                 }
1055                         }
1056                 }
1057         }
1058
1059         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1060                 goto out;
1061
1062         /* DVI-D and HDMI-A are digital only */
1063         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1064             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1065                 goto out;
1066
1067         /* if we aren't forcing don't do destructive polling */
1068         if (!force) {
1069                 /* only return the previous status if we last
1070                  * detected a monitor via load.
1071                  */
1072                 if (amdgpu_connector->detected_by_load)
1073                         ret = connector->status;
1074                 goto out;
1075         }
1076
1077         /* find analog encoder */
1078         if (amdgpu_connector->dac_load_detect) {
1079                 struct drm_encoder *encoder;
1080                 int i;
1081
1082                 drm_connector_for_each_possible_encoder(connector, encoder, i) {
1083                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1084                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1085                                 continue;
1086
1087                         encoder_funcs = encoder->helper_private;
1088                         if (encoder_funcs->detect) {
1089                                 if (!broken_edid) {
1090                                         if (ret != connector_status_connected) {
1091                                                 /* deal with analog monitors without DDC */
1092                                                 ret = encoder_funcs->detect(encoder, connector);
1093                                                 if (ret == connector_status_connected) {
1094                                                         amdgpu_connector->use_digital = false;
1095                                                 }
1096                                                 if (ret != connector_status_disconnected)
1097                                                         amdgpu_connector->detected_by_load = true;
1098                                         }
1099                                 } else {
1100                                         enum drm_connector_status lret;
1101                                         /* assume digital unless load detected otherwise */
1102                                         amdgpu_connector->use_digital = true;
1103                                         lret = encoder_funcs->detect(encoder, connector);
1104                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1105                                         if (lret == connector_status_connected)
1106                                                 amdgpu_connector->use_digital = false;
1107                                 }
1108                                 break;
1109                         }
1110                 }
1111         }
1112
1113 out:
1114         /* updated in get modes as well since we need to know if it's analog or digital */
1115         amdgpu_connector_update_scratch_regs(connector, ret);
1116
1117 exit:
1118         if (!drm_kms_helper_is_poll_worker()) {
1119                 pm_runtime_mark_last_busy(connector->dev->dev);
1120                 pm_runtime_put_autosuspend(connector->dev->dev);
1121         }
1122
1123         return ret;
1124 }
1125
1126 /* okay need to be smart in here about which encoder to pick */
1127 static struct drm_encoder *
1128 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1129 {
1130         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1131         struct drm_encoder *encoder;
1132         int i;
1133
1134         drm_connector_for_each_possible_encoder(connector, encoder, i) {
1135                 if (amdgpu_connector->use_digital == true) {
1136                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1137                                 return encoder;
1138                 } else {
1139                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1140                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1141                                 return encoder;
1142                 }
1143         }
1144
1145         /* see if we have a default encoder  TODO */
1146
1147         /* then check use digitial */
1148         /* pick the first one */
1149         drm_connector_for_each_possible_encoder(connector, encoder, i)
1150                 return encoder;
1151
1152         return NULL;
1153 }
1154
1155 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1156 {
1157         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1158         if (connector->force == DRM_FORCE_ON)
1159                 amdgpu_connector->use_digital = false;
1160         if (connector->force == DRM_FORCE_ON_DIGITAL)
1161                 amdgpu_connector->use_digital = true;
1162 }
1163
1164 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1165                                             struct drm_display_mode *mode)
1166 {
1167         struct drm_device *dev = connector->dev;
1168         struct amdgpu_device *adev = dev->dev_private;
1169         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1170
1171         /* XXX check mode bandwidth */
1172
1173         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1174                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1175                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1176                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1177                         return MODE_OK;
1178                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1179                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1180                         if (mode->clock > 340000)
1181                                 return MODE_CLOCK_HIGH;
1182                         else
1183                                 return MODE_OK;
1184                 } else {
1185                         return MODE_CLOCK_HIGH;
1186                 }
1187         }
1188
1189         /* check against the max pixel clock */
1190         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1191                 return MODE_CLOCK_HIGH;
1192
1193         return MODE_OK;
1194 }
1195
1196 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1197         .get_modes = amdgpu_connector_vga_get_modes,
1198         .mode_valid = amdgpu_connector_dvi_mode_valid,
1199         .best_encoder = amdgpu_connector_dvi_encoder,
1200 };
1201
1202 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1203         .dpms = drm_helper_connector_dpms,
1204         .detect = amdgpu_connector_dvi_detect,
1205         .fill_modes = drm_helper_probe_single_connector_modes,
1206         .set_property = amdgpu_connector_set_property,
1207         .early_unregister = amdgpu_connector_unregister,
1208         .destroy = amdgpu_connector_destroy,
1209         .force = amdgpu_connector_dvi_force,
1210 };
1211
1212 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1213 {
1214         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1215         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1216         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1217         int ret;
1218
1219         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1220             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1221                 struct drm_display_mode *mode;
1222
1223                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1224                         if (!amdgpu_dig_connector->edp_on)
1225                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1226                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1227                         amdgpu_connector_get_edid(connector);
1228                         ret = amdgpu_connector_ddc_get_modes(connector);
1229                         if (!amdgpu_dig_connector->edp_on)
1230                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1231                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1232                 } else {
1233                         /* need to setup ddc on the bridge */
1234                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1235                             ENCODER_OBJECT_ID_NONE) {
1236                                 if (encoder)
1237                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1238                         }
1239                         amdgpu_connector_get_edid(connector);
1240                         ret = amdgpu_connector_ddc_get_modes(connector);
1241                 }
1242
1243                 if (ret > 0) {
1244                         if (encoder) {
1245                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1246                                 /* add scaled modes */
1247                                 amdgpu_connector_add_common_modes(encoder, connector);
1248                         }
1249                         return ret;
1250                 }
1251
1252                 if (!encoder)
1253                         return 0;
1254
1255                 /* we have no EDID modes */
1256                 mode = amdgpu_connector_lcd_native_mode(encoder);
1257                 if (mode) {
1258                         ret = 1;
1259                         drm_mode_probed_add(connector, mode);
1260                         /* add the width/height from vbios tables if available */
1261                         connector->display_info.width_mm = mode->width_mm;
1262                         connector->display_info.height_mm = mode->height_mm;
1263                         /* add scaled modes */
1264                         amdgpu_connector_add_common_modes(encoder, connector);
1265                 }
1266         } else {
1267                 /* need to setup ddc on the bridge */
1268                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1269                         ENCODER_OBJECT_ID_NONE) {
1270                         if (encoder)
1271                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1272                 }
1273                 amdgpu_connector_get_edid(connector);
1274                 ret = amdgpu_connector_ddc_get_modes(connector);
1275
1276                 amdgpu_get_native_mode(connector);
1277         }
1278
1279         return ret;
1280 }
1281
1282 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1283 {
1284         struct drm_encoder *encoder;
1285         struct amdgpu_encoder *amdgpu_encoder;
1286         int i;
1287
1288         drm_connector_for_each_possible_encoder(connector, encoder, i) {
1289                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1290
1291                 switch (amdgpu_encoder->encoder_id) {
1292                 case ENCODER_OBJECT_ID_TRAVIS:
1293                 case ENCODER_OBJECT_ID_NUTMEG:
1294                         return amdgpu_encoder->encoder_id;
1295                 default:
1296                         break;
1297                 }
1298         }
1299
1300         return ENCODER_OBJECT_ID_NONE;
1301 }
1302
1303 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1304 {
1305         struct drm_encoder *encoder;
1306         struct amdgpu_encoder *amdgpu_encoder;
1307         int i;
1308         bool found = false;
1309
1310         drm_connector_for_each_possible_encoder(connector, encoder, i) {
1311                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1312                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1313                         found = true;
1314         }
1315
1316         return found;
1317 }
1318
1319 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1320 {
1321         struct drm_device *dev = connector->dev;
1322         struct amdgpu_device *adev = dev->dev_private;
1323
1324         if ((adev->clock.default_dispclk >= 53900) &&
1325             amdgpu_connector_encoder_is_hbr2(connector)) {
1326                 return true;
1327         }
1328
1329         return false;
1330 }
1331
1332 static enum drm_connector_status
1333 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1334 {
1335         struct drm_device *dev = connector->dev;
1336         struct amdgpu_device *adev = dev->dev_private;
1337         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1338         enum drm_connector_status ret = connector_status_disconnected;
1339         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1340         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1341         int r;
1342
1343         if (!drm_kms_helper_is_poll_worker()) {
1344                 r = pm_runtime_get_sync(connector->dev->dev);
1345                 if (r < 0) {
1346                         pm_runtime_put_autosuspend(connector->dev->dev);
1347                         return connector_status_disconnected;
1348                 }
1349         }
1350
1351         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1352                 ret = connector->status;
1353                 goto out;
1354         }
1355
1356         amdgpu_connector_free_edid(connector);
1357
1358         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1359             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1360                 if (encoder) {
1361                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1362                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1363
1364                         /* check if panel is valid */
1365                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1366                                 ret = connector_status_connected;
1367                 }
1368                 /* eDP is always DP */
1369                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1370                 if (!amdgpu_dig_connector->edp_on)
1371                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1372                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1373                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1374                         ret = connector_status_connected;
1375                 if (!amdgpu_dig_connector->edp_on)
1376                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1377                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1378         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1379                    ENCODER_OBJECT_ID_NONE) {
1380                 /* DP bridges are always DP */
1381                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1382                 /* get the DPCD from the bridge */
1383                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1384
1385                 if (encoder) {
1386                         /* setup ddc on the bridge */
1387                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1388                         /* bridge chips are always aux */
1389                         /* try DDC */
1390                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1391                                 ret = connector_status_connected;
1392                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1393                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1394                                 ret = encoder_funcs->detect(encoder, connector);
1395                         }
1396                 }
1397         } else {
1398                 amdgpu_dig_connector->dp_sink_type =
1399                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1400                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1401                         ret = connector_status_connected;
1402                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1403                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1404                 } else {
1405                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1406                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1407                                         ret = connector_status_connected;
1408                         } else {
1409                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1410                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1411                                                              false))
1412                                         ret = connector_status_connected;
1413                         }
1414                 }
1415         }
1416
1417         amdgpu_connector_update_scratch_regs(connector, ret);
1418 out:
1419         if (!drm_kms_helper_is_poll_worker()) {
1420                 pm_runtime_mark_last_busy(connector->dev->dev);
1421                 pm_runtime_put_autosuspend(connector->dev->dev);
1422         }
1423
1424         return ret;
1425 }
1426
1427 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1428                                            struct drm_display_mode *mode)
1429 {
1430         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1431         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1432
1433         /* XXX check mode bandwidth */
1434
1435         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1436             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1437                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1438
1439                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1440                         return MODE_PANEL;
1441
1442                 if (encoder) {
1443                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1444                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1445
1446                         /* AVIVO hardware supports downscaling modes larger than the panel
1447                          * to the panel size, but I'm not sure this is desirable.
1448                          */
1449                         if ((mode->hdisplay > native_mode->hdisplay) ||
1450                             (mode->vdisplay > native_mode->vdisplay))
1451                                 return MODE_PANEL;
1452
1453                         /* if scaling is disabled, block non-native modes */
1454                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1455                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1456                                     (mode->vdisplay != native_mode->vdisplay))
1457                                         return MODE_PANEL;
1458                         }
1459                 }
1460                 return MODE_OK;
1461         } else {
1462                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1463                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1464                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1465                 } else {
1466                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1467                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1468                                 if (mode->clock > 340000)
1469                                         return MODE_CLOCK_HIGH;
1470                         } else {
1471                                 if (mode->clock > 165000)
1472                                         return MODE_CLOCK_HIGH;
1473                         }
1474                 }
1475         }
1476
1477         return MODE_OK;
1478 }
1479
1480 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1481         .get_modes = amdgpu_connector_dp_get_modes,
1482         .mode_valid = amdgpu_connector_dp_mode_valid,
1483         .best_encoder = amdgpu_connector_dvi_encoder,
1484 };
1485
1486 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1487         .dpms = drm_helper_connector_dpms,
1488         .detect = amdgpu_connector_dp_detect,
1489         .fill_modes = drm_helper_probe_single_connector_modes,
1490         .set_property = amdgpu_connector_set_property,
1491         .early_unregister = amdgpu_connector_unregister,
1492         .destroy = amdgpu_connector_destroy,
1493         .force = amdgpu_connector_dvi_force,
1494 };
1495
1496 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1497         .dpms = drm_helper_connector_dpms,
1498         .detect = amdgpu_connector_dp_detect,
1499         .fill_modes = drm_helper_probe_single_connector_modes,
1500         .set_property = amdgpu_connector_set_lcd_property,
1501         .early_unregister = amdgpu_connector_unregister,
1502         .destroy = amdgpu_connector_destroy,
1503         .force = amdgpu_connector_dvi_force,
1504 };
1505
1506 void
1507 amdgpu_connector_add(struct amdgpu_device *adev,
1508                       uint32_t connector_id,
1509                       uint32_t supported_device,
1510                       int connector_type,
1511                       struct amdgpu_i2c_bus_rec *i2c_bus,
1512                       uint16_t connector_object_id,
1513                       struct amdgpu_hpd *hpd,
1514                       struct amdgpu_router *router)
1515 {
1516         struct drm_device *dev = adev->ddev;
1517         struct drm_connector *connector;
1518         struct amdgpu_connector *amdgpu_connector;
1519         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1520         struct drm_encoder *encoder;
1521         struct amdgpu_encoder *amdgpu_encoder;
1522         uint32_t subpixel_order = SubPixelNone;
1523         bool shared_ddc = false;
1524         bool is_dp_bridge = false;
1525         bool has_aux = false;
1526
1527         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1528                 return;
1529
1530         /* see if we already added it */
1531         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1532                 amdgpu_connector = to_amdgpu_connector(connector);
1533                 if (amdgpu_connector->connector_id == connector_id) {
1534                         amdgpu_connector->devices |= supported_device;
1535                         return;
1536                 }
1537                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1538                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1539                                 amdgpu_connector->shared_ddc = true;
1540                                 shared_ddc = true;
1541                         }
1542                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1543                             (amdgpu_connector->router.router_id == router->router_id)) {
1544                                 amdgpu_connector->shared_ddc = false;
1545                                 shared_ddc = false;
1546                         }
1547                 }
1548         }
1549
1550         /* check if it's a dp bridge */
1551         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1552                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1553                 if (amdgpu_encoder->devices & supported_device) {
1554                         switch (amdgpu_encoder->encoder_id) {
1555                         case ENCODER_OBJECT_ID_TRAVIS:
1556                         case ENCODER_OBJECT_ID_NUTMEG:
1557                                 is_dp_bridge = true;
1558                                 break;
1559                         default:
1560                                 break;
1561                         }
1562                 }
1563         }
1564
1565         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1566         if (!amdgpu_connector)
1567                 return;
1568
1569         connector = &amdgpu_connector->base;
1570
1571         amdgpu_connector->connector_id = connector_id;
1572         amdgpu_connector->devices = supported_device;
1573         amdgpu_connector->shared_ddc = shared_ddc;
1574         amdgpu_connector->connector_object_id = connector_object_id;
1575         amdgpu_connector->hpd = *hpd;
1576
1577         amdgpu_connector->router = *router;
1578         if (router->ddc_valid || router->cd_valid) {
1579                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1580                 if (!amdgpu_connector->router_bus)
1581                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1582         }
1583
1584         if (is_dp_bridge) {
1585                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1586                 if (!amdgpu_dig_connector)
1587                         goto failed;
1588                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1589                 if (i2c_bus->valid) {
1590                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1591                         if (amdgpu_connector->ddc_bus)
1592                                 has_aux = true;
1593                         else
1594                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1595                 }
1596                 switch (connector_type) {
1597                 case DRM_MODE_CONNECTOR_VGA:
1598                 case DRM_MODE_CONNECTOR_DVIA:
1599                 default:
1600                         drm_connector_init(dev, &amdgpu_connector->base,
1601                                            &amdgpu_connector_dp_funcs, connector_type);
1602                         drm_connector_helper_add(&amdgpu_connector->base,
1603                                                  &amdgpu_connector_dp_helper_funcs);
1604                         connector->interlace_allowed = true;
1605                         connector->doublescan_allowed = true;
1606                         amdgpu_connector->dac_load_detect = true;
1607                         drm_object_attach_property(&amdgpu_connector->base.base,
1608                                                       adev->mode_info.load_detect_property,
1609                                                       1);
1610                         drm_object_attach_property(&amdgpu_connector->base.base,
1611                                                    dev->mode_config.scaling_mode_property,
1612                                                    DRM_MODE_SCALE_NONE);
1613                         break;
1614                 case DRM_MODE_CONNECTOR_DVII:
1615                 case DRM_MODE_CONNECTOR_DVID:
1616                 case DRM_MODE_CONNECTOR_HDMIA:
1617                 case DRM_MODE_CONNECTOR_HDMIB:
1618                 case DRM_MODE_CONNECTOR_DisplayPort:
1619                         drm_connector_init(dev, &amdgpu_connector->base,
1620                                            &amdgpu_connector_dp_funcs, connector_type);
1621                         drm_connector_helper_add(&amdgpu_connector->base,
1622                                                  &amdgpu_connector_dp_helper_funcs);
1623                         drm_object_attach_property(&amdgpu_connector->base.base,
1624                                                       adev->mode_info.underscan_property,
1625                                                       UNDERSCAN_OFF);
1626                         drm_object_attach_property(&amdgpu_connector->base.base,
1627                                                       adev->mode_info.underscan_hborder_property,
1628                                                       0);
1629                         drm_object_attach_property(&amdgpu_connector->base.base,
1630                                                       adev->mode_info.underscan_vborder_property,
1631                                                       0);
1632
1633                         drm_object_attach_property(&amdgpu_connector->base.base,
1634                                                    dev->mode_config.scaling_mode_property,
1635                                                    DRM_MODE_SCALE_NONE);
1636
1637                         drm_object_attach_property(&amdgpu_connector->base.base,
1638                                                    adev->mode_info.dither_property,
1639                                                    AMDGPU_FMT_DITHER_DISABLE);
1640
1641                         if (amdgpu_audio != 0)
1642                                 drm_object_attach_property(&amdgpu_connector->base.base,
1643                                                            adev->mode_info.audio_property,
1644                                                            AMDGPU_AUDIO_AUTO);
1645
1646                         subpixel_order = SubPixelHorizontalRGB;
1647                         connector->interlace_allowed = true;
1648                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1649                                 connector->doublescan_allowed = true;
1650                         else
1651                                 connector->doublescan_allowed = false;
1652                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1653                                 amdgpu_connector->dac_load_detect = true;
1654                                 drm_object_attach_property(&amdgpu_connector->base.base,
1655                                                               adev->mode_info.load_detect_property,
1656                                                               1);
1657                         }
1658                         break;
1659                 case DRM_MODE_CONNECTOR_LVDS:
1660                 case DRM_MODE_CONNECTOR_eDP:
1661                         drm_connector_init(dev, &amdgpu_connector->base,
1662                                            &amdgpu_connector_edp_funcs, connector_type);
1663                         drm_connector_helper_add(&amdgpu_connector->base,
1664                                                  &amdgpu_connector_dp_helper_funcs);
1665                         drm_object_attach_property(&amdgpu_connector->base.base,
1666                                                       dev->mode_config.scaling_mode_property,
1667                                                       DRM_MODE_SCALE_FULLSCREEN);
1668                         subpixel_order = SubPixelHorizontalRGB;
1669                         connector->interlace_allowed = false;
1670                         connector->doublescan_allowed = false;
1671                         break;
1672                 }
1673         } else {
1674                 switch (connector_type) {
1675                 case DRM_MODE_CONNECTOR_VGA:
1676                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1677                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1678                         if (i2c_bus->valid) {
1679                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1680                                 if (!amdgpu_connector->ddc_bus)
1681                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1682                         }
1683                         amdgpu_connector->dac_load_detect = true;
1684                         drm_object_attach_property(&amdgpu_connector->base.base,
1685                                                       adev->mode_info.load_detect_property,
1686                                                       1);
1687                         drm_object_attach_property(&amdgpu_connector->base.base,
1688                                                    dev->mode_config.scaling_mode_property,
1689                                                    DRM_MODE_SCALE_NONE);
1690                         /* no HPD on analog connectors */
1691                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1692                         connector->interlace_allowed = true;
1693                         connector->doublescan_allowed = true;
1694                         break;
1695                 case DRM_MODE_CONNECTOR_DVIA:
1696                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1697                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1698                         if (i2c_bus->valid) {
1699                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1700                                 if (!amdgpu_connector->ddc_bus)
1701                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1702                         }
1703                         amdgpu_connector->dac_load_detect = true;
1704                         drm_object_attach_property(&amdgpu_connector->base.base,
1705                                                       adev->mode_info.load_detect_property,
1706                                                       1);
1707                         drm_object_attach_property(&amdgpu_connector->base.base,
1708                                                    dev->mode_config.scaling_mode_property,
1709                                                    DRM_MODE_SCALE_NONE);
1710                         /* no HPD on analog connectors */
1711                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1712                         connector->interlace_allowed = true;
1713                         connector->doublescan_allowed = true;
1714                         break;
1715                 case DRM_MODE_CONNECTOR_DVII:
1716                 case DRM_MODE_CONNECTOR_DVID:
1717                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1718                         if (!amdgpu_dig_connector)
1719                                 goto failed;
1720                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1721                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1722                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1723                         if (i2c_bus->valid) {
1724                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1725                                 if (!amdgpu_connector->ddc_bus)
1726                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1727                         }
1728                         subpixel_order = SubPixelHorizontalRGB;
1729                         drm_object_attach_property(&amdgpu_connector->base.base,
1730                                                       adev->mode_info.coherent_mode_property,
1731                                                       1);
1732                         drm_object_attach_property(&amdgpu_connector->base.base,
1733                                                    adev->mode_info.underscan_property,
1734                                                    UNDERSCAN_OFF);
1735                         drm_object_attach_property(&amdgpu_connector->base.base,
1736                                                    adev->mode_info.underscan_hborder_property,
1737                                                    0);
1738                         drm_object_attach_property(&amdgpu_connector->base.base,
1739                                                    adev->mode_info.underscan_vborder_property,
1740                                                    0);
1741                         drm_object_attach_property(&amdgpu_connector->base.base,
1742                                                    dev->mode_config.scaling_mode_property,
1743                                                    DRM_MODE_SCALE_NONE);
1744
1745                         if (amdgpu_audio != 0) {
1746                                 drm_object_attach_property(&amdgpu_connector->base.base,
1747                                                            adev->mode_info.audio_property,
1748                                                            AMDGPU_AUDIO_AUTO);
1749                         }
1750                         drm_object_attach_property(&amdgpu_connector->base.base,
1751                                                    adev->mode_info.dither_property,
1752                                                    AMDGPU_FMT_DITHER_DISABLE);
1753                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1754                                 amdgpu_connector->dac_load_detect = true;
1755                                 drm_object_attach_property(&amdgpu_connector->base.base,
1756                                                            adev->mode_info.load_detect_property,
1757                                                            1);
1758                         }
1759                         connector->interlace_allowed = true;
1760                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1761                                 connector->doublescan_allowed = true;
1762                         else
1763                                 connector->doublescan_allowed = false;
1764                         break;
1765                 case DRM_MODE_CONNECTOR_HDMIA:
1766                 case DRM_MODE_CONNECTOR_HDMIB:
1767                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1768                         if (!amdgpu_dig_connector)
1769                                 goto failed;
1770                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1771                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1772                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1773                         if (i2c_bus->valid) {
1774                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1775                                 if (!amdgpu_connector->ddc_bus)
1776                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1777                         }
1778                         drm_object_attach_property(&amdgpu_connector->base.base,
1779                                                       adev->mode_info.coherent_mode_property,
1780                                                       1);
1781                         drm_object_attach_property(&amdgpu_connector->base.base,
1782                                                    adev->mode_info.underscan_property,
1783                                                    UNDERSCAN_OFF);
1784                         drm_object_attach_property(&amdgpu_connector->base.base,
1785                                                    adev->mode_info.underscan_hborder_property,
1786                                                    0);
1787                         drm_object_attach_property(&amdgpu_connector->base.base,
1788                                                    adev->mode_info.underscan_vborder_property,
1789                                                    0);
1790                         drm_object_attach_property(&amdgpu_connector->base.base,
1791                                                    dev->mode_config.scaling_mode_property,
1792                                                    DRM_MODE_SCALE_NONE);
1793                         if (amdgpu_audio != 0) {
1794                                 drm_object_attach_property(&amdgpu_connector->base.base,
1795                                                            adev->mode_info.audio_property,
1796                                                            AMDGPU_AUDIO_AUTO);
1797                         }
1798                         drm_object_attach_property(&amdgpu_connector->base.base,
1799                                                    adev->mode_info.dither_property,
1800                                                    AMDGPU_FMT_DITHER_DISABLE);
1801                         subpixel_order = SubPixelHorizontalRGB;
1802                         connector->interlace_allowed = true;
1803                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1804                                 connector->doublescan_allowed = true;
1805                         else
1806                                 connector->doublescan_allowed = false;
1807                         break;
1808                 case DRM_MODE_CONNECTOR_DisplayPort:
1809                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1810                         if (!amdgpu_dig_connector)
1811                                 goto failed;
1812                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1813                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1814                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1815                         if (i2c_bus->valid) {
1816                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1817                                 if (amdgpu_connector->ddc_bus)
1818                                         has_aux = true;
1819                                 else
1820                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1821                         }
1822                         subpixel_order = SubPixelHorizontalRGB;
1823                         drm_object_attach_property(&amdgpu_connector->base.base,
1824                                                       adev->mode_info.coherent_mode_property,
1825                                                       1);
1826                         drm_object_attach_property(&amdgpu_connector->base.base,
1827                                                    adev->mode_info.underscan_property,
1828                                                    UNDERSCAN_OFF);
1829                         drm_object_attach_property(&amdgpu_connector->base.base,
1830                                                    adev->mode_info.underscan_hborder_property,
1831                                                    0);
1832                         drm_object_attach_property(&amdgpu_connector->base.base,
1833                                                    adev->mode_info.underscan_vborder_property,
1834                                                    0);
1835                         drm_object_attach_property(&amdgpu_connector->base.base,
1836                                                    dev->mode_config.scaling_mode_property,
1837                                                    DRM_MODE_SCALE_NONE);
1838                         if (amdgpu_audio != 0) {
1839                                 drm_object_attach_property(&amdgpu_connector->base.base,
1840                                                            adev->mode_info.audio_property,
1841                                                            AMDGPU_AUDIO_AUTO);
1842                         }
1843                         drm_object_attach_property(&amdgpu_connector->base.base,
1844                                                    adev->mode_info.dither_property,
1845                                                    AMDGPU_FMT_DITHER_DISABLE);
1846                         connector->interlace_allowed = true;
1847                         /* in theory with a DP to VGA converter... */
1848                         connector->doublescan_allowed = false;
1849                         break;
1850                 case DRM_MODE_CONNECTOR_eDP:
1851                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1852                         if (!amdgpu_dig_connector)
1853                                 goto failed;
1854                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1855                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1856                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1857                         if (i2c_bus->valid) {
1858                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1859                                 if (amdgpu_connector->ddc_bus)
1860                                         has_aux = true;
1861                                 else
1862                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1863                         }
1864                         drm_object_attach_property(&amdgpu_connector->base.base,
1865                                                       dev->mode_config.scaling_mode_property,
1866                                                       DRM_MODE_SCALE_FULLSCREEN);
1867                         subpixel_order = SubPixelHorizontalRGB;
1868                         connector->interlace_allowed = false;
1869                         connector->doublescan_allowed = false;
1870                         break;
1871                 case DRM_MODE_CONNECTOR_LVDS:
1872                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1873                         if (!amdgpu_dig_connector)
1874                                 goto failed;
1875                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1876                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1877                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1878                         if (i2c_bus->valid) {
1879                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1880                                 if (!amdgpu_connector->ddc_bus)
1881                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1882                         }
1883                         drm_object_attach_property(&amdgpu_connector->base.base,
1884                                                       dev->mode_config.scaling_mode_property,
1885                                                       DRM_MODE_SCALE_FULLSCREEN);
1886                         subpixel_order = SubPixelHorizontalRGB;
1887                         connector->interlace_allowed = false;
1888                         connector->doublescan_allowed = false;
1889                         break;
1890                 }
1891         }
1892
1893         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1894                 if (i2c_bus->valid) {
1895                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1896                                             DRM_CONNECTOR_POLL_DISCONNECT;
1897                 }
1898         } else
1899                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1900
1901         connector->display_info.subpixel_order = subpixel_order;
1902         drm_connector_register(connector);
1903
1904         if (has_aux)
1905                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1906
1907         return;
1908
1909 failed:
1910         drm_connector_cleanup(connector);
1911         kfree(connector);
1912 }