drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_fb_helper.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "atom.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_i2c.h"
  37
  38 #include <linux/pm_runtime.h>
  39
  40 void amdgpu_connector_hotplug(struct drm_connector *connector)
  41 {
  42         struct drm_device *dev = connector->dev;
  43         struct amdgpu_device *adev = dev->dev_private;
  44         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  45
  46         /* bail if the connector does not have hpd pin, e.g.,
  47          * VGA, TV, etc.
  48          */
  49         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  50                 return;
  51
  52         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  53
  54         /* if the connector is already off, don't turn it back on */
  55         if (connector->dpms != DRM_MODE_DPMS_ON)
  56                 return;
  57
  58         /* just deal with DP (not eDP) here. */
  59         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  60                 struct amdgpu_connector_atom_dig *dig_connector =
  61                         amdgpu_connector->con_priv;
  62
  63                 /* if existing sink type was not DP no need to retrain */
  64                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  65                         return;
  66
  67                 /* first get sink type as it may be reset after (un)plug */
  68                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  69                 /* don't do anything if sink is not display port, i.e.,
  70                  * passive dp->(dvi|hdmi) adaptor
  71                  */
  72                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  73                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  74                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  75                         /* Don't start link training before we have the DPCD */
  76                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  77                                 return;
  78
  79                         /* Turn the connector off and back on immediately, which
  80                          * will trigger link training
  81                          */
  82                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  83                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  84                 }
  85         }
  86 }
  87
  88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  89 {
  90         struct drm_crtc *crtc = encoder->crtc;
  91
  92         if (crtc && crtc->enabled) {
  93                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  94                                          crtc->x, crtc->y, crtc->primary->fb);
  95         }
  96 }
  97
  98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
  99 {
 100         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 101         struct amdgpu_connector_atom_dig *dig_connector;
 102         int bpc = 8;
 103         unsigned mode_clock, max_tmds_clock;
 104
 105         switch (connector->connector_type) {
 106         case DRM_MODE_CONNECTOR_DVII:
 107         case DRM_MODE_CONNECTOR_HDMIB:
 108                 if (amdgpu_connector->use_digital) {
 109                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 110                                 if (connector->display_info.bpc)
 111                                         bpc = connector->display_info.bpc;
 112                         }
 113                 }
 114                 break;
 115         case DRM_MODE_CONNECTOR_DVID:
 116         case DRM_MODE_CONNECTOR_HDMIA:
 117                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 118                         if (connector->display_info.bpc)
 119                                 bpc = connector->display_info.bpc;
 120                 }
 121                 break;
 122         case DRM_MODE_CONNECTOR_DisplayPort:
 123                 dig_connector = amdgpu_connector->con_priv;
 124                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 125                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 126                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 127                         if (connector->display_info.bpc)
 128                                 bpc = connector->display_info.bpc;
 129                 }
 130                 break;
 131         case DRM_MODE_CONNECTOR_eDP:
 132         case DRM_MODE_CONNECTOR_LVDS:
 133                 if (connector->display_info.bpc)
 134                         bpc = connector->display_info.bpc;
 135                 else {
 136                         const struct drm_connector_helper_funcs *connector_funcs =
 137                                 connector->helper_private;
 138                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 139                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 140                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 141
 142                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 143                                 bpc = 6;
 144                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 145                                 bpc = 8;
 146                 }
 147                 break;
 148         }
 149
 150         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 151                 /*
 152                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 153                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 154                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 155                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 156                  */
 157                 if (bpc > 12) {
 158                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 159                                   connector->name, bpc);
 160                         bpc = 12;
 161                 }
 162
 163                 /* Any defined maximum tmds clock limit we must not exceed? */
 164                 if (connector->max_tmds_clock > 0) {
 165                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 166                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 167
 168                         /* Maximum allowable input clock in kHz */
 169                         max_tmds_clock = connector->max_tmds_clock * 1000;
 170
 171                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 172                                   connector->name, mode_clock, max_tmds_clock);
 173
 174                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 175                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 176                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 177                                     (mode_clock * 5/4 <= max_tmds_clock))
 178                                         bpc = 10;
 179                                 else
 180                                         bpc = 8;
 181
 182                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 183                                           connector->name, bpc);
 184                         }
 185
 186                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 187                                 bpc = 8;
 188                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 189                                           connector->name, bpc);
 190                         }
 191                 } else if (bpc > 8) {
 192                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 193                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 194                                   connector->name);
 195                         bpc = 8;
 196                 }
 197         }
 198
 199         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 200                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 201                           connector->name);
 202                 bpc = 8;
 203         }
 204
 205         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 206                   connector->name, connector->display_info.bpc, bpc);
 207
 208         return bpc;
 209 }
 210
 211 static void
 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 213                                       enum drm_connector_status status)
 214 {
 215         struct drm_encoder *best_encoder = NULL;
 216         struct drm_encoder *encoder = NULL;
 217         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 218         bool connected;
 219         int i;
 220
 221         best_encoder = connector_funcs->best_encoder(connector);
 222
 223         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 224                 if (connector->encoder_ids[i] == 0)
 225                         break;
 226
 227                 encoder = drm_encoder_find(connector->dev,
 228                                         connector->encoder_ids[i]);
 229                 if (!encoder)
 230                         continue;
 231
 232                 if ((encoder == best_encoder) && (status == connector_status_connected))
 233                         connected = true;
 234                 else
 235                         connected = false;
 236
 237                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 238
 239         }
 240 }
 241
 242 static struct drm_encoder *
 243 amdgpu_connector_find_encoder(struct drm_connector *connector,
 244                                int encoder_type)
 245 {
 246         struct drm_encoder *encoder;
 247         int i;
 248
 249         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 250                 if (connector->encoder_ids[i] == 0)
 251                         break;
 252                 encoder = drm_encoder_find(connector->dev,
 253                                         connector->encoder_ids[i]);
 254                 if (!encoder)
 255                         continue;
 256
 257                 if (encoder->encoder_type == encoder_type)
 258                         return encoder;
 259         }
 260         return NULL;
 261 }
 262
 263 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 264 {
 265         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 266         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 267
 268         if (amdgpu_connector->edid) {
 269                 return amdgpu_connector->edid;
 270         } else if (edid_blob) {
 271                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 272                 if (edid)
 273                         amdgpu_connector->edid = edid;
 274         }
 275         return amdgpu_connector->edid;
 276 }
 277
 278 static struct edid *
 279 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 280 {
 281         struct edid *edid;
 282
 283         if (adev->mode_info.bios_hardcoded_edid) {
 284                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 285                 if (edid) {
 286                         memcpy((unsigned char *)edid,
 287                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 288                                adev->mode_info.bios_hardcoded_edid_size);
 289                         return edid;
 290                 }
 291         }
 292         return NULL;
 293 }
 294
 295 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 296 {
 297         struct drm_device *dev = connector->dev;
 298         struct amdgpu_device *adev = dev->dev_private;
 299         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 300
 301         if (amdgpu_connector->edid)
 302                 return;
 303
 304         /* on hw with routers, select right port */
 305         if (amdgpu_connector->router.ddc_valid)
 306                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 307
 308         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 309              ENCODER_OBJECT_ID_NONE) &&
 310             amdgpu_connector->ddc_bus->has_aux) {
 311                 amdgpu_connector->edid = drm_get_edid(connector,
 312                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 313         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 314                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 315                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 316
 317                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 318                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 319                     amdgpu_connector->ddc_bus->has_aux)
 320                         amdgpu_connector->edid = drm_get_edid(connector,
 321                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 322                 else if (amdgpu_connector->ddc_bus)
 323                         amdgpu_connector->edid = drm_get_edid(connector,
 324                                                               &amdgpu_connector->ddc_bus->adapter);
 325         } else if (amdgpu_connector->ddc_bus) {
 326                 amdgpu_connector->edid = drm_get_edid(connector,
 327                                                       &amdgpu_connector->ddc_bus->adapter);
 328         }
 329
 330         if (!amdgpu_connector->edid) {
 331                 /* some laptops provide a hardcoded edid in rom for LCDs */
 332                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 333                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 334                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 335         }
 336 }
 337
 338 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 339 {
 340         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 341
 342         if (amdgpu_connector->edid) {
 343                 kfree(amdgpu_connector->edid);
 344                 amdgpu_connector->edid = NULL;
 345         }
 346 }
 347
 348 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 349 {
 350         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 351         int ret;
 352
 353         if (amdgpu_connector->edid) {
 354                 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
 355                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 356                 drm_edid_to_eld(connector, amdgpu_connector->edid);
 357                 return ret;
 358         }
 359         drm_mode_connector_update_edid_property(connector, NULL);
 360         return 0;
 361 }
 362
 363 static struct drm_encoder *
 364 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 365 {
 366         int enc_id = connector->encoder_ids[0];
 367
 368         /* pick the encoder ids */
 369         if (enc_id)
 370                 return drm_encoder_find(connector->dev, enc_id);
 371         return NULL;
 372 }
 373
 374 static void amdgpu_get_native_mode(struct drm_connector *connector)
 375 {
 376         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 377         struct amdgpu_encoder *amdgpu_encoder;
 378
 379         if (encoder == NULL)
 380                 return;
 381
 382         amdgpu_encoder = to_amdgpu_encoder(encoder);
 383
 384         if (!list_empty(&connector->probed_modes)) {
 385                 struct drm_display_mode *preferred_mode =
 386                         list_first_entry(&connector->probed_modes,
 387                                          struct drm_display_mode, head);
 388
 389                 amdgpu_encoder->native_mode = *preferred_mode;
 390         } else {
 391                 amdgpu_encoder->native_mode.clock = 0;
 392         }
 393 }
 394
 395 static struct drm_display_mode *
 396 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 397 {
 398         struct drm_device *dev = encoder->dev;
 399         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 400         struct drm_display_mode *mode = NULL;
 401         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 402
 403         if (native_mode->hdisplay != 0 &&
 404             native_mode->vdisplay != 0 &&
 405             native_mode->clock != 0) {
 406                 mode = drm_mode_duplicate(dev, native_mode);
 407                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 408                 drm_mode_set_name(mode);
 409
 410                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 411         } else if (native_mode->hdisplay != 0 &&
 412                    native_mode->vdisplay != 0) {
 413                 /* mac laptops without an edid */
 414                 /* Note that this is not necessarily the exact panel mode,
 415                  * but an approximation based on the cvt formula.  For these
 416                  * systems we should ideally read the mode info out of the
 417                  * registers or add a mode table, but this works and is much
 418                  * simpler.
 419                  */
 420                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 421                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 422                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 423         }
 424         return mode;
 425 }
 426
 427 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 428                                                struct drm_connector *connector)
 429 {
 430         struct drm_device *dev = encoder->dev;
 431         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 432         struct drm_display_mode *mode = NULL;
 433         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 434         int i;
 435         struct mode_size {
 436                 int w;
 437                 int h;
 438         } common_modes[17] = {
 439                 { 640,  480},
 440                 { 720,  480},
 441                 { 800,  600},
 442                 { 848,  480},
 443                 {1024,  768},
 444                 {1152,  768},
 445                 {1280,  720},
 446                 {1280,  800},
 447                 {1280,  854},
 448                 {1280,  960},
 449                 {1280, 1024},
 450                 {1440,  900},
 451                 {1400, 1050},
 452                 {1680, 1050},
 453                 {1600, 1200},
 454                 {1920, 1080},
 455                 {1920, 1200}
 456         };
 457
 458         for (i = 0; i < 17; i++) {
 459                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 460                         if (common_modes[i].w > 1024 ||
 461                             common_modes[i].h > 768)
 462                                 continue;
 463                 }
 464                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 465                         if (common_modes[i].w > native_mode->hdisplay ||
 466                             common_modes[i].h > native_mode->vdisplay ||
 467                             (common_modes[i].w == native_mode->hdisplay &&
 468                              common_modes[i].h == native_mode->vdisplay))
 469                                 continue;
 470                 }
 471                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 472                         continue;
 473
 474                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 475                 drm_mode_probed_add(connector, mode);
 476         }
 477 }
 478
 479 static int amdgpu_connector_set_property(struct drm_connector *connector,
 480                                           struct drm_property *property,
 481                                           uint64_t val)
 482 {
 483         struct drm_device *dev = connector->dev;
 484         struct amdgpu_device *adev = dev->dev_private;
 485         struct drm_encoder *encoder;
 486         struct amdgpu_encoder *amdgpu_encoder;
 487
 488         if (property == adev->mode_info.coherent_mode_property) {
 489                 struct amdgpu_encoder_atom_dig *dig;
 490                 bool new_coherent_mode;
 491
 492                 /* need to find digital encoder on connector */
 493                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 494                 if (!encoder)
 495                         return 0;
 496
 497                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 498
 499                 if (!amdgpu_encoder->enc_priv)
 500                         return 0;
 501
 502                 dig = amdgpu_encoder->enc_priv;
 503                 new_coherent_mode = val ? true : false;
 504                 if (dig->coherent_mode != new_coherent_mode) {
 505                         dig->coherent_mode = new_coherent_mode;
 506                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 507                 }
 508         }
 509
 510         if (property == adev->mode_info.audio_property) {
 511                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 512                 /* need to find digital encoder on connector */
 513                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 514                 if (!encoder)
 515                         return 0;
 516
 517                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 518
 519                 if (amdgpu_connector->audio != val) {
 520                         amdgpu_connector->audio = val;
 521                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 522                 }
 523         }
 524
 525         if (property == adev->mode_info.dither_property) {
 526                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 527                 /* need to find digital encoder on connector */
 528                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 529                 if (!encoder)
 530                         return 0;
 531
 532                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 533
 534                 if (amdgpu_connector->dither != val) {
 535                         amdgpu_connector->dither = val;
 536                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 537                 }
 538         }
 539
 540         if (property == adev->mode_info.underscan_property) {
 541                 /* need to find digital encoder on connector */
 542                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 543                 if (!encoder)
 544                         return 0;
 545
 546                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 547
 548                 if (amdgpu_encoder->underscan_type != val) {
 549                         amdgpu_encoder->underscan_type = val;
 550                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 551                 }
 552         }
 553
 554         if (property == adev->mode_info.underscan_hborder_property) {
 555                 /* need to find digital encoder on connector */
 556                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 557                 if (!encoder)
 558                         return 0;
 559
 560                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 561
 562                 if (amdgpu_encoder->underscan_hborder != val) {
 563                         amdgpu_encoder->underscan_hborder = val;
 564                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 565                 }
 566         }
 567
 568         if (property == adev->mode_info.underscan_vborder_property) {
 569                 /* need to find digital encoder on connector */
 570                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 571                 if (!encoder)
 572                         return 0;
 573
 574                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 575
 576                 if (amdgpu_encoder->underscan_vborder != val) {
 577                         amdgpu_encoder->underscan_vborder = val;
 578                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 579                 }
 580         }
 581
 582         if (property == adev->mode_info.load_detect_property) {
 583                 struct amdgpu_connector *amdgpu_connector =
 584                         to_amdgpu_connector(connector);
 585
 586                 if (val == 0)
 587                         amdgpu_connector->dac_load_detect = false;
 588                 else
 589                         amdgpu_connector->dac_load_detect = true;
 590         }
 591
 592         if (property == dev->mode_config.scaling_mode_property) {
 593                 enum amdgpu_rmx_type rmx_type;
 594
 595                 if (connector->encoder) {
 596                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 597                 } else {
 598                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 599                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 600                 }
 601
 602                 switch (val) {
 603                 default:
 604                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 605                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 606                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 607                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 608                 }
 609                 if (amdgpu_encoder->rmx_type == rmx_type)
 610                         return 0;
 611
 612                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 613                     (amdgpu_encoder->native_mode.clock == 0))
 614                         return 0;
 615
 616                 amdgpu_encoder->rmx_type = rmx_type;
 617
 618                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 619         }
 620
 621         return 0;
 622 }
 623
 624 static void
 625 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 626                                         struct drm_connector *connector)
 627 {
 628         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 629         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 630         struct drm_display_mode *t, *mode;
 631
 632         /* If the EDID preferred mode doesn't match the native mode, use it */
 633         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 634                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 635                         if (mode->hdisplay != native_mode->hdisplay ||
 636                             mode->vdisplay != native_mode->vdisplay)
 637                                 memcpy(native_mode, mode, sizeof(*mode));
 638                 }
 639         }
 640
 641         /* Try to get native mode details from EDID if necessary */
 642         if (!native_mode->clock) {
 643                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 644                         if (mode->hdisplay == native_mode->hdisplay &&
 645                             mode->vdisplay == native_mode->vdisplay) {
 646                                 *native_mode = *mode;
 647                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 648                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 649                                 break;
 650                         }
 651                 }
 652         }
 653
 654         if (!native_mode->clock) {
 655                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 656                 amdgpu_encoder->rmx_type = RMX_OFF;
 657         }
 658 }
 659
 660 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 661 {
 662         struct drm_encoder *encoder;
 663         int ret = 0;
 664         struct drm_display_mode *mode;
 665
 666         amdgpu_connector_get_edid(connector);
 667         ret = amdgpu_connector_ddc_get_modes(connector);
 668         if (ret > 0) {
 669                 encoder = amdgpu_connector_best_single_encoder(connector);
 670                 if (encoder) {
 671                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 672                         /* add scaled modes */
 673                         amdgpu_connector_add_common_modes(encoder, connector);
 674                 }
 675                 return ret;
 676         }
 677
 678         encoder = amdgpu_connector_best_single_encoder(connector);
 679         if (!encoder)
 680                 return 0;
 681
 682         /* we have no EDID modes */
 683         mode = amdgpu_connector_lcd_native_mode(encoder);
 684         if (mode) {
 685                 ret = 1;
 686                 drm_mode_probed_add(connector, mode);
 687                 /* add the width/height from vbios tables if available */
 688                 connector->display_info.width_mm = mode->width_mm;
 689                 connector->display_info.height_mm = mode->height_mm;
 690                 /* add scaled modes */
 691                 amdgpu_connector_add_common_modes(encoder, connector);
 692         }
 693
 694         return ret;
 695 }
 696
 697 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 698                                              struct drm_display_mode *mode)
 699 {
 700         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 701
 702         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 703                 return MODE_PANEL;
 704
 705         if (encoder) {
 706                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 707                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 708
 709                 /* AVIVO hardware supports downscaling modes larger than the panel
 710                  * to the panel size, but I'm not sure this is desirable.
 711                  */
 712                 if ((mode->hdisplay > native_mode->hdisplay) ||
 713                     (mode->vdisplay > native_mode->vdisplay))
 714                         return MODE_PANEL;
 715
 716                 /* if scaling is disabled, block non-native modes */
 717                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 718                         if ((mode->hdisplay != native_mode->hdisplay) ||
 719                             (mode->vdisplay != native_mode->vdisplay))
 720                                 return MODE_PANEL;
 721                 }
 722         }
 723
 724         return MODE_OK;
 725 }
 726
 727 static enum drm_connector_status
 728 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 729 {
 730         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 731         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 732         enum drm_connector_status ret = connector_status_disconnected;
 733         int r;
 734
 735         if (!drm_kms_helper_is_poll_worker()) {
 736                 r = pm_runtime_get_sync(connector->dev->dev);
 737                 if (r < 0) {
 738                         pm_runtime_put_autosuspend(connector->dev->dev);
 739                         return connector_status_disconnected;
 740                 }
 741         }
 742
 743         if (encoder) {
 744                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 745                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 746
 747                 /* check if panel is valid */
 748                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 749                         ret = connector_status_connected;
 750
 751         }
 752
 753         /* check for edid as well */
 754         amdgpu_connector_get_edid(connector);
 755         if (amdgpu_connector->edid)
 756                 ret = connector_status_connected;
 757         /* check acpi lid status ??? */
 758
 759         amdgpu_connector_update_scratch_regs(connector, ret);
 760
 761         if (!drm_kms_helper_is_poll_worker()) {
 762                 pm_runtime_mark_last_busy(connector->dev->dev);
 763                 pm_runtime_put_autosuspend(connector->dev->dev);
 764         }
 765
 766         return ret;
 767 }
 768
 769 static void amdgpu_connector_destroy(struct drm_connector *connector)
 770 {
 771         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 772
 773         if (amdgpu_connector->ddc_bus->has_aux)
 774                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 775         amdgpu_connector_free_edid(connector);
 776         kfree(amdgpu_connector->con_priv);
 777         drm_connector_unregister(connector);
 778         drm_connector_cleanup(connector);
 779         kfree(connector);
 780 }
 781
 782 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 783                                               struct drm_property *property,
 784                                               uint64_t value)
 785 {
 786         struct drm_device *dev = connector->dev;
 787         struct amdgpu_encoder *amdgpu_encoder;
 788         enum amdgpu_rmx_type rmx_type;
 789
 790         DRM_DEBUG_KMS("\n");
 791         if (property != dev->mode_config.scaling_mode_property)
 792                 return 0;
 793
 794         if (connector->encoder)
 795                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 796         else {
 797                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 798                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 799         }
 800
 801         switch (value) {
 802         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 803         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 804         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 805         default:
 806         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 807         }
 808         if (amdgpu_encoder->rmx_type == rmx_type)
 809                 return 0;
 810
 811         amdgpu_encoder->rmx_type = rmx_type;
 812
 813         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 814         return 0;
 815 }
 816
 817
 818 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 819         .get_modes = amdgpu_connector_lvds_get_modes,
 820         .mode_valid = amdgpu_connector_lvds_mode_valid,
 821         .best_encoder = amdgpu_connector_best_single_encoder,
 822 };
 823
 824 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 825         .dpms = drm_helper_connector_dpms,
 826         .detect = amdgpu_connector_lvds_detect,
 827         .fill_modes = drm_helper_probe_single_connector_modes,
 828         .destroy = amdgpu_connector_destroy,
 829         .set_property = amdgpu_connector_set_lcd_property,
 830 };
 831
 832 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 833 {
 834         int ret;
 835
 836         amdgpu_connector_get_edid(connector);
 837         ret = amdgpu_connector_ddc_get_modes(connector);
 838
 839         return ret;
 840 }
 841
 842 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 843                                             struct drm_display_mode *mode)
 844 {
 845         struct drm_device *dev = connector->dev;
 846         struct amdgpu_device *adev = dev->dev_private;
 847
 848         /* XXX check mode bandwidth */
 849
 850         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 851                 return MODE_CLOCK_HIGH;
 852
 853         return MODE_OK;
 854 }
 855
 856 static enum drm_connector_status
 857 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 858 {
 859         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 860         struct drm_encoder *encoder;
 861         const struct drm_encoder_helper_funcs *encoder_funcs;
 862         bool dret = false;
 863         enum drm_connector_status ret = connector_status_disconnected;
 864         int r;
 865
 866         if (!drm_kms_helper_is_poll_worker()) {
 867                 r = pm_runtime_get_sync(connector->dev->dev);
 868                 if (r < 0) {
 869                         pm_runtime_put_autosuspend(connector->dev->dev);
 870                         return connector_status_disconnected;
 871                 }
 872         }
 873
 874         encoder = amdgpu_connector_best_single_encoder(connector);
 875         if (!encoder)
 876                 ret = connector_status_disconnected;
 877
 878         if (amdgpu_connector->ddc_bus)
 879                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
 880         if (dret) {
 881                 amdgpu_connector->detected_by_load = false;
 882                 amdgpu_connector_free_edid(connector);
 883                 amdgpu_connector_get_edid(connector);
 884
 885                 if (!amdgpu_connector->edid) {
 886                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 887                                         connector->name);
 888                         ret = connector_status_connected;
 889                 } else {
 890                         amdgpu_connector->use_digital =
 891                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 892
 893                         /* some oems have boards with separate digital and analog connectors
 894                          * with a shared ddc line (often vga + hdmi)
 895                          */
 896                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 897                                 amdgpu_connector_free_edid(connector);
 898                                 ret = connector_status_disconnected;
 899                         } else {
 900                                 ret = connector_status_connected;
 901                         }
 902                 }
 903         } else {
 904
 905                 /* if we aren't forcing don't do destructive polling */
 906                 if (!force) {
 907                         /* only return the previous status if we last
 908                          * detected a monitor via load.
 909                          */
 910                         if (amdgpu_connector->detected_by_load)
 911                                 ret = connector->status;
 912                         goto out;
 913                 }
 914
 915                 if (amdgpu_connector->dac_load_detect && encoder) {
 916                         encoder_funcs = encoder->helper_private;
 917                         ret = encoder_funcs->detect(encoder, connector);
 918                         if (ret != connector_status_disconnected)
 919                                 amdgpu_connector->detected_by_load = true;
 920                 }
 921         }
 922
 923         amdgpu_connector_update_scratch_regs(connector, ret);
 924
 925 out:
 926         if (!drm_kms_helper_is_poll_worker()) {
 927                 pm_runtime_mark_last_busy(connector->dev->dev);
 928                 pm_runtime_put_autosuspend(connector->dev->dev);
 929         }
 930
 931         return ret;
 932 }
 933
 934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 935         .get_modes = amdgpu_connector_vga_get_modes,
 936         .mode_valid = amdgpu_connector_vga_mode_valid,
 937         .best_encoder = amdgpu_connector_best_single_encoder,
 938 };
 939
 940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 941         .dpms = drm_helper_connector_dpms,
 942         .detect = amdgpu_connector_vga_detect,
 943         .fill_modes = drm_helper_probe_single_connector_modes,
 944         .destroy = amdgpu_connector_destroy,
 945         .set_property = amdgpu_connector_set_property,
 946 };
 947
 948 static bool
 949 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 950 {
 951         struct drm_device *dev = connector->dev;
 952         struct amdgpu_device *adev = dev->dev_private;
 953         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 954         enum drm_connector_status status;
 955
 956         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 957                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 958                         status = connector_status_connected;
 959                 else
 960                         status = connector_status_disconnected;
 961                 if (connector->status == status)
 962                         return true;
 963         }
 964
 965         return false;
 966 }
 967
 968 /*
 969  * DVI is complicated
 970  * Do a DDC probe, if DDC probe passes, get the full EDID so
 971  * we can do analog/digital monitor detection at this point.
 972  * If the monitor is an analog monitor or we got no DDC,
 973  * we need to find the DAC encoder object for this connector.
 974  * If we got no DDC, we do load detection on the DAC encoder object.
 975  * If we got analog DDC or load detection passes on the DAC encoder
 976  * we have to check if this analog encoder is shared with anyone else (TV)
 977  * if its shared we have to set the other connector to disconnected.
 978  */
 979 static enum drm_connector_status
 980 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 981 {
 982         struct drm_device *dev = connector->dev;
 983         struct amdgpu_device *adev = dev->dev_private;
 984         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 985         struct drm_encoder *encoder = NULL;
 986         const struct drm_encoder_helper_funcs *encoder_funcs;
 987         int i, r;
 988         enum drm_connector_status ret = connector_status_disconnected;
 989         bool dret = false, broken_edid = false;
 990
 991         if (!drm_kms_helper_is_poll_worker()) {
 992                 r = pm_runtime_get_sync(connector->dev->dev);
 993                 if (r < 0) {
 994                         pm_runtime_put_autosuspend(connector->dev->dev);
 995                         return connector_status_disconnected;
 996                 }
 997         }
 998
 999         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1000                 ret = connector->status;
1001                 goto exit;
1002         }
1003
1004         if (amdgpu_connector->ddc_bus)
1005                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1006         if (dret) {
1007                 amdgpu_connector->detected_by_load = false;
1008                 amdgpu_connector_free_edid(connector);
1009                 amdgpu_connector_get_edid(connector);
1010
1011                 if (!amdgpu_connector->edid) {
1012                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1013                                         connector->name);
1014                         ret = connector_status_connected;
1015                         broken_edid = true; /* defer use_digital to later */
1016                 } else {
1017                         amdgpu_connector->use_digital =
1018                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1019
1020                         /* some oems have boards with separate digital and analog connectors
1021                          * with a shared ddc line (often vga + hdmi)
1022                          */
1023                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1024                                 amdgpu_connector_free_edid(connector);
1025                                 ret = connector_status_disconnected;
1026                         } else {
1027                                 ret = connector_status_connected;
1028                         }
1029
1030                         /* This gets complicated.  We have boards with VGA + HDMI with a
1031                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1032                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1033                          * you don't really know what's connected to which port as both are digital.
1034                          */
1035                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1036                                 struct drm_connector *list_connector;
1037                                 struct amdgpu_connector *list_amdgpu_connector;
1038                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1039                                         if (connector == list_connector)
1040                                                 continue;
1041                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1042                                         if (list_amdgpu_connector->shared_ddc &&
1043                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1044                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1045                                                 /* cases where both connectors are digital */
1046                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1047                                                         /* hpd is our only option in this case */
1048                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1049                                                                 amdgpu_connector_free_edid(connector);
1050                                                                 ret = connector_status_disconnected;
1051                                                         }
1052                                                 }
1053                                         }
1054                                 }
1055                         }
1056                 }
1057         }
1058
1059         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1060                 goto out;
1061
1062         /* DVI-D and HDMI-A are digital only */
1063         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1064             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1065                 goto out;
1066
1067         /* if we aren't forcing don't do destructive polling */
1068         if (!force) {
1069                 /* only return the previous status if we last
1070                  * detected a monitor via load.
1071                  */
1072                 if (amdgpu_connector->detected_by_load)
1073                         ret = connector->status;
1074                 goto out;
1075         }
1076
1077         /* find analog encoder */
1078         if (amdgpu_connector->dac_load_detect) {
1079                 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1080                         if (connector->encoder_ids[i] == 0)
1081                                 break;
1082
1083                         encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1084                         if (!encoder)
1085                                 continue;
1086
1087                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1088                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1089                                 continue;
1090
1091                         encoder_funcs = encoder->helper_private;
1092                         if (encoder_funcs->detect) {
1093                                 if (!broken_edid) {
1094                                         if (ret != connector_status_connected) {
1095                                                 /* deal with analog monitors without DDC */
1096                                                 ret = encoder_funcs->detect(encoder, connector);
1097                                                 if (ret == connector_status_connected) {
1098                                                         amdgpu_connector->use_digital = false;
1099                                                 }
1100                                                 if (ret != connector_status_disconnected)
1101                                                         amdgpu_connector->detected_by_load = true;
1102                                         }
1103                                 } else {
1104                                         enum drm_connector_status lret;
1105                                         /* assume digital unless load detected otherwise */
1106                                         amdgpu_connector->use_digital = true;
1107                                         lret = encoder_funcs->detect(encoder, connector);
1108                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1109                                         if (lret == connector_status_connected)
1110                                                 amdgpu_connector->use_digital = false;
1111                                 }
1112                                 break;
1113                         }
1114                 }
1115         }
1116
1117 out:
1118         /* updated in get modes as well since we need to know if it's analog or digital */
1119         amdgpu_connector_update_scratch_regs(connector, ret);
1120
1121 exit:
1122         if (!drm_kms_helper_is_poll_worker()) {
1123                 pm_runtime_mark_last_busy(connector->dev->dev);
1124                 pm_runtime_put_autosuspend(connector->dev->dev);
1125         }
1126
1127         return ret;
1128 }
1129
1130 /* okay need to be smart in here about which encoder to pick */
1131 static struct drm_encoder *
1132 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1133 {
1134         int enc_id = connector->encoder_ids[0];
1135         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1136         struct drm_encoder *encoder;
1137         int i;
1138         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1139                 if (connector->encoder_ids[i] == 0)
1140                         break;
1141
1142                 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
1143                 if (!encoder)
1144                         continue;
1145
1146                 if (amdgpu_connector->use_digital == true) {
1147                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1148                                 return encoder;
1149                 } else {
1150                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1151                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1152                                 return encoder;
1153                 }
1154         }
1155
1156         /* see if we have a default encoder  TODO */
1157
1158         /* then check use digitial */
1159         /* pick the first one */
1160         if (enc_id)
1161                 return drm_encoder_find(connector->dev, enc_id);
1162         return NULL;
1163 }
1164
1165 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1166 {
1167         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1168         if (connector->force == DRM_FORCE_ON)
1169                 amdgpu_connector->use_digital = false;
1170         if (connector->force == DRM_FORCE_ON_DIGITAL)
1171                 amdgpu_connector->use_digital = true;
1172 }
1173
1174 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1175                                             struct drm_display_mode *mode)
1176 {
1177         struct drm_device *dev = connector->dev;
1178         struct amdgpu_device *adev = dev->dev_private;
1179         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1180
1181         /* XXX check mode bandwidth */
1182
1183         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1184                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1185                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1186                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1187                         return MODE_OK;
1188                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1189                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1190                         if (mode->clock > 340000)
1191                                 return MODE_CLOCK_HIGH;
1192                         else
1193                                 return MODE_OK;
1194                 } else {
1195                         return MODE_CLOCK_HIGH;
1196                 }
1197         }
1198
1199         /* check against the max pixel clock */
1200         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1201                 return MODE_CLOCK_HIGH;
1202
1203         return MODE_OK;
1204 }
1205
1206 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1207         .get_modes = amdgpu_connector_vga_get_modes,
1208         .mode_valid = amdgpu_connector_dvi_mode_valid,
1209         .best_encoder = amdgpu_connector_dvi_encoder,
1210 };
1211
1212 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1213         .dpms = drm_helper_connector_dpms,
1214         .detect = amdgpu_connector_dvi_detect,
1215         .fill_modes = drm_helper_probe_single_connector_modes,
1216         .set_property = amdgpu_connector_set_property,
1217         .destroy = amdgpu_connector_destroy,
1218         .force = amdgpu_connector_dvi_force,
1219 };
1220
1221 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1222 {
1223         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1224         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1225         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1226         int ret;
1227
1228         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1229             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1230                 struct drm_display_mode *mode;
1231
1232                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1233                         if (!amdgpu_dig_connector->edp_on)
1234                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1235                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1236                         amdgpu_connector_get_edid(connector);
1237                         ret = amdgpu_connector_ddc_get_modes(connector);
1238                         if (!amdgpu_dig_connector->edp_on)
1239                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1240                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1241                 } else {
1242                         /* need to setup ddc on the bridge */
1243                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1244                             ENCODER_OBJECT_ID_NONE) {
1245                                 if (encoder)
1246                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1247                         }
1248                         amdgpu_connector_get_edid(connector);
1249                         ret = amdgpu_connector_ddc_get_modes(connector);
1250                 }
1251
1252                 if (ret > 0) {
1253                         if (encoder) {
1254                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1255                                 /* add scaled modes */
1256                                 amdgpu_connector_add_common_modes(encoder, connector);
1257                         }
1258                         return ret;
1259                 }
1260
1261                 if (!encoder)
1262                         return 0;
1263
1264                 /* we have no EDID modes */
1265                 mode = amdgpu_connector_lcd_native_mode(encoder);
1266                 if (mode) {
1267                         ret = 1;
1268                         drm_mode_probed_add(connector, mode);
1269                         /* add the width/height from vbios tables if available */
1270                         connector->display_info.width_mm = mode->width_mm;
1271                         connector->display_info.height_mm = mode->height_mm;
1272                         /* add scaled modes */
1273                         amdgpu_connector_add_common_modes(encoder, connector);
1274                 }
1275         } else {
1276                 /* need to setup ddc on the bridge */
1277                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1278                         ENCODER_OBJECT_ID_NONE) {
1279                         if (encoder)
1280                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1281                 }
1282                 amdgpu_connector_get_edid(connector);
1283                 ret = amdgpu_connector_ddc_get_modes(connector);
1284
1285                 amdgpu_get_native_mode(connector);
1286         }
1287
1288         return ret;
1289 }
1290
1291 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1292 {
1293         struct drm_encoder *encoder;
1294         struct amdgpu_encoder *amdgpu_encoder;
1295         int i;
1296
1297         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1298                 if (connector->encoder_ids[i] == 0)
1299                         break;
1300
1301                 encoder = drm_encoder_find(connector->dev,
1302                                         connector->encoder_ids[i]);
1303                 if (!encoder)
1304                         continue;
1305
1306                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1307
1308                 switch (amdgpu_encoder->encoder_id) {
1309                 case ENCODER_OBJECT_ID_TRAVIS:
1310                 case ENCODER_OBJECT_ID_NUTMEG:
1311                         return amdgpu_encoder->encoder_id;
1312                 default:
1313                         break;
1314                 }
1315         }
1316
1317         return ENCODER_OBJECT_ID_NONE;
1318 }
1319
1320 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1321 {
1322         struct drm_encoder *encoder;
1323         struct amdgpu_encoder *amdgpu_encoder;
1324         int i;
1325         bool found = false;
1326
1327         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1328                 if (connector->encoder_ids[i] == 0)
1329                         break;
1330                 encoder = drm_encoder_find(connector->dev,
1331                                         connector->encoder_ids[i]);
1332                 if (!encoder)
1333                         continue;
1334
1335                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1336                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1337                         found = true;
1338         }
1339
1340         return found;
1341 }
1342
1343 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1344 {
1345         struct drm_device *dev = connector->dev;
1346         struct amdgpu_device *adev = dev->dev_private;
1347
1348         if ((adev->clock.default_dispclk >= 53900) &&
1349             amdgpu_connector_encoder_is_hbr2(connector)) {
1350                 return true;
1351         }
1352
1353         return false;
1354 }
1355
1356 static enum drm_connector_status
1357 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1358 {
1359         struct drm_device *dev = connector->dev;
1360         struct amdgpu_device *adev = dev->dev_private;
1361         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1362         enum drm_connector_status ret = connector_status_disconnected;
1363         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1364         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1365         int r;
1366
1367         if (!drm_kms_helper_is_poll_worker()) {
1368                 r = pm_runtime_get_sync(connector->dev->dev);
1369                 if (r < 0) {
1370                         pm_runtime_put_autosuspend(connector->dev->dev);
1371                         return connector_status_disconnected;
1372                 }
1373         }
1374
1375         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1376                 ret = connector->status;
1377                 goto out;
1378         }
1379
1380         amdgpu_connector_free_edid(connector);
1381
1382         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1383             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1384                 if (encoder) {
1385                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1386                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1387
1388                         /* check if panel is valid */
1389                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1390                                 ret = connector_status_connected;
1391                 }
1392                 /* eDP is always DP */
1393                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1394                 if (!amdgpu_dig_connector->edp_on)
1395                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1396                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1397                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1398                         ret = connector_status_connected;
1399                 if (!amdgpu_dig_connector->edp_on)
1400                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1401                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1402         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1403                    ENCODER_OBJECT_ID_NONE) {
1404                 /* DP bridges are always DP */
1405                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1406                 /* get the DPCD from the bridge */
1407                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1408
1409                 if (encoder) {
1410                         /* setup ddc on the bridge */
1411                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1412                         /* bridge chips are always aux */
1413                         if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1414                                 ret = connector_status_connected;
1415                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1416                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1417                                 ret = encoder_funcs->detect(encoder, connector);
1418                         }
1419                 }
1420         } else {
1421                 amdgpu_dig_connector->dp_sink_type =
1422                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1423                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1424                         ret = connector_status_connected;
1425                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1426                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1427                 } else {
1428                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1429                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1430                                         ret = connector_status_connected;
1431                         } else {
1432                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1433                                 if (amdgpu_ddc_probe(amdgpu_connector, false))
1434                                         ret = connector_status_connected;
1435                         }
1436                 }
1437         }
1438
1439         amdgpu_connector_update_scratch_regs(connector, ret);
1440 out:
1441         if (!drm_kms_helper_is_poll_worker()) {
1442                 pm_runtime_mark_last_busy(connector->dev->dev);
1443                 pm_runtime_put_autosuspend(connector->dev->dev);
1444         }
1445
1446         return ret;
1447 }
1448
1449 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1450                                            struct drm_display_mode *mode)
1451 {
1452         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1453         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1454
1455         /* XXX check mode bandwidth */
1456
1457         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1458             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1459                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1460
1461                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1462                         return MODE_PANEL;
1463
1464                 if (encoder) {
1465                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1466                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1467
1468                         /* AVIVO hardware supports downscaling modes larger than the panel
1469                          * to the panel size, but I'm not sure this is desirable.
1470                          */
1471                         if ((mode->hdisplay > native_mode->hdisplay) ||
1472                             (mode->vdisplay > native_mode->vdisplay))
1473                                 return MODE_PANEL;
1474
1475                         /* if scaling is disabled, block non-native modes */
1476                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1477                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1478                                     (mode->vdisplay != native_mode->vdisplay))
1479                                         return MODE_PANEL;
1480                         }
1481                 }
1482                 return MODE_OK;
1483         } else {
1484                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1485                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1486                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1487                 } else {
1488                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1489                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1490                                 if (mode->clock > 340000)
1491                                         return MODE_CLOCK_HIGH;
1492                         } else {
1493                                 if (mode->clock > 165000)
1494                                         return MODE_CLOCK_HIGH;
1495                         }
1496                 }
1497         }
1498
1499         return MODE_OK;
1500 }
1501
1502 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1503         .get_modes = amdgpu_connector_dp_get_modes,
1504         .mode_valid = amdgpu_connector_dp_mode_valid,
1505         .best_encoder = amdgpu_connector_dvi_encoder,
1506 };
1507
1508 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1509         .dpms = drm_helper_connector_dpms,
1510         .detect = amdgpu_connector_dp_detect,
1511         .fill_modes = drm_helper_probe_single_connector_modes,
1512         .set_property = amdgpu_connector_set_property,
1513         .destroy = amdgpu_connector_destroy,
1514         .force = amdgpu_connector_dvi_force,
1515 };
1516
1517 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1518         .dpms = drm_helper_connector_dpms,
1519         .detect = amdgpu_connector_dp_detect,
1520         .fill_modes = drm_helper_probe_single_connector_modes,
1521         .set_property = amdgpu_connector_set_lcd_property,
1522         .destroy = amdgpu_connector_destroy,
1523         .force = amdgpu_connector_dvi_force,
1524 };
1525
1526 void
1527 amdgpu_connector_add(struct amdgpu_device *adev,
1528                       uint32_t connector_id,
1529                       uint32_t supported_device,
1530                       int connector_type,
1531                       struct amdgpu_i2c_bus_rec *i2c_bus,
1532                       uint16_t connector_object_id,
1533                       struct amdgpu_hpd *hpd,
1534                       struct amdgpu_router *router)
1535 {
1536         struct drm_device *dev = adev->ddev;
1537         struct drm_connector *connector;
1538         struct amdgpu_connector *amdgpu_connector;
1539         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1540         struct drm_encoder *encoder;
1541         struct amdgpu_encoder *amdgpu_encoder;
1542         uint32_t subpixel_order = SubPixelNone;
1543         bool shared_ddc = false;
1544         bool is_dp_bridge = false;
1545         bool has_aux = false;
1546
1547         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1548                 return;
1549
1550         /* see if we already added it */
1551         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1552                 amdgpu_connector = to_amdgpu_connector(connector);
1553                 if (amdgpu_connector->connector_id == connector_id) {
1554                         amdgpu_connector->devices |= supported_device;
1555                         return;
1556                 }
1557                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1558                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1559                                 amdgpu_connector->shared_ddc = true;
1560                                 shared_ddc = true;
1561                         }
1562                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1563                             (amdgpu_connector->router.router_id == router->router_id)) {
1564                                 amdgpu_connector->shared_ddc = false;
1565                                 shared_ddc = false;
1566                         }
1567                 }
1568         }
1569
1570         /* check if it's a dp bridge */
1571         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1572                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1573                 if (amdgpu_encoder->devices & supported_device) {
1574                         switch (amdgpu_encoder->encoder_id) {
1575                         case ENCODER_OBJECT_ID_TRAVIS:
1576                         case ENCODER_OBJECT_ID_NUTMEG:
1577                                 is_dp_bridge = true;
1578                                 break;
1579                         default:
1580                                 break;
1581                         }
1582                 }
1583         }
1584
1585         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1586         if (!amdgpu_connector)
1587                 return;
1588
1589         connector = &amdgpu_connector->base;
1590
1591         amdgpu_connector->connector_id = connector_id;
1592         amdgpu_connector->devices = supported_device;
1593         amdgpu_connector->shared_ddc = shared_ddc;
1594         amdgpu_connector->connector_object_id = connector_object_id;
1595         amdgpu_connector->hpd = *hpd;
1596
1597         amdgpu_connector->router = *router;
1598         if (router->ddc_valid || router->cd_valid) {
1599                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1600                 if (!amdgpu_connector->router_bus)
1601                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1602         }
1603
1604         if (is_dp_bridge) {
1605                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1606                 if (!amdgpu_dig_connector)
1607                         goto failed;
1608                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1609                 if (i2c_bus->valid) {
1610                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1611                         if (amdgpu_connector->ddc_bus)
1612                                 has_aux = true;
1613                         else
1614                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1615                 }
1616                 switch (connector_type) {
1617                 case DRM_MODE_CONNECTOR_VGA:
1618                 case DRM_MODE_CONNECTOR_DVIA:
1619                 default:
1620                         drm_connector_init(dev, &amdgpu_connector->base,
1621                                            &amdgpu_connector_dp_funcs, connector_type);
1622                         drm_connector_helper_add(&amdgpu_connector->base,
1623                                                  &amdgpu_connector_dp_helper_funcs);
1624                         connector->interlace_allowed = true;
1625                         connector->doublescan_allowed = true;
1626                         amdgpu_connector->dac_load_detect = true;
1627                         drm_object_attach_property(&amdgpu_connector->base.base,
1628                                                       adev->mode_info.load_detect_property,
1629                                                       1);
1630                         drm_object_attach_property(&amdgpu_connector->base.base,
1631                                                    dev->mode_config.scaling_mode_property,
1632                                                    DRM_MODE_SCALE_NONE);
1633                         break;
1634                 case DRM_MODE_CONNECTOR_DVII:
1635                 case DRM_MODE_CONNECTOR_DVID:
1636                 case DRM_MODE_CONNECTOR_HDMIA:
1637                 case DRM_MODE_CONNECTOR_HDMIB:
1638                 case DRM_MODE_CONNECTOR_DisplayPort:
1639                         drm_connector_init(dev, &amdgpu_connector->base,
1640                                            &amdgpu_connector_dp_funcs, connector_type);
1641                         drm_connector_helper_add(&amdgpu_connector->base,
1642                                                  &amdgpu_connector_dp_helper_funcs);
1643                         drm_object_attach_property(&amdgpu_connector->base.base,
1644                                                       adev->mode_info.underscan_property,
1645                                                       UNDERSCAN_OFF);
1646                         drm_object_attach_property(&amdgpu_connector->base.base,
1647                                                       adev->mode_info.underscan_hborder_property,
1648                                                       0);
1649                         drm_object_attach_property(&amdgpu_connector->base.base,
1650                                                       adev->mode_info.underscan_vborder_property,
1651                                                       0);
1652
1653                         drm_object_attach_property(&amdgpu_connector->base.base,
1654                                                    dev->mode_config.scaling_mode_property,
1655                                                    DRM_MODE_SCALE_NONE);
1656
1657                         drm_object_attach_property(&amdgpu_connector->base.base,
1658                                                    adev->mode_info.dither_property,
1659                                                    AMDGPU_FMT_DITHER_DISABLE);
1660
1661                         if (amdgpu_audio != 0)
1662                                 drm_object_attach_property(&amdgpu_connector->base.base,
1663                                                            adev->mode_info.audio_property,
1664                                                            AMDGPU_AUDIO_AUTO);
1665
1666                         subpixel_order = SubPixelHorizontalRGB;
1667                         connector->interlace_allowed = true;
1668                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1669                                 connector->doublescan_allowed = true;
1670                         else
1671                                 connector->doublescan_allowed = false;
1672                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1673                                 amdgpu_connector->dac_load_detect = true;
1674                                 drm_object_attach_property(&amdgpu_connector->base.base,
1675                                                               adev->mode_info.load_detect_property,
1676                                                               1);
1677                         }
1678                         break;
1679                 case DRM_MODE_CONNECTOR_LVDS:
1680                 case DRM_MODE_CONNECTOR_eDP:
1681                         drm_connector_init(dev, &amdgpu_connector->base,
1682                                            &amdgpu_connector_edp_funcs, connector_type);
1683                         drm_connector_helper_add(&amdgpu_connector->base,
1684                                                  &amdgpu_connector_dp_helper_funcs);
1685                         drm_object_attach_property(&amdgpu_connector->base.base,
1686                                                       dev->mode_config.scaling_mode_property,
1687                                                       DRM_MODE_SCALE_FULLSCREEN);
1688                         subpixel_order = SubPixelHorizontalRGB;
1689                         connector->interlace_allowed = false;
1690                         connector->doublescan_allowed = false;
1691                         break;
1692                 }
1693         } else {
1694                 switch (connector_type) {
1695                 case DRM_MODE_CONNECTOR_VGA:
1696                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1697                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1698                         if (i2c_bus->valid) {
1699                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1700                                 if (!amdgpu_connector->ddc_bus)
1701                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1702                         }
1703                         amdgpu_connector->dac_load_detect = true;
1704                         drm_object_attach_property(&amdgpu_connector->base.base,
1705                                                       adev->mode_info.load_detect_property,
1706                                                       1);
1707                         drm_object_attach_property(&amdgpu_connector->base.base,
1708                                                    dev->mode_config.scaling_mode_property,
1709                                                    DRM_MODE_SCALE_NONE);
1710                         /* no HPD on analog connectors */
1711                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1712                         connector->interlace_allowed = true;
1713                         connector->doublescan_allowed = true;
1714                         break;
1715                 case DRM_MODE_CONNECTOR_DVIA:
1716                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1717                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1718                         if (i2c_bus->valid) {
1719                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1720                                 if (!amdgpu_connector->ddc_bus)
1721                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1722                         }
1723                         amdgpu_connector->dac_load_detect = true;
1724                         drm_object_attach_property(&amdgpu_connector->base.base,
1725                                                       adev->mode_info.load_detect_property,
1726                                                       1);
1727                         drm_object_attach_property(&amdgpu_connector->base.base,
1728                                                    dev->mode_config.scaling_mode_property,
1729                                                    DRM_MODE_SCALE_NONE);
1730                         /* no HPD on analog connectors */
1731                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1732                         connector->interlace_allowed = true;
1733                         connector->doublescan_allowed = true;
1734                         break;
1735                 case DRM_MODE_CONNECTOR_DVII:
1736                 case DRM_MODE_CONNECTOR_DVID:
1737                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1738                         if (!amdgpu_dig_connector)
1739                                 goto failed;
1740                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1741                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1742                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1743                         if (i2c_bus->valid) {
1744                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1745                                 if (!amdgpu_connector->ddc_bus)
1746                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1747                         }
1748                         subpixel_order = SubPixelHorizontalRGB;
1749                         drm_object_attach_property(&amdgpu_connector->base.base,
1750                                                       adev->mode_info.coherent_mode_property,
1751                                                       1);
1752                         drm_object_attach_property(&amdgpu_connector->base.base,
1753                                                    adev->mode_info.underscan_property,
1754                                                    UNDERSCAN_OFF);
1755                         drm_object_attach_property(&amdgpu_connector->base.base,
1756                                                    adev->mode_info.underscan_hborder_property,
1757                                                    0);
1758                         drm_object_attach_property(&amdgpu_connector->base.base,
1759                                                    adev->mode_info.underscan_vborder_property,
1760                                                    0);
1761                         drm_object_attach_property(&amdgpu_connector->base.base,
1762                                                    dev->mode_config.scaling_mode_property,
1763                                                    DRM_MODE_SCALE_NONE);
1764
1765                         if (amdgpu_audio != 0) {
1766                                 drm_object_attach_property(&amdgpu_connector->base.base,
1767                                                            adev->mode_info.audio_property,
1768                                                            AMDGPU_AUDIO_AUTO);
1769                         }
1770                         drm_object_attach_property(&amdgpu_connector->base.base,
1771                                                    adev->mode_info.dither_property,
1772                                                    AMDGPU_FMT_DITHER_DISABLE);
1773                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1774                                 amdgpu_connector->dac_load_detect = true;
1775                                 drm_object_attach_property(&amdgpu_connector->base.base,
1776                                                            adev->mode_info.load_detect_property,
1777                                                            1);
1778                         }
1779                         connector->interlace_allowed = true;
1780                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1781                                 connector->doublescan_allowed = true;
1782                         else
1783                                 connector->doublescan_allowed = false;
1784                         break;
1785                 case DRM_MODE_CONNECTOR_HDMIA:
1786                 case DRM_MODE_CONNECTOR_HDMIB:
1787                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1788                         if (!amdgpu_dig_connector)
1789                                 goto failed;
1790                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1791                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1792                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1793                         if (i2c_bus->valid) {
1794                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1795                                 if (!amdgpu_connector->ddc_bus)
1796                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1797                         }
1798                         drm_object_attach_property(&amdgpu_connector->base.base,
1799                                                       adev->mode_info.coherent_mode_property,
1800                                                       1);
1801                         drm_object_attach_property(&amdgpu_connector->base.base,
1802                                                    adev->mode_info.underscan_property,
1803                                                    UNDERSCAN_OFF);
1804                         drm_object_attach_property(&amdgpu_connector->base.base,
1805                                                    adev->mode_info.underscan_hborder_property,
1806                                                    0);
1807                         drm_object_attach_property(&amdgpu_connector->base.base,
1808                                                    adev->mode_info.underscan_vborder_property,
1809                                                    0);
1810                         drm_object_attach_property(&amdgpu_connector->base.base,
1811                                                    dev->mode_config.scaling_mode_property,
1812                                                    DRM_MODE_SCALE_NONE);
1813                         if (amdgpu_audio != 0) {
1814                                 drm_object_attach_property(&amdgpu_connector->base.base,
1815                                                            adev->mode_info.audio_property,
1816                                                            AMDGPU_AUDIO_AUTO);
1817                         }
1818                         drm_object_attach_property(&amdgpu_connector->base.base,
1819                                                    adev->mode_info.dither_property,
1820                                                    AMDGPU_FMT_DITHER_DISABLE);
1821                         subpixel_order = SubPixelHorizontalRGB;
1822                         connector->interlace_allowed = true;
1823                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1824                                 connector->doublescan_allowed = true;
1825                         else
1826                                 connector->doublescan_allowed = false;
1827                         break;
1828                 case DRM_MODE_CONNECTOR_DisplayPort:
1829                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1830                         if (!amdgpu_dig_connector)
1831                                 goto failed;
1832                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1833                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1834                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1835                         if (i2c_bus->valid) {
1836                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1837                                 if (amdgpu_connector->ddc_bus)
1838                                         has_aux = true;
1839                                 else
1840                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1841                         }
1842                         subpixel_order = SubPixelHorizontalRGB;
1843                         drm_object_attach_property(&amdgpu_connector->base.base,
1844                                                       adev->mode_info.coherent_mode_property,
1845                                                       1);
1846                         drm_object_attach_property(&amdgpu_connector->base.base,
1847                                                    adev->mode_info.underscan_property,
1848                                                    UNDERSCAN_OFF);
1849                         drm_object_attach_property(&amdgpu_connector->base.base,
1850                                                    adev->mode_info.underscan_hborder_property,
1851                                                    0);
1852                         drm_object_attach_property(&amdgpu_connector->base.base,
1853                                                    adev->mode_info.underscan_vborder_property,
1854                                                    0);
1855                         drm_object_attach_property(&amdgpu_connector->base.base,
1856                                                    dev->mode_config.scaling_mode_property,
1857                                                    DRM_MODE_SCALE_NONE);
1858                         if (amdgpu_audio != 0) {
1859                                 drm_object_attach_property(&amdgpu_connector->base.base,
1860                                                            adev->mode_info.audio_property,
1861                                                            AMDGPU_AUDIO_AUTO);
1862                         }
1863                         drm_object_attach_property(&amdgpu_connector->base.base,
1864                                                    adev->mode_info.dither_property,
1865                                                    AMDGPU_FMT_DITHER_DISABLE);
1866                         connector->interlace_allowed = true;
1867                         /* in theory with a DP to VGA converter... */
1868                         connector->doublescan_allowed = false;
1869                         break;
1870                 case DRM_MODE_CONNECTOR_eDP:
1871                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1872                         if (!amdgpu_dig_connector)
1873                                 goto failed;
1874                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1875                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1876                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1877                         if (i2c_bus->valid) {
1878                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1879                                 if (amdgpu_connector->ddc_bus)
1880                                         has_aux = true;
1881                                 else
1882                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1883                         }
1884                         drm_object_attach_property(&amdgpu_connector->base.base,
1885                                                       dev->mode_config.scaling_mode_property,
1886                                                       DRM_MODE_SCALE_FULLSCREEN);
1887                         subpixel_order = SubPixelHorizontalRGB;
1888                         connector->interlace_allowed = false;
1889                         connector->doublescan_allowed = false;
1890                         break;
1891                 case DRM_MODE_CONNECTOR_LVDS:
1892                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1893                         if (!amdgpu_dig_connector)
1894                                 goto failed;
1895                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1896                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1897                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1898                         if (i2c_bus->valid) {
1899                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1900                                 if (!amdgpu_connector->ddc_bus)
1901                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1902                         }
1903                         drm_object_attach_property(&amdgpu_connector->base.base,
1904                                                       dev->mode_config.scaling_mode_property,
1905                                                       DRM_MODE_SCALE_FULLSCREEN);
1906                         subpixel_order = SubPixelHorizontalRGB;
1907                         connector->interlace_allowed = false;
1908                         connector->doublescan_allowed = false;
1909                         break;
1910                 }
1911         }
1912
1913         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1914                 if (i2c_bus->valid) {
1915                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1916                                             DRM_CONNECTOR_POLL_DISCONNECT;
1917                 }
1918         } else
1919                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1920
1921         connector->display_info.subpixel_order = subpixel_order;
1922         drm_connector_register(connector);
1923
1924         if (has_aux)
1925                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1926
1927         return;
1928
1929 failed:
1930         drm_connector_cleanup(connector);
1931         kfree(connector);
1932 }