drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev,
 238                                          uint32_t supported_device,
 239                                          int *connector_type,
 240                                          struct amdgpu_i2c_bus_rec *i2c_bus,
 241                                          uint16_t *line_mux,
 242                                          struct amdgpu_hpd *hpd)
 243 {
 244         return true;
 245 }
 246
 247 static const int object_connector_convert[] = {
 248         DRM_MODE_CONNECTOR_Unknown,
 249         DRM_MODE_CONNECTOR_DVII,
 250         DRM_MODE_CONNECTOR_DVII,
 251         DRM_MODE_CONNECTOR_DVID,
 252         DRM_MODE_CONNECTOR_DVID,
 253         DRM_MODE_CONNECTOR_VGA,
 254         DRM_MODE_CONNECTOR_Composite,
 255         DRM_MODE_CONNECTOR_SVIDEO,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_Unknown,
 258         DRM_MODE_CONNECTOR_9PinDIN,
 259         DRM_MODE_CONNECTOR_Unknown,
 260         DRM_MODE_CONNECTOR_HDMIA,
 261         DRM_MODE_CONNECTOR_HDMIB,
 262         DRM_MODE_CONNECTOR_LVDS,
 263         DRM_MODE_CONNECTOR_9PinDIN,
 264         DRM_MODE_CONNECTOR_Unknown,
 265         DRM_MODE_CONNECTOR_Unknown,
 266         DRM_MODE_CONNECTOR_Unknown,
 267         DRM_MODE_CONNECTOR_DisplayPort,
 268         DRM_MODE_CONNECTOR_eDP,
 269         DRM_MODE_CONNECTOR_Unknown
 270 };
 271
 272 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 273 {
 274         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 275         struct atom_context *ctx = mode_info->atom_context;
 276         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 277         u16 size, data_offset;
 278         u8 frev, crev;
 279         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 280         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 281         ATOM_OBJECT_TABLE *router_obj;
 282         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 283         ATOM_OBJECT_HEADER *obj_header;
 284         int i, j, k, path_size, device_support;
 285         int connector_type;
 286         u16 conn_id, connector_object_id;
 287         struct amdgpu_i2c_bus_rec ddc_bus;
 288         struct amdgpu_router router;
 289         struct amdgpu_gpio_rec gpio;
 290         struct amdgpu_hpd hpd;
 291
 292         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 293                 return false;
 294
 295         if (crev < 2)
 296                 return false;
 297
 298         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 299         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 300             (ctx->bios + data_offset +
 301              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 302         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 303             (ctx->bios + data_offset +
 304              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 305         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 306             (ctx->bios + data_offset +
 307              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 308         router_obj = (ATOM_OBJECT_TABLE *)
 309                 (ctx->bios + data_offset +
 310                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 311         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 312
 313         path_size = 0;
 314         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 315                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 316                 ATOM_DISPLAY_OBJECT_PATH *path;
 317                 addr += path_size;
 318                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 319                 path_size += le16_to_cpu(path->usSize);
 320
 321                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 322                         uint8_t con_obj_id =
 323                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 324                             >> OBJECT_ID_SHIFT;
 325
 326                         /* Skip TV/CV support */
 327                         if ((le16_to_cpu(path->usDeviceTag) ==
 328                              ATOM_DEVICE_TV1_SUPPORT) ||
 329                             (le16_to_cpu(path->usDeviceTag) ==
 330                              ATOM_DEVICE_CV_SUPPORT))
 331                                 continue;
 332
 333                         if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 334                                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 335                                           con_obj_id, le16_to_cpu(path->usDeviceTag));
 336                                 continue;
 337                         }
 338
 339                         connector_type =
 340                                 object_connector_convert[con_obj_id];
 341                         connector_object_id = con_obj_id;
 342
 343                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 344                                 continue;
 345
 346                         router.ddc_valid = false;
 347                         router.cd_valid = false;
 348                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 349                                 uint8_t grph_obj_type =
 350                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 351                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 352
 353                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 354                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 355                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 356                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 357                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 358                                                                 (ctx->bios + data_offset +
 359                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 360                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 361                                                         u16 caps = 0;
 362
 363                                                         while (record->ucRecordSize > 0 &&
 364                                                                record->ucRecordType > 0 &&
 365                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 366                                                                 switch (record->ucRecordType) {
 367                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 368                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 369                                                                                 record;
 370                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 371                                                                         break;
 372                                                                 }
 373                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 374                                                                         ((char *)record + record->ucRecordSize);
 375                                                         }
 376                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 377                                                                                     le16_to_cpu(path->usDeviceTag),
 378                                                                                     caps);
 379                                                 }
 380                                         }
 381                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 382                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 383                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 384                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 385                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 386                                                                 (ctx->bios + data_offset +
 387                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 388                                                         ATOM_I2C_RECORD *i2c_record;
 389                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 390                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 391                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 392                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 393                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 394                                                                 (ctx->bios + data_offset +
 395                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 396                                                         u8 *num_dst_objs = (u8 *)
 397                                                                 ((u8 *)router_src_dst_table + 1 +
 398                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 399                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 400                                                         int enum_id;
 401
 402                                                         router.router_id = router_obj_id;
 403                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 404                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 405                                                                     le16_to_cpu(dst_objs[enum_id]))
 406                                                                         break;
 407                                                         }
 408
 409                                                         while (record->ucRecordSize > 0 &&
 410                                                                record->ucRecordType > 0 &&
 411                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 412                                                                 switch (record->ucRecordType) {
 413                                                                 case ATOM_I2C_RECORD_TYPE:
 414                                                                         i2c_record =
 415                                                                                 (ATOM_I2C_RECORD *)
 416                                                                                 record;
 417                                                                         i2c_config =
 418                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 419                                                                                 &i2c_record->sucI2cId;
 420                                                                         router.i2c_info =
 421                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 422                                                                                                        i2c_config->
 423                                                                                                        ucAccess);
 424                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 425                                                                         break;
 426                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 427                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 428                                                                                 record;
 429                                                                         router.ddc_valid = true;
 430                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 431                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 432                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 433                                                                         break;
 434                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 435                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 436                                                                                 record;
 437                                                                         router.cd_valid = true;
 438                                                                         router.cd_mux_type = cd_path->ucMuxType;
 439                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 440                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 441                                                                         break;
 442                                                                 }
 443                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 444                                                                         ((char *)record + record->ucRecordSize);
 445                                                         }
 446                                                 }
 447                                         }
 448                                 }
 449                         }
 450
 451                         /* look up gpio for ddc, hpd */
 452                         ddc_bus.valid = false;
 453                         hpd.hpd = AMDGPU_HPD_NONE;
 454                         if ((le16_to_cpu(path->usDeviceTag) &
 455                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 456                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 457                                         if (le16_to_cpu(path->usConnObjectId) ==
 458                                             le16_to_cpu(con_obj->asObjects[j].
 459                                                         usObjectID)) {
 460                                                 ATOM_COMMON_RECORD_HEADER
 461                                                     *record =
 462                                                     (ATOM_COMMON_RECORD_HEADER
 463                                                      *)
 464                                                     (ctx->bios + data_offset +
 465                                                      le16_to_cpu(con_obj->
 466                                                                  asObjects[j].
 467                                                                  usRecordOffset));
 468                                                 ATOM_I2C_RECORD *i2c_record;
 469                                                 ATOM_HPD_INT_RECORD *hpd_record;
 470                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 471
 472                                                 while (record->ucRecordSize > 0 &&
 473                                                        record->ucRecordType > 0 &&
 474                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 475                                                         switch (record->ucRecordType) {
 476                                                         case ATOM_I2C_RECORD_TYPE:
 477                                                                 i2c_record =
 478                                                                     (ATOM_I2C_RECORD *)
 479                                                                         record;
 480                                                                 i2c_config =
 481                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 482                                                                         &i2c_record->sucI2cId;
 483                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 484                                                                                                  i2c_config->
 485                                                                                                  ucAccess);
 486                                                                 break;
 487                                                         case ATOM_HPD_INT_RECORD_TYPE:
 488                                                                 hpd_record =
 489                                                                         (ATOM_HPD_INT_RECORD *)
 490                                                                         record;
 491                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 492                                                                                           hpd_record->ucHPDIntGPIOID);
 493                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 494                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 495                                                                 break;
 496                                                         }
 497                                                         record =
 498                                                             (ATOM_COMMON_RECORD_HEADER
 499                                                              *) ((char *)record
 500                                                                  +
 501                                                                  record->
 502                                                                  ucRecordSize);
 503                                                 }
 504                                                 break;
 505                                         }
 506                                 }
 507                         }
 508
 509                         /* needed for aux chan transactions */
 510                         ddc_bus.hpd = hpd.hpd;
 511
 512                         conn_id = le16_to_cpu(path->usConnObjectId);
 513
 514                         if (!amdgpu_atombios_apply_quirks
 515                             (adev, le16_to_cpu(path->usDeviceTag), &connector_type,
 516                              &ddc_bus, &conn_id, &hpd))
 517                                 continue;
 518
 519                         amdgpu_display_add_connector(adev,
 520                                                       conn_id,
 521                                                       le16_to_cpu(path->usDeviceTag),
 522                                                       connector_type, &ddc_bus,
 523                                                       connector_object_id,
 524                                                       &hpd,
 525                                                       &router);
 526
 527                 }
 528         }
 529
 530         amdgpu_link_encoder_connector(adev->ddev);
 531
 532         return true;
 533 }
 534
 535 union firmware_info {
 536         ATOM_FIRMWARE_INFO info;
 537         ATOM_FIRMWARE_INFO_V1_2 info_12;
 538         ATOM_FIRMWARE_INFO_V1_3 info_13;
 539         ATOM_FIRMWARE_INFO_V1_4 info_14;
 540         ATOM_FIRMWARE_INFO_V2_1 info_21;
 541         ATOM_FIRMWARE_INFO_V2_2 info_22;
 542 };
 543
 544 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 545 {
 546         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 547         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 548         uint8_t frev, crev;
 549         uint16_t data_offset;
 550         int ret = -EINVAL;
 551
 552         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 553                                    &frev, &crev, &data_offset)) {
 554                 int i;
 555                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 556                 struct amdgpu_pll *spll = &adev->clock.spll;
 557                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 558                 union firmware_info *firmware_info =
 559                         (union firmware_info *)(mode_info->atom_context->bios +
 560                                                 data_offset);
 561                 /* pixel clocks */
 562                 ppll->reference_freq =
 563                     le16_to_cpu(firmware_info->info.usReferenceClock);
 564                 ppll->reference_div = 0;
 565
 566                 ppll->pll_out_min =
 567                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 568                 ppll->pll_out_max =
 569                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 570
 571                 ppll->lcd_pll_out_min =
 572                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 573                 if (ppll->lcd_pll_out_min == 0)
 574                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 575                 ppll->lcd_pll_out_max =
 576                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 577                 if (ppll->lcd_pll_out_max == 0)
 578                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 579
 580                 if (ppll->pll_out_min == 0)
 581                         ppll->pll_out_min = 64800;
 582
 583                 ppll->pll_in_min =
 584                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 585                 ppll->pll_in_max =
 586                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 587
 588                 ppll->min_post_div = 2;
 589                 ppll->max_post_div = 0x7f;
 590                 ppll->min_frac_feedback_div = 0;
 591                 ppll->max_frac_feedback_div = 9;
 592                 ppll->min_ref_div = 2;
 593                 ppll->max_ref_div = 0x3ff;
 594                 ppll->min_feedback_div = 4;
 595                 ppll->max_feedback_div = 0xfff;
 596                 ppll->best_vco = 0;
 597
 598                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 599                         adev->clock.ppll[i] = *ppll;
 600
 601                 /* system clock */
 602                 spll->reference_freq =
 603                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 604                 spll->reference_div = 0;
 605
 606                 spll->pll_out_min =
 607                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 608                 spll->pll_out_max =
 609                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 610
 611                 /* ??? */
 612                 if (spll->pll_out_min == 0)
 613                         spll->pll_out_min = 64800;
 614
 615                 spll->pll_in_min =
 616                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 617                 spll->pll_in_max =
 618                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 619
 620                 spll->min_post_div = 1;
 621                 spll->max_post_div = 1;
 622                 spll->min_ref_div = 2;
 623                 spll->max_ref_div = 0xff;
 624                 spll->min_feedback_div = 4;
 625                 spll->max_feedback_div = 0xff;
 626                 spll->best_vco = 0;
 627
 628                 /* memory clock */
 629                 mpll->reference_freq =
 630                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 631                 mpll->reference_div = 0;
 632
 633                 mpll->pll_out_min =
 634                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 635                 mpll->pll_out_max =
 636                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 637
 638                 /* ??? */
 639                 if (mpll->pll_out_min == 0)
 640                         mpll->pll_out_min = 64800;
 641
 642                 mpll->pll_in_min =
 643                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 644                 mpll->pll_in_max =
 645                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 646
 647                 adev->clock.default_sclk =
 648                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 649                 adev->clock.default_mclk =
 650                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 651
 652                 mpll->min_post_div = 1;
 653                 mpll->max_post_div = 1;
 654                 mpll->min_ref_div = 2;
 655                 mpll->max_ref_div = 0xff;
 656                 mpll->min_feedback_div = 4;
 657                 mpll->max_feedback_div = 0xff;
 658                 mpll->best_vco = 0;
 659
 660                 /* disp clock */
 661                 adev->clock.default_dispclk =
 662                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 663                 /* set a reasonable default for DP */
 664                 if (adev->clock.default_dispclk < 53900) {
 665                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 666                                  adev->clock.default_dispclk / 100);
 667                         adev->clock.default_dispclk = 60000;
 668                 } else if (adev->clock.default_dispclk <= 60000) {
 669                         DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
 670                                  adev->clock.default_dispclk / 100);
 671                         adev->clock.default_dispclk = 62500;
 672                 }
 673                 adev->clock.dp_extclk =
 674                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 675                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 676
 677                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 678                 if (adev->clock.max_pixel_clock == 0)
 679                         adev->clock.max_pixel_clock = 40000;
 680
 681                 /* not technically a clock, but... */
 682                 adev->mode_info.firmware_flags =
 683                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 684
 685                 ret = 0;
 686         }
 687
 688         adev->pm.current_sclk = adev->clock.default_sclk;
 689         adev->pm.current_mclk = adev->clock.default_mclk;
 690
 691         return ret;
 692 }
 693
 694 union igp_info {
 695         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 696         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 697         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 698         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 699         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 700         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 701 };
 702
 703 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 704                                                  struct amdgpu_atom_ss *ss,
 705                                                  int id)
 706 {
 707         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 708         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 709         u16 data_offset, size;
 710         union igp_info *igp_info;
 711         u8 frev, crev;
 712         u16 percentage = 0, rate = 0;
 713
 714         /* get any igp specific overrides */
 715         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 716                                    &frev, &crev, &data_offset)) {
 717                 igp_info = (union igp_info *)
 718                         (mode_info->atom_context->bios + data_offset);
 719                 switch (crev) {
 720                 case 6:
 721                         switch (id) {
 722                         case ASIC_INTERNAL_SS_ON_TMDS:
 723                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 724                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 725                                 break;
 726                         case ASIC_INTERNAL_SS_ON_HDMI:
 727                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 728                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 729                                 break;
 730                         case ASIC_INTERNAL_SS_ON_LVDS:
 731                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 732                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 733                                 break;
 734                         }
 735                         break;
 736                 case 7:
 737                         switch (id) {
 738                         case ASIC_INTERNAL_SS_ON_TMDS:
 739                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 740                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 741                                 break;
 742                         case ASIC_INTERNAL_SS_ON_HDMI:
 743                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 744                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 745                                 break;
 746                         case ASIC_INTERNAL_SS_ON_LVDS:
 747                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 748                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 749                                 break;
 750                         }
 751                         break;
 752                 case 8:
 753                         switch (id) {
 754                         case ASIC_INTERNAL_SS_ON_TMDS:
 755                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 756                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 757                                 break;
 758                         case ASIC_INTERNAL_SS_ON_HDMI:
 759                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 760                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 761                                 break;
 762                         case ASIC_INTERNAL_SS_ON_LVDS:
 763                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 764                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 765                                 break;
 766                         }
 767                         break;
 768                 case 9:
 769                         switch (id) {
 770                         case ASIC_INTERNAL_SS_ON_TMDS:
 771                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 772                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 773                                 break;
 774                         case ASIC_INTERNAL_SS_ON_HDMI:
 775                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 776                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 777                                 break;
 778                         case ASIC_INTERNAL_SS_ON_LVDS:
 779                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 780                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 781                                 break;
 782                         }
 783                         break;
 784                 default:
 785                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 786                         break;
 787                 }
 788                 if (percentage)
 789                         ss->percentage = percentage;
 790                 if (rate)
 791                         ss->rate = rate;
 792         }
 793 }
 794
 795 union asic_ss_info {
 796         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 797         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 798         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 799 };
 800
 801 union asic_ss_assignment {
 802         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 803         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 804         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 805 };
 806
 807 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 808                                       struct amdgpu_atom_ss *ss,
 809                                       int id, u32 clock)
 810 {
 811         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 812         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 813         uint16_t data_offset, size;
 814         union asic_ss_info *ss_info;
 815         union asic_ss_assignment *ss_assign;
 816         uint8_t frev, crev;
 817         int i, num_indices;
 818
 819         if (id == ASIC_INTERNAL_MEMORY_SS) {
 820                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 821                         return false;
 822         }
 823         if (id == ASIC_INTERNAL_ENGINE_SS) {
 824                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 825                         return false;
 826         }
 827
 828         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 829         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 830                                    &frev, &crev, &data_offset)) {
 831
 832                 ss_info =
 833                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 834
 835                 switch (frev) {
 836                 case 1:
 837                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 838                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 839
 840                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 841                         for (i = 0; i < num_indices; i++) {
 842                                 if ((ss_assign->v1.ucClockIndication == id) &&
 843                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 844                                         ss->percentage =
 845                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 846                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 847                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 848                                         ss->percentage_divider = 100;
 849                                         return true;
 850                                 }
 851                                 ss_assign = (union asic_ss_assignment *)
 852                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 853                         }
 854                         break;
 855                 case 2:
 856                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 857                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 858                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 859                         for (i = 0; i < num_indices; i++) {
 860                                 if ((ss_assign->v2.ucClockIndication == id) &&
 861                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 862                                         ss->percentage =
 863                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 864                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 865                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 866                                         ss->percentage_divider = 100;
 867                                         if ((crev == 2) &&
 868                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 869                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 870                                                 ss->rate /= 100;
 871                                         return true;
 872                                 }
 873                                 ss_assign = (union asic_ss_assignment *)
 874                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 875                         }
 876                         break;
 877                 case 3:
 878                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 879                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 880                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 881                         for (i = 0; i < num_indices; i++) {
 882                                 if ((ss_assign->v3.ucClockIndication == id) &&
 883                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 884                                         ss->percentage =
 885                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 886                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 887                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 888                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 889                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 890                                                 ss->percentage_divider = 1000;
 891                                         else
 892                                                 ss->percentage_divider = 100;
 893                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 894                                             (id == ASIC_INTERNAL_MEMORY_SS))
 895                                                 ss->rate /= 100;
 896                                         if (adev->flags & AMD_IS_APU)
 897                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 898                                         return true;
 899                                 }
 900                                 ss_assign = (union asic_ss_assignment *)
 901                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 902                         }
 903                         break;
 904                 default:
 905                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 906                         break;
 907                 }
 908
 909         }
 910         return false;
 911 }
 912
 913 union get_clock_dividers {
 914         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 915         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 916         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 917         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 918         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 919         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 920         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 921 };
 922
 923 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 924                                        u8 clock_type,
 925                                        u32 clock,
 926                                        bool strobe_mode,
 927                                        struct atom_clock_dividers *dividers)
 928 {
 929         union get_clock_dividers args;
 930         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 931         u8 frev, crev;
 932
 933         memset(&args, 0, sizeof(args));
 934         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 935
 936         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 937                 return -EINVAL;
 938
 939         switch (crev) {
 940         case 4:
 941                 /* fusion */
 942                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
 943
 944                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 945
 946                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
 947                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
 948                 break;
 949         case 6:
 950                 /* CI */
 951                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
 952                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
 953                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
 954
 955                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 956
 957                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
 958                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
 959                 dividers->ref_div = args.v6_out.ucPllRefDiv;
 960                 dividers->post_div = args.v6_out.ucPllPostDiv;
 961                 dividers->flags = args.v6_out.ucPllCntlFlag;
 962                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
 963                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
 964                 break;
 965         default:
 966                 return -EINVAL;
 967         }
 968         return 0;
 969 }
 970
 971 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
 972                                             u32 clock,
 973                                             bool strobe_mode,
 974                                             struct atom_mpll_param *mpll_param)
 975 {
 976         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
 977         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
 978         u8 frev, crev;
 979
 980         memset(&args, 0, sizeof(args));
 981         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
 982
 983         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 984                 return -EINVAL;
 985
 986         switch (frev) {
 987         case 2:
 988                 switch (crev) {
 989                 case 1:
 990                         /* SI */
 991                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
 992                         args.ucInputFlag = 0;
 993                         if (strobe_mode)
 994                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
 995
 996                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 997
 998                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
 999                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1000                         mpll_param->post_div = args.ucPostDiv;
1001                         mpll_param->dll_speed = args.ucDllSpeed;
1002                         mpll_param->bwcntl = args.ucBWCntl;
1003                         mpll_param->vco_mode =
1004                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1005                         mpll_param->yclk_sel =
1006                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1007                         mpll_param->qdr =
1008                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1009                         mpll_param->half_rate =
1010                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1011                         break;
1012                 default:
1013                         return -EINVAL;
1014                 }
1015                 break;
1016         default:
1017                 return -EINVAL;
1018         }
1019         return 0;
1020 }
1021
1022 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1023 {
1024         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1025         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1026
1027         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1028         return le32_to_cpu(args.ulReturnEngineClock);
1029 }
1030
1031 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1032 {
1033         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1034         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1035
1036         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1037         return le32_to_cpu(args.ulReturnMemoryClock);
1038 }
1039
1040 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1041                                       uint32_t eng_clock)
1042 {
1043         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1044         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1045
1046         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1047
1048         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1049 }
1050
1051 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1052                                       uint32_t mem_clock)
1053 {
1054         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1055         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1056
1057         if (adev->flags & AMD_IS_APU)
1058                 return;
1059
1060         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1061
1062         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1063 }
1064
1065 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1066                                              u32 eng_clock, u32 mem_clock)
1067 {
1068         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1069         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1070         u32 tmp;
1071
1072         memset(&args, 0, sizeof(args));
1073
1074         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1075         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1076
1077         args.ulTargetEngineClock = cpu_to_le32(tmp);
1078         if (mem_clock)
1079                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1080
1081         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1082 }
1083
1084 union set_voltage {
1085         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1086         struct _SET_VOLTAGE_PARAMETERS v1;
1087         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1088         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1089 };
1090
1091 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1092                                  u16 voltage_level,
1093                                  u8 voltage_type)
1094 {
1095         union set_voltage args;
1096         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1097         u8 frev, crev, volt_index = voltage_level;
1098
1099         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1100                 return;
1101
1102         /* 0xff01 is a flag rather then an actual voltage */
1103         if (voltage_level == 0xff01)
1104                 return;
1105
1106         switch (crev) {
1107         case 1:
1108                 args.v1.ucVoltageType = voltage_type;
1109                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1110                 args.v1.ucVoltageIndex = volt_index;
1111                 break;
1112         case 2:
1113                 args.v2.ucVoltageType = voltage_type;
1114                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1115                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1116                 break;
1117         case 3:
1118                 args.v3.ucVoltageType = voltage_type;
1119                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1120                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1121                 break;
1122         default:
1123                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1124                 return;
1125         }
1126
1127         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1128 }
1129
1130 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1131                                               u16 *leakage_id)
1132 {
1133         union set_voltage args;
1134         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1135         u8 frev, crev;
1136
1137         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1138                 return -EINVAL;
1139
1140         switch (crev) {
1141         case 3:
1142         case 4:
1143                 args.v3.ucVoltageType = 0;
1144                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1145                 args.v3.usVoltageLevel = 0;
1146
1147                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1148
1149                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1150                 break;
1151         default:
1152                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1153                 return -EINVAL;
1154         }
1155
1156         return 0;
1157 }
1158
1159 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1160                                                              u16 *vddc, u16 *vddci,
1161                                                              u16 virtual_voltage_id,
1162                                                              u16 vbios_voltage_id)
1163 {
1164         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1165         u8 frev, crev;
1166         u16 data_offset, size;
1167         int i, j;
1168         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1169         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1170
1171         *vddc = 0;
1172         *vddci = 0;
1173
1174         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1175                                     &frev, &crev, &data_offset))
1176                 return -EINVAL;
1177
1178         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1179                 (adev->mode_info.atom_context->bios + data_offset);
1180
1181         switch (frev) {
1182         case 1:
1183                 return -EINVAL;
1184         case 2:
1185                 switch (crev) {
1186                 case 1:
1187                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1188                                 return -EINVAL;
1189                         leakage_bin = (u16 *)
1190                                 (adev->mode_info.atom_context->bios + data_offset +
1191                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1192                         vddc_id_buf = (u16 *)
1193                                 (adev->mode_info.atom_context->bios + data_offset +
1194                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1195                         vddc_buf = (u16 *)
1196                                 (adev->mode_info.atom_context->bios + data_offset +
1197                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1198                         vddci_id_buf = (u16 *)
1199                                 (adev->mode_info.atom_context->bios + data_offset +
1200                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1201                         vddci_buf = (u16 *)
1202                                 (adev->mode_info.atom_context->bios + data_offset +
1203                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1204
1205                         if (profile->ucElbVDDC_Num > 0) {
1206                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1207                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1208                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1209                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1210                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1211                                                                 break;
1212                                                         }
1213                                                 }
1214                                                 break;
1215                                         }
1216                                 }
1217                         }
1218                         if (profile->ucElbVDDCI_Num > 0) {
1219                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1220                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1221                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1222                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1223                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1224                                                                 break;
1225                                                         }
1226                                                 }
1227                                                 break;
1228                                         }
1229                                 }
1230                         }
1231                         break;
1232                 default:
1233                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1234                         return -EINVAL;
1235                 }
1236                 break;
1237         default:
1238                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1239                 return -EINVAL;
1240         }
1241
1242         return 0;
1243 }
1244
1245 union get_voltage_info {
1246         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1247         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1248 };
1249
1250 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1251                                     u16 virtual_voltage_id,
1252                                     u16 *voltage)
1253 {
1254         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1255         u32 entry_id;
1256         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1257         union get_voltage_info args;
1258
1259         for (entry_id = 0; entry_id < count; entry_id++) {
1260                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1261                     virtual_voltage_id)
1262                         break;
1263         }
1264
1265         if (entry_id >= count)
1266                 return -EINVAL;
1267
1268         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1269         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1270         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1271         args.in.ulSCLKFreq =
1272                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1273
1274         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1275
1276         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1277
1278         return 0;
1279 }
1280
1281 union voltage_object_info {
1282         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1283         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1284         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1285 };
1286
1287 union voltage_object {
1288         struct _ATOM_VOLTAGE_OBJECT v1;
1289         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1290         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1291 };
1292
1293
1294 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1295                                                                         u8 voltage_type, u8 voltage_mode)
1296 {
1297         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1298         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1299         u8 *start = (u8*)v3;
1300
1301         while (offset < size) {
1302                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1303                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1304                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1305                         return vo;
1306                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1307         }
1308         return NULL;
1309 }
1310
1311 bool
1312 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1313                                 u8 voltage_type, u8 voltage_mode)
1314 {
1315         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1316         u8 frev, crev;
1317         u16 data_offset, size;
1318         union voltage_object_info *voltage_info;
1319
1320         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1321                                    &frev, &crev, &data_offset)) {
1322                 voltage_info = (union voltage_object_info *)
1323                         (adev->mode_info.atom_context->bios + data_offset);
1324
1325                 switch (frev) {
1326                 case 3:
1327                         switch (crev) {
1328                         case 1:
1329                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1330                                                                   voltage_type, voltage_mode))
1331                                         return true;
1332                                 break;
1333                         default:
1334                                 DRM_ERROR("unknown voltage object table\n");
1335                                 return false;
1336                         }
1337                         break;
1338                 default:
1339                         DRM_ERROR("unknown voltage object table\n");
1340                         return false;
1341                 }
1342
1343         }
1344         return false;
1345 }
1346
1347 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1348                                       u8 voltage_type, u8 voltage_mode,
1349                                       struct atom_voltage_table *voltage_table)
1350 {
1351         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1352         u8 frev, crev;
1353         u16 data_offset, size;
1354         int i;
1355         union voltage_object_info *voltage_info;
1356         union voltage_object *voltage_object = NULL;
1357
1358         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1359                                    &frev, &crev, &data_offset)) {
1360                 voltage_info = (union voltage_object_info *)
1361                         (adev->mode_info.atom_context->bios + data_offset);
1362
1363                 switch (frev) {
1364                 case 3:
1365                         switch (crev) {
1366                         case 1:
1367                                 voltage_object = (union voltage_object *)
1368                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1369                                                                       voltage_type, voltage_mode);
1370                                 if (voltage_object) {
1371                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1372                                                 &voltage_object->v3.asGpioVoltageObj;
1373                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1374                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1375                                                 return -EINVAL;
1376                                         lut = &gpio->asVolGpioLut[0];
1377                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1378                                                 voltage_table->entries[i].value =
1379                                                         le16_to_cpu(lut->usVoltageValue);
1380                                                 voltage_table->entries[i].smio_low =
1381                                                         le32_to_cpu(lut->ulVoltageId);
1382                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1383                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1384                                         }
1385                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1386                                         voltage_table->count = gpio->ucGpioEntryNum;
1387                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1388                                         return 0;
1389                                 }
1390                                 break;
1391                         default:
1392                                 DRM_ERROR("unknown voltage object table\n");
1393                                 return -EINVAL;
1394                         }
1395                         break;
1396                 default:
1397                         DRM_ERROR("unknown voltage object table\n");
1398                         return -EINVAL;
1399                 }
1400         }
1401         return -EINVAL;
1402 }
1403
1404 union vram_info {
1405         struct _ATOM_VRAM_INFO_V3 v1_3;
1406         struct _ATOM_VRAM_INFO_V4 v1_4;
1407         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1408 };
1409
1410 #define MEM_ID_MASK           0xff000000
1411 #define MEM_ID_SHIFT          24
1412 #define CLOCK_RANGE_MASK      0x00ffffff
1413 #define CLOCK_RANGE_SHIFT     0
1414 #define LOW_NIBBLE_MASK       0xf
1415 #define DATA_EQU_PREV         0
1416 #define DATA_FROM_TABLE       4
1417
1418 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1419                                       u8 module_index,
1420                                       struct atom_mc_reg_table *reg_table)
1421 {
1422         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1423         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1424         u32 i = 0, j;
1425         u16 data_offset, size;
1426         union vram_info *vram_info;
1427
1428         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1429
1430         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1431                                    &frev, &crev, &data_offset)) {
1432                 vram_info = (union vram_info *)
1433                         (adev->mode_info.atom_context->bios + data_offset);
1434                 switch (frev) {
1435                 case 1:
1436                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1437                         return -EINVAL;
1438                 case 2:
1439                         switch (crev) {
1440                         case 1:
1441                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1442                                         ATOM_INIT_REG_BLOCK *reg_block =
1443                                                 (ATOM_INIT_REG_BLOCK *)
1444                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1445                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1446                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1447                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1448                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1449                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1450                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1451                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1452                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1453                                                 return -EINVAL;
1454                                         while (i < num_entries) {
1455                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1456                                                         break;
1457                                                 reg_table->mc_reg_address[i].s1 =
1458                                                         (u16)(le16_to_cpu(format->usRegIndex));
1459                                                 reg_table->mc_reg_address[i].pre_reg_data =
1460                                                         (u8)(format->ucPreRegDataLength);
1461                                                 i++;
1462                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1463                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1464                                         }
1465                                         reg_table->last = i;
1466                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1467                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1468                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1469                                                                 >> MEM_ID_SHIFT);
1470                                                 if (module_index == t_mem_id) {
1471                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1472                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1473                                                                       >> CLOCK_RANGE_SHIFT);
1474                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1475                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1476                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1477                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1478                                                                         j++;
1479                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1480                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1481                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1482                                                                 }
1483                                                         }
1484                                                         num_ranges++;
1485                                                 }
1486                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1487                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1488                                         }
1489                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1490                                                 return -EINVAL;
1491                                         reg_table->num_entries = num_ranges;
1492                                 } else
1493                                         return -EINVAL;
1494                                 break;
1495                         default:
1496                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1497                                 return -EINVAL;
1498                         }
1499                         break;
1500                 default:
1501                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1502                         return -EINVAL;
1503                 }
1504                 return 0;
1505         }
1506         return -EINVAL;
1507 }
1508
1509 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1510 {
1511         uint32_t bios_6_scratch;
1512
1513         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1514
1515         if (lock) {
1516                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1517                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1518         } else {
1519                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1520                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1521         }
1522
1523         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1524 }
1525
1526 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1527 {
1528         uint32_t bios_2_scratch, bios_6_scratch;
1529
1530         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1531         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1532
1533         /* let the bios control the backlight */
1534         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1535
1536         /* tell the bios not to handle mode switching */
1537         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1538
1539         /* clear the vbios dpms state */
1540         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1541
1542         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1543         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1544 }
1545
1546 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1547 {
1548         int i;
1549
1550         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1551                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1552 }
1553
1554 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1555 {
1556         int i;
1557
1558         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1559                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1560 }
1561
1562 /* Atom needs data in little endian format so swap as appropriate when copying
1563  * data to or from atom. Note that atom operates on dw units.
1564  *
1565  * Use to_le=true when sending data to atom and provide at least
1566  * ALIGN(num_bytes,4) bytes in the dst buffer.
1567  *
1568  * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1569  * byes in the src buffer.
1570  */
1571 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1572 {
1573 #ifdef __BIG_ENDIAN
1574         u32 src_tmp[5], dst_tmp[5];
1575         int i;
1576         u8 align_num_bytes = ALIGN(num_bytes, 4);
1577
1578         if (to_le) {
1579                 memcpy(src_tmp, src, num_bytes);
1580                 for (i = 0; i < align_num_bytes / 4; i++)
1581                         dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1582                 memcpy(dst, dst_tmp, align_num_bytes);
1583         } else {
1584                 memcpy(src_tmp, src, align_num_bytes);
1585                 for (i = 0; i < align_num_bytes / 4; i++)
1586                         dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1587                 memcpy(dst, dst_tmp, num_bytes);
1588         }
1589 #else
1590         memcpy(dst, src, num_bytes);
1591 #endif
1592 }