drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static const int object_connector_convert[] = {
 238         DRM_MODE_CONNECTOR_Unknown,
 239         DRM_MODE_CONNECTOR_DVII,
 240         DRM_MODE_CONNECTOR_DVII,
 241         DRM_MODE_CONNECTOR_DVID,
 242         DRM_MODE_CONNECTOR_DVID,
 243         DRM_MODE_CONNECTOR_VGA,
 244         DRM_MODE_CONNECTOR_Composite,
 245         DRM_MODE_CONNECTOR_SVIDEO,
 246         DRM_MODE_CONNECTOR_Unknown,
 247         DRM_MODE_CONNECTOR_Unknown,
 248         DRM_MODE_CONNECTOR_9PinDIN,
 249         DRM_MODE_CONNECTOR_Unknown,
 250         DRM_MODE_CONNECTOR_HDMIA,
 251         DRM_MODE_CONNECTOR_HDMIB,
 252         DRM_MODE_CONNECTOR_LVDS,
 253         DRM_MODE_CONNECTOR_9PinDIN,
 254         DRM_MODE_CONNECTOR_Unknown,
 255         DRM_MODE_CONNECTOR_Unknown,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_DisplayPort,
 258         DRM_MODE_CONNECTOR_eDP,
 259         DRM_MODE_CONNECTOR_Unknown
 260 };
 261
 262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 265         struct atom_context *ctx = mode_info->atom_context;
 266         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 267         u16 size, data_offset;
 268         u8 frev, crev;
 269         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 270         ATOM_OBJECT_HEADER *obj_header;
 271
 272         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 273                 return false;
 274
 275         if (crev < 2)
 276                 return false;
 277
 278         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 279         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 280             (ctx->bios + data_offset +
 281              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 282
 283         if (path_obj->ucNumOfDispPath)
 284                 return true;
 285         else
 286                 return false;
 287 }
 288
 289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 290 {
 291         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 292         struct atom_context *ctx = mode_info->atom_context;
 293         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 294         u16 size, data_offset;
 295         u8 frev, crev;
 296         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 297         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 298         ATOM_OBJECT_TABLE *router_obj;
 299         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 300         ATOM_OBJECT_HEADER *obj_header;
 301         int i, j, k, path_size, device_support;
 302         int connector_type;
 303         u16 conn_id, connector_object_id;
 304         struct amdgpu_i2c_bus_rec ddc_bus;
 305         struct amdgpu_router router;
 306         struct amdgpu_gpio_rec gpio;
 307         struct amdgpu_hpd hpd;
 308
 309         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 310                 return false;
 311
 312         if (crev < 2)
 313                 return false;
 314
 315         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 316         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 317             (ctx->bios + data_offset +
 318              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 319         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 320             (ctx->bios + data_offset +
 321              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 322         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 323             (ctx->bios + data_offset +
 324              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 325         router_obj = (ATOM_OBJECT_TABLE *)
 326                 (ctx->bios + data_offset +
 327                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 328         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 329
 330         path_size = 0;
 331         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 332                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 333                 ATOM_DISPLAY_OBJECT_PATH *path;
 334                 addr += path_size;
 335                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 336                 path_size += le16_to_cpu(path->usSize);
 337
 338                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 339                         uint8_t con_obj_id =
 340                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 341                             >> OBJECT_ID_SHIFT;
 342
 343                         /* Skip TV/CV support */
 344                         if ((le16_to_cpu(path->usDeviceTag) ==
 345                              ATOM_DEVICE_TV1_SUPPORT) ||
 346                             (le16_to_cpu(path->usDeviceTag) ==
 347                              ATOM_DEVICE_CV_SUPPORT))
 348                                 continue;
 349
 350                         if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 351                                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 352                                           con_obj_id, le16_to_cpu(path->usDeviceTag));
 353                                 continue;
 354                         }
 355
 356                         connector_type =
 357                                 object_connector_convert[con_obj_id];
 358                         connector_object_id = con_obj_id;
 359
 360                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 361                                 continue;
 362
 363                         router.ddc_valid = false;
 364                         router.cd_valid = false;
 365                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 366                                 uint8_t grph_obj_type =
 367                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 368                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 369
 370                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 371                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 372                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 373                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 374                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 375                                                                 (ctx->bios + data_offset +
 376                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 377                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 378                                                         u16 caps = 0;
 379
 380                                                         while (record->ucRecordSize > 0 &&
 381                                                                record->ucRecordType > 0 &&
 382                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 383                                                                 switch (record->ucRecordType) {
 384                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 385                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 386                                                                                 record;
 387                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 388                                                                         break;
 389                                                                 }
 390                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 391                                                                         ((char *)record + record->ucRecordSize);
 392                                                         }
 393                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 394                                                                                     le16_to_cpu(path->usDeviceTag),
 395                                                                                     caps);
 396                                                 }
 397                                         }
 398                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 399                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 400                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 401                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 402                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 403                                                                 (ctx->bios + data_offset +
 404                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 405                                                         ATOM_I2C_RECORD *i2c_record;
 406                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 407                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 408                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 409                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 410                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 411                                                                 (ctx->bios + data_offset +
 412                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 413                                                         u8 *num_dst_objs = (u8 *)
 414                                                                 ((u8 *)router_src_dst_table + 1 +
 415                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 416                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 417                                                         int enum_id;
 418
 419                                                         router.router_id = router_obj_id;
 420                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 421                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 422                                                                     le16_to_cpu(dst_objs[enum_id]))
 423                                                                         break;
 424                                                         }
 425
 426                                                         while (record->ucRecordSize > 0 &&
 427                                                                record->ucRecordType > 0 &&
 428                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 429                                                                 switch (record->ucRecordType) {
 430                                                                 case ATOM_I2C_RECORD_TYPE:
 431                                                                         i2c_record =
 432                                                                                 (ATOM_I2C_RECORD *)
 433                                                                                 record;
 434                                                                         i2c_config =
 435                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 436                                                                                 &i2c_record->sucI2cId;
 437                                                                         router.i2c_info =
 438                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 439                                                                                                        i2c_config->
 440                                                                                                        ucAccess);
 441                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 442                                                                         break;
 443                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 444                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 445                                                                                 record;
 446                                                                         router.ddc_valid = true;
 447                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 448                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 449                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 450                                                                         break;
 451                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 452                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 453                                                                                 record;
 454                                                                         router.cd_valid = true;
 455                                                                         router.cd_mux_type = cd_path->ucMuxType;
 456                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 457                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 458                                                                         break;
 459                                                                 }
 460                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 461                                                                         ((char *)record + record->ucRecordSize);
 462                                                         }
 463                                                 }
 464                                         }
 465                                 }
 466                         }
 467
 468                         /* look up gpio for ddc, hpd */
 469                         ddc_bus.valid = false;
 470                         hpd.hpd = AMDGPU_HPD_NONE;
 471                         if ((le16_to_cpu(path->usDeviceTag) &
 472                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 473                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 474                                         if (le16_to_cpu(path->usConnObjectId) ==
 475                                             le16_to_cpu(con_obj->asObjects[j].
 476                                                         usObjectID)) {
 477                                                 ATOM_COMMON_RECORD_HEADER
 478                                                     *record =
 479                                                     (ATOM_COMMON_RECORD_HEADER
 480                                                      *)
 481                                                     (ctx->bios + data_offset +
 482                                                      le16_to_cpu(con_obj->
 483                                                                  asObjects[j].
 484                                                                  usRecordOffset));
 485                                                 ATOM_I2C_RECORD *i2c_record;
 486                                                 ATOM_HPD_INT_RECORD *hpd_record;
 487                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 488
 489                                                 while (record->ucRecordSize > 0 &&
 490                                                        record->ucRecordType > 0 &&
 491                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 492                                                         switch (record->ucRecordType) {
 493                                                         case ATOM_I2C_RECORD_TYPE:
 494                                                                 i2c_record =
 495                                                                     (ATOM_I2C_RECORD *)
 496                                                                         record;
 497                                                                 i2c_config =
 498                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 499                                                                         &i2c_record->sucI2cId;
 500                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 501                                                                                                  i2c_config->
 502                                                                                                  ucAccess);
 503                                                                 break;
 504                                                         case ATOM_HPD_INT_RECORD_TYPE:
 505                                                                 hpd_record =
 506                                                                         (ATOM_HPD_INT_RECORD *)
 507                                                                         record;
 508                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 509                                                                                           hpd_record->ucHPDIntGPIOID);
 510                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 511                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 512                                                                 break;
 513                                                         }
 514                                                         record =
 515                                                             (ATOM_COMMON_RECORD_HEADER
 516                                                              *) ((char *)record
 517                                                                  +
 518                                                                  record->
 519                                                                  ucRecordSize);
 520                                                 }
 521                                                 break;
 522                                         }
 523                                 }
 524                         }
 525
 526                         /* needed for aux chan transactions */
 527                         ddc_bus.hpd = hpd.hpd;
 528
 529                         conn_id = le16_to_cpu(path->usConnObjectId);
 530
 531                         amdgpu_display_add_connector(adev,
 532                                                       conn_id,
 533                                                       le16_to_cpu(path->usDeviceTag),
 534                                                       connector_type, &ddc_bus,
 535                                                       connector_object_id,
 536                                                       &hpd,
 537                                                       &router);
 538
 539                 }
 540         }
 541
 542         amdgpu_link_encoder_connector(adev->ddev);
 543
 544         return true;
 545 }
 546
 547 union firmware_info {
 548         ATOM_FIRMWARE_INFO info;
 549         ATOM_FIRMWARE_INFO_V1_2 info_12;
 550         ATOM_FIRMWARE_INFO_V1_3 info_13;
 551         ATOM_FIRMWARE_INFO_V1_4 info_14;
 552         ATOM_FIRMWARE_INFO_V2_1 info_21;
 553         ATOM_FIRMWARE_INFO_V2_2 info_22;
 554 };
 555
 556 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 557 {
 558         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 559         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 560         uint8_t frev, crev;
 561         uint16_t data_offset;
 562         int ret = -EINVAL;
 563
 564         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 565                                    &frev, &crev, &data_offset)) {
 566                 int i;
 567                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 568                 struct amdgpu_pll *spll = &adev->clock.spll;
 569                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 570                 union firmware_info *firmware_info =
 571                         (union firmware_info *)(mode_info->atom_context->bios +
 572                                                 data_offset);
 573                 /* pixel clocks */
 574                 ppll->reference_freq =
 575                     le16_to_cpu(firmware_info->info.usReferenceClock);
 576                 ppll->reference_div = 0;
 577
 578                 ppll->pll_out_min =
 579                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 580                 ppll->pll_out_max =
 581                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 582
 583                 ppll->lcd_pll_out_min =
 584                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 585                 if (ppll->lcd_pll_out_min == 0)
 586                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 587                 ppll->lcd_pll_out_max =
 588                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 589                 if (ppll->lcd_pll_out_max == 0)
 590                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 591
 592                 if (ppll->pll_out_min == 0)
 593                         ppll->pll_out_min = 64800;
 594
 595                 ppll->pll_in_min =
 596                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 597                 ppll->pll_in_max =
 598                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 599
 600                 ppll->min_post_div = 2;
 601                 ppll->max_post_div = 0x7f;
 602                 ppll->min_frac_feedback_div = 0;
 603                 ppll->max_frac_feedback_div = 9;
 604                 ppll->min_ref_div = 2;
 605                 ppll->max_ref_div = 0x3ff;
 606                 ppll->min_feedback_div = 4;
 607                 ppll->max_feedback_div = 0xfff;
 608                 ppll->best_vco = 0;
 609
 610                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 611                         adev->clock.ppll[i] = *ppll;
 612
 613                 /* system clock */
 614                 spll->reference_freq =
 615                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 616                 spll->reference_div = 0;
 617
 618                 spll->pll_out_min =
 619                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 620                 spll->pll_out_max =
 621                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 622
 623                 /* ??? */
 624                 if (spll->pll_out_min == 0)
 625                         spll->pll_out_min = 64800;
 626
 627                 spll->pll_in_min =
 628                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 629                 spll->pll_in_max =
 630                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 631
 632                 spll->min_post_div = 1;
 633                 spll->max_post_div = 1;
 634                 spll->min_ref_div = 2;
 635                 spll->max_ref_div = 0xff;
 636                 spll->min_feedback_div = 4;
 637                 spll->max_feedback_div = 0xff;
 638                 spll->best_vco = 0;
 639
 640                 /* memory clock */
 641                 mpll->reference_freq =
 642                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 643                 mpll->reference_div = 0;
 644
 645                 mpll->pll_out_min =
 646                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 647                 mpll->pll_out_max =
 648                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 649
 650                 /* ??? */
 651                 if (mpll->pll_out_min == 0)
 652                         mpll->pll_out_min = 64800;
 653
 654                 mpll->pll_in_min =
 655                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 656                 mpll->pll_in_max =
 657                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 658
 659                 adev->clock.default_sclk =
 660                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 661                 adev->clock.default_mclk =
 662                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 663
 664                 mpll->min_post_div = 1;
 665                 mpll->max_post_div = 1;
 666                 mpll->min_ref_div = 2;
 667                 mpll->max_ref_div = 0xff;
 668                 mpll->min_feedback_div = 4;
 669                 mpll->max_feedback_div = 0xff;
 670                 mpll->best_vco = 0;
 671
 672                 /* disp clock */
 673                 adev->clock.default_dispclk =
 674                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 675                 /* set a reasonable default for DP */
 676                 if (adev->clock.default_dispclk < 53900) {
 677                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 678                                  adev->clock.default_dispclk / 100);
 679                         adev->clock.default_dispclk = 60000;
 680                 } else if (adev->clock.default_dispclk <= 60000) {
 681                         DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
 682                                  adev->clock.default_dispclk / 100);
 683                         adev->clock.default_dispclk = 62500;
 684                 }
 685                 adev->clock.dp_extclk =
 686                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 687                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 688
 689                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 690                 if (adev->clock.max_pixel_clock == 0)
 691                         adev->clock.max_pixel_clock = 40000;
 692
 693                 /* not technically a clock, but... */
 694                 adev->mode_info.firmware_flags =
 695                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 696
 697                 ret = 0;
 698         }
 699
 700         adev->pm.current_sclk = adev->clock.default_sclk;
 701         adev->pm.current_mclk = adev->clock.default_mclk;
 702
 703         return ret;
 704 }
 705
 706 union gfx_info {
 707         ATOM_GFX_INFO_V2_1 info;
 708 };
 709
 710 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
 711 {
 712         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 713         int index = GetIndexIntoMasterTable(DATA, GFX_Info);
 714         uint8_t frev, crev;
 715         uint16_t data_offset;
 716         int ret = -EINVAL;
 717
 718         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 719                                    &frev, &crev, &data_offset)) {
 720                 union gfx_info *gfx_info = (union gfx_info *)
 721                         (mode_info->atom_context->bios + data_offset);
 722
 723                 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
 724                 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
 725                 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
 726                 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
 727                 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
 728                 adev->gfx.config.max_texture_channel_caches =
 729                         gfx_info->info.max_texture_channel_caches;
 730
 731                 ret = 0;
 732         }
 733         return ret;
 734 }
 735
 736 union igp_info {
 737         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 738         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 739         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 740         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 741         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 742         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 743 };
 744
 745 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 746                                                  struct amdgpu_atom_ss *ss,
 747                                                  int id)
 748 {
 749         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 750         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 751         u16 data_offset, size;
 752         union igp_info *igp_info;
 753         u8 frev, crev;
 754         u16 percentage = 0, rate = 0;
 755
 756         /* get any igp specific overrides */
 757         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 758                                    &frev, &crev, &data_offset)) {
 759                 igp_info = (union igp_info *)
 760                         (mode_info->atom_context->bios + data_offset);
 761                 switch (crev) {
 762                 case 6:
 763                         switch (id) {
 764                         case ASIC_INTERNAL_SS_ON_TMDS:
 765                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 766                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 767                                 break;
 768                         case ASIC_INTERNAL_SS_ON_HDMI:
 769                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 770                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 771                                 break;
 772                         case ASIC_INTERNAL_SS_ON_LVDS:
 773                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 774                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 775                                 break;
 776                         }
 777                         break;
 778                 case 7:
 779                         switch (id) {
 780                         case ASIC_INTERNAL_SS_ON_TMDS:
 781                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 782                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 783                                 break;
 784                         case ASIC_INTERNAL_SS_ON_HDMI:
 785                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 786                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 787                                 break;
 788                         case ASIC_INTERNAL_SS_ON_LVDS:
 789                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 790                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 791                                 break;
 792                         }
 793                         break;
 794                 case 8:
 795                         switch (id) {
 796                         case ASIC_INTERNAL_SS_ON_TMDS:
 797                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 798                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 799                                 break;
 800                         case ASIC_INTERNAL_SS_ON_HDMI:
 801                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 802                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 803                                 break;
 804                         case ASIC_INTERNAL_SS_ON_LVDS:
 805                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 806                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 807                                 break;
 808                         }
 809                         break;
 810                 case 9:
 811                         switch (id) {
 812                         case ASIC_INTERNAL_SS_ON_TMDS:
 813                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 814                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 815                                 break;
 816                         case ASIC_INTERNAL_SS_ON_HDMI:
 817                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 818                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 819                                 break;
 820                         case ASIC_INTERNAL_SS_ON_LVDS:
 821                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 822                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 823                                 break;
 824                         }
 825                         break;
 826                 default:
 827                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 828                         break;
 829                 }
 830                 if (percentage)
 831                         ss->percentage = percentage;
 832                 if (rate)
 833                         ss->rate = rate;
 834         }
 835 }
 836
 837 union asic_ss_info {
 838         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 839         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 840         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 841 };
 842
 843 union asic_ss_assignment {
 844         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 845         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 846         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 847 };
 848
 849 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 850                                       struct amdgpu_atom_ss *ss,
 851                                       int id, u32 clock)
 852 {
 853         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 854         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 855         uint16_t data_offset, size;
 856         union asic_ss_info *ss_info;
 857         union asic_ss_assignment *ss_assign;
 858         uint8_t frev, crev;
 859         int i, num_indices;
 860
 861         if (id == ASIC_INTERNAL_MEMORY_SS) {
 862                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 863                         return false;
 864         }
 865         if (id == ASIC_INTERNAL_ENGINE_SS) {
 866                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 867                         return false;
 868         }
 869
 870         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 871         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 872                                    &frev, &crev, &data_offset)) {
 873
 874                 ss_info =
 875                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 876
 877                 switch (frev) {
 878                 case 1:
 879                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 880                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 881
 882                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 883                         for (i = 0; i < num_indices; i++) {
 884                                 if ((ss_assign->v1.ucClockIndication == id) &&
 885                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 886                                         ss->percentage =
 887                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 888                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 889                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 890                                         ss->percentage_divider = 100;
 891                                         return true;
 892                                 }
 893                                 ss_assign = (union asic_ss_assignment *)
 894                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 895                         }
 896                         break;
 897                 case 2:
 898                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 899                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 900                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 901                         for (i = 0; i < num_indices; i++) {
 902                                 if ((ss_assign->v2.ucClockIndication == id) &&
 903                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 904                                         ss->percentage =
 905                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 906                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 907                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 908                                         ss->percentage_divider = 100;
 909                                         if ((crev == 2) &&
 910                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 911                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 912                                                 ss->rate /= 100;
 913                                         return true;
 914                                 }
 915                                 ss_assign = (union asic_ss_assignment *)
 916                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 917                         }
 918                         break;
 919                 case 3:
 920                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 921                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 922                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 923                         for (i = 0; i < num_indices; i++) {
 924                                 if ((ss_assign->v3.ucClockIndication == id) &&
 925                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 926                                         ss->percentage =
 927                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 928                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 929                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 930                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 931                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 932                                                 ss->percentage_divider = 1000;
 933                                         else
 934                                                 ss->percentage_divider = 100;
 935                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 936                                             (id == ASIC_INTERNAL_MEMORY_SS))
 937                                                 ss->rate /= 100;
 938                                         if (adev->flags & AMD_IS_APU)
 939                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 940                                         return true;
 941                                 }
 942                                 ss_assign = (union asic_ss_assignment *)
 943                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 944                         }
 945                         break;
 946                 default:
 947                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 948                         break;
 949                 }
 950
 951         }
 952         return false;
 953 }
 954
 955 union get_clock_dividers {
 956         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 957         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 958         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 959         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 960         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 961         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 962         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 963 };
 964
 965 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 966                                        u8 clock_type,
 967                                        u32 clock,
 968                                        bool strobe_mode,
 969                                        struct atom_clock_dividers *dividers)
 970 {
 971         union get_clock_dividers args;
 972         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 973         u8 frev, crev;
 974
 975         memset(&args, 0, sizeof(args));
 976         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 977
 978         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 979                 return -EINVAL;
 980
 981         switch (crev) {
 982         case 2:
 983         case 3:
 984         case 5:
 985                 /* r6xx, r7xx, evergreen, ni, si.
 986                  * TODO: add support for asic_type <= CHIP_RV770*/
 987                 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
 988                         args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
 989
 990                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 991
 992                         dividers->post_div = args.v3.ucPostDiv;
 993                         dividers->enable_post_div = (args.v3.ucCntlFlag &
 994                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
 995                         dividers->enable_dithen = (args.v3.ucCntlFlag &
 996                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
 997                         dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
 998                         dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
 999                         dividers->ref_div = args.v3.ucRefDiv;
1000                         dividers->vco_mode = (args.v3.ucCntlFlag &
1001                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1002                 } else {
1003                         /* for SI we use ComputeMemoryClockParam for memory plls */
1004                         if (adev->asic_type >= CHIP_TAHITI)
1005                                 return -EINVAL;
1006                         args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1007                         if (strobe_mode)
1008                                 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1009
1010                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1011
1012                         dividers->post_div = args.v5.ucPostDiv;
1013                         dividers->enable_post_div = (args.v5.ucCntlFlag &
1014                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1015                         dividers->enable_dithen = (args.v5.ucCntlFlag &
1016                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1017                         dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1018                         dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1019                         dividers->ref_div = args.v5.ucRefDiv;
1020                         dividers->vco_mode = (args.v5.ucCntlFlag &
1021                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1022                 }
1023                 break;
1024         case 4:
1025                 /* fusion */
1026                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
1027
1028                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1029
1030                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1031                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1032                 break;
1033         case 6:
1034                 /* CI */
1035                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1036                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1037                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
1038
1039                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1040
1041                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1042                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1043                 dividers->ref_div = args.v6_out.ucPllRefDiv;
1044                 dividers->post_div = args.v6_out.ucPllPostDiv;
1045                 dividers->flags = args.v6_out.ucPllCntlFlag;
1046                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1047                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1048                 break;
1049         default:
1050                 return -EINVAL;
1051         }
1052         return 0;
1053 }
1054
1055 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1056                                             u32 clock,
1057                                             bool strobe_mode,
1058                                             struct atom_mpll_param *mpll_param)
1059 {
1060         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1061         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1062         u8 frev, crev;
1063
1064         memset(&args, 0, sizeof(args));
1065         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1066
1067         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1068                 return -EINVAL;
1069
1070         switch (frev) {
1071         case 2:
1072                 switch (crev) {
1073                 case 1:
1074                         /* SI */
1075                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1076                         args.ucInputFlag = 0;
1077                         if (strobe_mode)
1078                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1079
1080                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1081
1082                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1083                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1084                         mpll_param->post_div = args.ucPostDiv;
1085                         mpll_param->dll_speed = args.ucDllSpeed;
1086                         mpll_param->bwcntl = args.ucBWCntl;
1087                         mpll_param->vco_mode =
1088                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1089                         mpll_param->yclk_sel =
1090                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1091                         mpll_param->qdr =
1092                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1093                         mpll_param->half_rate =
1094                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1095                         break;
1096                 default:
1097                         return -EINVAL;
1098                 }
1099                 break;
1100         default:
1101                 return -EINVAL;
1102         }
1103         return 0;
1104 }
1105
1106 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1107 {
1108         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1109         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1110
1111         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1112         return le32_to_cpu(args.ulReturnEngineClock);
1113 }
1114
1115 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1116 {
1117         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1118         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1119
1120         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1121         return le32_to_cpu(args.ulReturnMemoryClock);
1122 }
1123
1124 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1125                                       uint32_t eng_clock)
1126 {
1127         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1128         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1129
1130         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1131
1132         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1133 }
1134
1135 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1136                                       uint32_t mem_clock)
1137 {
1138         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1139         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1140
1141         if (adev->flags & AMD_IS_APU)
1142                 return;
1143
1144         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1145
1146         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1147 }
1148
1149 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1150                                              u32 eng_clock, u32 mem_clock)
1151 {
1152         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1153         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1154         u32 tmp;
1155
1156         memset(&args, 0, sizeof(args));
1157
1158         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1159         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1160
1161         args.ulTargetEngineClock = cpu_to_le32(tmp);
1162         if (mem_clock)
1163                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1164
1165         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1166 }
1167
1168 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1169                                           u16 *vddc, u16 *vddci, u16 *mvdd)
1170 {
1171         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1172         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1173         u8 frev, crev;
1174         u16 data_offset;
1175         union firmware_info *firmware_info;
1176
1177         *vddc = 0;
1178         *vddci = 0;
1179         *mvdd = 0;
1180
1181         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1182                                    &frev, &crev, &data_offset)) {
1183                 firmware_info =
1184                         (union firmware_info *)(mode_info->atom_context->bios +
1185                                                 data_offset);
1186                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1187                 if ((frev == 2) && (crev >= 2)) {
1188                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1189                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1190                 }
1191         }
1192 }
1193
1194 union set_voltage {
1195         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1196         struct _SET_VOLTAGE_PARAMETERS v1;
1197         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1198         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1199 };
1200
1201 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1202                              u16 voltage_id, u16 *voltage)
1203 {
1204         union set_voltage args;
1205         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1206         u8 frev, crev;
1207
1208         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1209                 return -EINVAL;
1210
1211         switch (crev) {
1212         case 1:
1213                 return -EINVAL;
1214         case 2:
1215                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1216                 args.v2.ucVoltageMode = 0;
1217                 args.v2.usVoltageLevel = 0;
1218
1219                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1220
1221                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1222                 break;
1223         case 3:
1224                 args.v3.ucVoltageType = voltage_type;
1225                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1226                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1227
1228                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1229
1230                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1231                 break;
1232         default:
1233                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1234                 return -EINVAL;
1235         }
1236
1237         return 0;
1238 }
1239
1240 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1241                                                       u16 *voltage,
1242                                                       u16 leakage_idx)
1243 {
1244         return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1245 }
1246
1247 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1248                                  u16 voltage_level,
1249                                  u8 voltage_type)
1250 {
1251         union set_voltage args;
1252         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1253         u8 frev, crev, volt_index = voltage_level;
1254
1255         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1256                 return;
1257
1258         /* 0xff01 is a flag rather then an actual voltage */
1259         if (voltage_level == 0xff01)
1260                 return;
1261
1262         switch (crev) {
1263         case 1:
1264                 args.v1.ucVoltageType = voltage_type;
1265                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1266                 args.v1.ucVoltageIndex = volt_index;
1267                 break;
1268         case 2:
1269                 args.v2.ucVoltageType = voltage_type;
1270                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1271                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1272                 break;
1273         case 3:
1274                 args.v3.ucVoltageType = voltage_type;
1275                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1276                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1277                 break;
1278         default:
1279                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1280                 return;
1281         }
1282
1283         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1284 }
1285
1286 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1287                                               u16 *leakage_id)
1288 {
1289         union set_voltage args;
1290         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1291         u8 frev, crev;
1292
1293         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1294                 return -EINVAL;
1295
1296         switch (crev) {
1297         case 3:
1298         case 4:
1299                 args.v3.ucVoltageType = 0;
1300                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1301                 args.v3.usVoltageLevel = 0;
1302
1303                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1304
1305                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1306                 break;
1307         default:
1308                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1309                 return -EINVAL;
1310         }
1311
1312         return 0;
1313 }
1314
1315 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1316                                                              u16 *vddc, u16 *vddci,
1317                                                              u16 virtual_voltage_id,
1318                                                              u16 vbios_voltage_id)
1319 {
1320         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1321         u8 frev, crev;
1322         u16 data_offset, size;
1323         int i, j;
1324         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1325         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1326
1327         *vddc = 0;
1328         *vddci = 0;
1329
1330         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1331                                     &frev, &crev, &data_offset))
1332                 return -EINVAL;
1333
1334         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1335                 (adev->mode_info.atom_context->bios + data_offset);
1336
1337         switch (frev) {
1338         case 1:
1339                 return -EINVAL;
1340         case 2:
1341                 switch (crev) {
1342                 case 1:
1343                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1344                                 return -EINVAL;
1345                         leakage_bin = (u16 *)
1346                                 (adev->mode_info.atom_context->bios + data_offset +
1347                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1348                         vddc_id_buf = (u16 *)
1349                                 (adev->mode_info.atom_context->bios + data_offset +
1350                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1351                         vddc_buf = (u16 *)
1352                                 (adev->mode_info.atom_context->bios + data_offset +
1353                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1354                         vddci_id_buf = (u16 *)
1355                                 (adev->mode_info.atom_context->bios + data_offset +
1356                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1357                         vddci_buf = (u16 *)
1358                                 (adev->mode_info.atom_context->bios + data_offset +
1359                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1360
1361                         if (profile->ucElbVDDC_Num > 0) {
1362                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1363                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1364                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1365                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1366                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1367                                                                 break;
1368                                                         }
1369                                                 }
1370                                                 break;
1371                                         }
1372                                 }
1373                         }
1374                         if (profile->ucElbVDDCI_Num > 0) {
1375                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1376                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1377                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1378                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1379                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1380                                                                 break;
1381                                                         }
1382                                                 }
1383                                                 break;
1384                                         }
1385                                 }
1386                         }
1387                         break;
1388                 default:
1389                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1390                         return -EINVAL;
1391                 }
1392                 break;
1393         default:
1394                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1395                 return -EINVAL;
1396         }
1397
1398         return 0;
1399 }
1400
1401 union get_voltage_info {
1402         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1403         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1404 };
1405
1406 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1407                                     u16 virtual_voltage_id,
1408                                     u16 *voltage)
1409 {
1410         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1411         u32 entry_id;
1412         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1413         union get_voltage_info args;
1414
1415         for (entry_id = 0; entry_id < count; entry_id++) {
1416                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1417                     virtual_voltage_id)
1418                         break;
1419         }
1420
1421         if (entry_id >= count)
1422                 return -EINVAL;
1423
1424         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1425         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1426         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1427         args.in.ulSCLKFreq =
1428                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1429
1430         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1431
1432         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1433
1434         return 0;
1435 }
1436
1437 union voltage_object_info {
1438         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1439         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1440         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1441 };
1442
1443 union voltage_object {
1444         struct _ATOM_VOLTAGE_OBJECT v1;
1445         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1446         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1447 };
1448
1449
1450 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1451                                                                         u8 voltage_type, u8 voltage_mode)
1452 {
1453         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1454         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1455         u8 *start = (u8*)v3;
1456
1457         while (offset < size) {
1458                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1459                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1460                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1461                         return vo;
1462                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1463         }
1464         return NULL;
1465 }
1466
1467 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1468                               u8 voltage_type,
1469                               u8 *svd_gpio_id, u8 *svc_gpio_id)
1470 {
1471         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1472         u8 frev, crev;
1473         u16 data_offset, size;
1474         union voltage_object_info *voltage_info;
1475         union voltage_object *voltage_object = NULL;
1476
1477         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1478                                    &frev, &crev, &data_offset)) {
1479                 voltage_info = (union voltage_object_info *)
1480                         (adev->mode_info.atom_context->bios + data_offset);
1481
1482                 switch (frev) {
1483                 case 3:
1484                         switch (crev) {
1485                         case 1:
1486                                 voltage_object = (union voltage_object *)
1487                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1488                                                                       voltage_type,
1489                                                                       VOLTAGE_OBJ_SVID2);
1490                                 if (voltage_object) {
1491                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1492                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1493                                 } else {
1494                                         return -EINVAL;
1495                                 }
1496                                 break;
1497                         default:
1498                                 DRM_ERROR("unknown voltage object table\n");
1499                                 return -EINVAL;
1500                         }
1501                         break;
1502                 default:
1503                         DRM_ERROR("unknown voltage object table\n");
1504                         return -EINVAL;
1505                 }
1506
1507         }
1508         return 0;
1509 }
1510
1511 bool
1512 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1513                                 u8 voltage_type, u8 voltage_mode)
1514 {
1515         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1516         u8 frev, crev;
1517         u16 data_offset, size;
1518         union voltage_object_info *voltage_info;
1519
1520         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1521                                    &frev, &crev, &data_offset)) {
1522                 voltage_info = (union voltage_object_info *)
1523                         (adev->mode_info.atom_context->bios + data_offset);
1524
1525                 switch (frev) {
1526                 case 3:
1527                         switch (crev) {
1528                         case 1:
1529                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1530                                                                   voltage_type, voltage_mode))
1531                                         return true;
1532                                 break;
1533                         default:
1534                                 DRM_ERROR("unknown voltage object table\n");
1535                                 return false;
1536                         }
1537                         break;
1538                 default:
1539                         DRM_ERROR("unknown voltage object table\n");
1540                         return false;
1541                 }
1542
1543         }
1544         return false;
1545 }
1546
1547 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1548                                       u8 voltage_type, u8 voltage_mode,
1549                                       struct atom_voltage_table *voltage_table)
1550 {
1551         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1552         u8 frev, crev;
1553         u16 data_offset, size;
1554         int i;
1555         union voltage_object_info *voltage_info;
1556         union voltage_object *voltage_object = NULL;
1557
1558         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1559                                    &frev, &crev, &data_offset)) {
1560                 voltage_info = (union voltage_object_info *)
1561                         (adev->mode_info.atom_context->bios + data_offset);
1562
1563                 switch (frev) {
1564                 case 3:
1565                         switch (crev) {
1566                         case 1:
1567                                 voltage_object = (union voltage_object *)
1568                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1569                                                                       voltage_type, voltage_mode);
1570                                 if (voltage_object) {
1571                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1572                                                 &voltage_object->v3.asGpioVoltageObj;
1573                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1574                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1575                                                 return -EINVAL;
1576                                         lut = &gpio->asVolGpioLut[0];
1577                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1578                                                 voltage_table->entries[i].value =
1579                                                         le16_to_cpu(lut->usVoltageValue);
1580                                                 voltage_table->entries[i].smio_low =
1581                                                         le32_to_cpu(lut->ulVoltageId);
1582                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1583                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1584                                         }
1585                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1586                                         voltage_table->count = gpio->ucGpioEntryNum;
1587                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1588                                         return 0;
1589                                 }
1590                                 break;
1591                         default:
1592                                 DRM_ERROR("unknown voltage object table\n");
1593                                 return -EINVAL;
1594                         }
1595                         break;
1596                 default:
1597                         DRM_ERROR("unknown voltage object table\n");
1598                         return -EINVAL;
1599                 }
1600         }
1601         return -EINVAL;
1602 }
1603
1604 union vram_info {
1605         struct _ATOM_VRAM_INFO_V3 v1_3;
1606         struct _ATOM_VRAM_INFO_V4 v1_4;
1607         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1608 };
1609
1610 #define MEM_ID_MASK           0xff000000
1611 #define MEM_ID_SHIFT          24
1612 #define CLOCK_RANGE_MASK      0x00ffffff
1613 #define CLOCK_RANGE_SHIFT     0
1614 #define LOW_NIBBLE_MASK       0xf
1615 #define DATA_EQU_PREV         0
1616 #define DATA_FROM_TABLE       4
1617
1618 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1619                                       u8 module_index,
1620                                       struct atom_mc_reg_table *reg_table)
1621 {
1622         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1623         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1624         u32 i = 0, j;
1625         u16 data_offset, size;
1626         union vram_info *vram_info;
1627
1628         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1629
1630         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1631                                    &frev, &crev, &data_offset)) {
1632                 vram_info = (union vram_info *)
1633                         (adev->mode_info.atom_context->bios + data_offset);
1634                 switch (frev) {
1635                 case 1:
1636                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1637                         return -EINVAL;
1638                 case 2:
1639                         switch (crev) {
1640                         case 1:
1641                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1642                                         ATOM_INIT_REG_BLOCK *reg_block =
1643                                                 (ATOM_INIT_REG_BLOCK *)
1644                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1645                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1646                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1647                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1648                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1649                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1650                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1651                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1652                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1653                                                 return -EINVAL;
1654                                         while (i < num_entries) {
1655                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1656                                                         break;
1657                                                 reg_table->mc_reg_address[i].s1 =
1658                                                         (u16)(le16_to_cpu(format->usRegIndex));
1659                                                 reg_table->mc_reg_address[i].pre_reg_data =
1660                                                         (u8)(format->ucPreRegDataLength);
1661                                                 i++;
1662                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1663                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1664                                         }
1665                                         reg_table->last = i;
1666                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1667                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1668                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1669                                                                 >> MEM_ID_SHIFT);
1670                                                 if (module_index == t_mem_id) {
1671                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1672                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1673                                                                       >> CLOCK_RANGE_SHIFT);
1674                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1675                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1676                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1677                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1678                                                                         j++;
1679                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1680                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1681                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1682                                                                 }
1683                                                         }
1684                                                         num_ranges++;
1685                                                 }
1686                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1687                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1688                                         }
1689                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1690                                                 return -EINVAL;
1691                                         reg_table->num_entries = num_ranges;
1692                                 } else
1693                                         return -EINVAL;
1694                                 break;
1695                         default:
1696                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1697                                 return -EINVAL;
1698                         }
1699                         break;
1700                 default:
1701                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1702                         return -EINVAL;
1703                 }
1704                 return 0;
1705         }
1706         return -EINVAL;
1707 }
1708
1709 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1710 {
1711         int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1712         u8 frev, crev;
1713         u16 data_offset, size;
1714
1715         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1716                                           &frev, &crev, &data_offset))
1717                 return true;
1718
1719         return false;
1720 }
1721
1722 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1723 {
1724         uint32_t bios_6_scratch;
1725
1726         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1727
1728         if (lock) {
1729                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1730                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1731         } else {
1732                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1733                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1734         }
1735
1736         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1737 }
1738
1739 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1740 {
1741         uint32_t bios_2_scratch, bios_6_scratch;
1742
1743         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1744         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1745
1746         /* let the bios control the backlight */
1747         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1748
1749         /* tell the bios not to handle mode switching */
1750         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1751
1752         /* clear the vbios dpms state */
1753         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1754
1755         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1756         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1757 }
1758
1759 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1760 {
1761         int i;
1762
1763         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1764                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1765 }
1766
1767 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1768 {
1769         int i;
1770
1771         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1772                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1773 }
1774
1775 /* Atom needs data in little endian format so swap as appropriate when copying
1776  * data to or from atom. Note that atom operates on dw units.
1777  *
1778  * Use to_le=true when sending data to atom and provide at least
1779  * ALIGN(num_bytes,4) bytes in the dst buffer.
1780  *
1781  * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1782  * byes in the src buffer.
1783  */
1784 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1785 {
1786 #ifdef __BIG_ENDIAN
1787         u32 src_tmp[5], dst_tmp[5];
1788         int i;
1789         u8 align_num_bytes = ALIGN(num_bytes, 4);
1790
1791         if (to_le) {
1792                 memcpy(src_tmp, src, num_bytes);
1793                 for (i = 0; i < align_num_bytes / 4; i++)
1794                         dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1795                 memcpy(dst, dst_tmp, align_num_bytes);
1796         } else {
1797                 memcpy(src_tmp, src, align_num_bytes);
1798                 for (i = 0; i < align_num_bytes / 4; i++)
1799                         dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1800                 memcpy(dst, dst_tmp, num_bytes);
1801         }
1802 #else
1803         memcpy(dst, src, num_bytes);
1804 #endif
1805 }