2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/fdtable.h>
25 #include <linux/uaccess.h>
26 #include <linux/firmware.h>
29 #include "amdgpu_amdkfd.h"
30 #include "amdgpu_ucode.h"
32 #include "gca/gfx_8_0_sh_mask.h"
33 #include "gca/gfx_8_0_d.h"
34 #include "gca/gfx_8_0_enum.h"
35 #include "oss/oss_3_0_sh_mask.h"
36 #include "oss/oss_3_0_d.h"
37 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gmc/gmc_8_1_d.h"
39 #include "vi_structs.h"
42 enum hqd_dequeue_request_type {
48 struct cik_sdma_rlc_registers;
51 * Register access functions
54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
55 uint32_t sh_mem_config,
56 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
57 uint32_t sh_mem_bases);
58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
60 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
61 uint32_t hpd_size, uint64_t hpd_gpu_addr);
62 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
63 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
64 uint32_t queue_id, uint32_t __user *wptr,
65 uint32_t wptr_shift, uint32_t wptr_mask,
66 struct mm_struct *mm);
67 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
68 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
69 uint32_t pipe_id, uint32_t queue_id);
70 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
71 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
72 enum kfd_preempt_type reset_type,
73 unsigned int utimeout, uint32_t pipe_id,
75 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
76 unsigned int utimeout);
77 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
78 static int kgd_address_watch_disable(struct kgd_dev *kgd);
79 static int kgd_address_watch_execute(struct kgd_dev *kgd,
80 unsigned int watch_point_id,
84 static int kgd_wave_control_execute(struct kgd_dev *kgd,
85 uint32_t gfx_index_val,
87 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
88 unsigned int watch_point_id,
89 unsigned int reg_offset);
91 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
93 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
95 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
96 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
97 static void set_scratch_backing_va(struct kgd_dev *kgd,
98 uint64_t va, uint32_t vmid);
100 /* Because of REG_GET_FIELD() being used, we put this function in the
101 * asic specific file.
103 static int get_tile_config(struct kgd_dev *kgd,
104 struct tile_config *config)
106 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
108 config->gb_addr_config = adev->gfx.config.gb_addr_config;
109 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
110 MC_ARB_RAMCFG, NOOFBANK);
111 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
112 MC_ARB_RAMCFG, NOOFRANKS);
114 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
115 config->num_tile_configs =
116 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
117 config->macro_tile_config_ptr =
118 adev->gfx.config.macrotile_mode_array;
119 config->num_macro_tile_configs =
120 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
125 static const struct kfd2kgd_calls kfd2kgd = {
126 .init_gtt_mem_allocation = alloc_gtt_mem,
127 .free_gtt_mem = free_gtt_mem,
128 .get_vmem_size = get_vmem_size,
129 .get_gpu_clock_counter = get_gpu_clock_counter,
130 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
131 .program_sh_mem_settings = kgd_program_sh_mem_settings,
132 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
133 .init_pipeline = kgd_init_pipeline,
134 .init_interrupts = kgd_init_interrupts,
135 .hqd_load = kgd_hqd_load,
136 .hqd_sdma_load = kgd_hqd_sdma_load,
137 .hqd_is_occupied = kgd_hqd_is_occupied,
138 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
139 .hqd_destroy = kgd_hqd_destroy,
140 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
141 .address_watch_disable = kgd_address_watch_disable,
142 .address_watch_execute = kgd_address_watch_execute,
143 .wave_control_execute = kgd_wave_control_execute,
144 .address_watch_get_offset = kgd_address_watch_get_offset,
145 .get_atc_vmid_pasid_mapping_pasid =
146 get_atc_vmid_pasid_mapping_pasid,
147 .get_atc_vmid_pasid_mapping_valid =
148 get_atc_vmid_pasid_mapping_valid,
149 .write_vmid_invalidate_request = write_vmid_invalidate_request,
150 .get_fw_version = get_fw_version,
151 .set_scratch_backing_va = set_scratch_backing_va,
152 .get_tile_config = get_tile_config,
155 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
157 return (struct kfd2kgd_calls *)&kfd2kgd;
160 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
162 return (struct amdgpu_device *)kgd;
165 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
166 uint32_t queue, uint32_t vmid)
168 struct amdgpu_device *adev = get_amdgpu_device(kgd);
169 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
171 mutex_lock(&adev->srbm_mutex);
172 WREG32(mmSRBM_GFX_CNTL, value);
175 static void unlock_srbm(struct kgd_dev *kgd)
177 struct amdgpu_device *adev = get_amdgpu_device(kgd);
179 WREG32(mmSRBM_GFX_CNTL, 0);
180 mutex_unlock(&adev->srbm_mutex);
183 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
186 struct amdgpu_device *adev = get_amdgpu_device(kgd);
188 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
189 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
191 lock_srbm(kgd, mec, pipe, queue_id, 0);
194 static void release_queue(struct kgd_dev *kgd)
199 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
200 uint32_t sh_mem_config,
201 uint32_t sh_mem_ape1_base,
202 uint32_t sh_mem_ape1_limit,
203 uint32_t sh_mem_bases)
205 struct amdgpu_device *adev = get_amdgpu_device(kgd);
207 lock_srbm(kgd, 0, 0, 0, vmid);
209 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
210 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
211 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
212 WREG32(mmSH_MEM_BASES, sh_mem_bases);
217 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
220 struct amdgpu_device *adev = get_amdgpu_device(kgd);
223 * We have to assume that there is no outstanding mapping.
224 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
225 * a mapping is in progress or because a mapping finished
226 * and the SW cleared it.
227 * So the protocol is to always wait & clear.
229 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
230 ATC_VMID0_PASID_MAPPING__VALID_MASK;
232 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
234 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
236 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
238 /* Mapping vmid to pasid also for IH block */
239 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
244 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
245 uint32_t hpd_size, uint64_t hpd_gpu_addr)
247 /* amdgpu owns the per-pipe state */
251 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
253 struct amdgpu_device *adev = get_amdgpu_device(kgd);
257 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
258 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
260 lock_srbm(kgd, mec, pipe, 0, 0);
262 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
269 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
274 static inline struct vi_mqd *get_mqd(void *mqd)
276 return (struct vi_mqd *)mqd;
279 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
281 return (struct cik_sdma_rlc_registers *)mqd;
284 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
285 uint32_t queue_id, uint32_t __user *wptr,
286 uint32_t wptr_shift, uint32_t wptr_mask,
287 struct mm_struct *mm)
289 struct amdgpu_device *adev = get_amdgpu_device(kgd);
292 uint32_t reg, wptr_val, data;
296 acquire_queue(kgd, pipe_id, queue_id);
298 /* HIQ is set during driver init period with vmid set to 0*/
299 if (m->cp_hqd_vmid == 0) {
300 uint32_t value, mec, pipe;
302 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
303 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
305 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
306 mec, pipe, queue_id);
307 value = RREG32(mmRLC_CP_SCHEDULERS);
308 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
309 ((mec << 5) | (pipe << 3) | queue_id | 0x80));
310 WREG32(mmRLC_CP_SCHEDULERS, value);
313 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
314 mqd_hqd = &m->cp_mqd_base_addr_lo;
316 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
317 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
319 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
320 * This is safe since EOP RPTR==WPTR for any inactive HQD
321 * on ASICs that do not support context-save.
322 * EOP writes/reads can start anywhere in the ring.
324 if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
325 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
326 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
327 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
330 for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
331 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
333 /* Copy userspace write pointer value to register.
334 * Activate doorbell logic to monitor subsequent changes.
336 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
337 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
338 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
340 if (read_user_wptr(mm, wptr, wptr_val))
341 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
343 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
344 WREG32(mmCP_HQD_ACTIVE, data);
351 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
356 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
357 uint32_t pipe_id, uint32_t queue_id)
359 struct amdgpu_device *adev = get_amdgpu_device(kgd);
364 acquire_queue(kgd, pipe_id, queue_id);
365 act = RREG32(mmCP_HQD_ACTIVE);
367 low = lower_32_bits(queue_address >> 8);
368 high = upper_32_bits(queue_address >> 8);
370 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
371 high == RREG32(mmCP_HQD_PQ_BASE_HI))
378 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
380 struct amdgpu_device *adev = get_amdgpu_device(kgd);
381 struct cik_sdma_rlc_registers *m;
382 uint32_t sdma_base_addr;
383 uint32_t sdma_rlc_rb_cntl;
385 m = get_sdma_mqd(mqd);
386 sdma_base_addr = get_sdma_base_addr(m);
388 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
390 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
396 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
397 enum kfd_preempt_type reset_type,
398 unsigned int utimeout, uint32_t pipe_id,
401 struct amdgpu_device *adev = get_amdgpu_device(kgd);
403 enum hqd_dequeue_request_type type;
404 unsigned long flags, end_jiffies;
406 struct vi_mqd *m = get_mqd(mqd);
408 acquire_queue(kgd, pipe_id, queue_id);
410 if (m->cp_hqd_vmid == 0)
411 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
413 switch (reset_type) {
414 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
417 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
425 /* Workaround: If IQ timer is active and the wait time is close to or
426 * equal to 0, dequeueing is not safe. Wait until either the wait time
427 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
428 * cleared before continuing. Also, ensure wait times are set to at
431 local_irq_save(flags);
433 retry = 5000; /* wait for 500 usecs at maximum */
435 temp = RREG32(mmCP_HQD_IQ_TIMER);
436 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
437 pr_debug("HW is processing IQ\n");
440 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
441 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
442 == 3) /* SEM-rearm is safe */
444 /* Wait time 3 is safe for CP, but our MMIO read/write
445 * time is close to 1 microsecond, so check for 10 to
446 * leave more buffer room
448 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
451 pr_debug("IQ timer is active\n");
456 pr_err("CP HQD IQ timer status time out\n");
464 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
465 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
467 pr_debug("Dequeue request is pending\n");
470 pr_err("CP HQD dequeue request time out\n");
476 local_irq_restore(flags);
479 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
481 end_jiffies = (utimeout * HZ / 1000) + jiffies;
483 temp = RREG32(mmCP_HQD_ACTIVE);
484 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
486 if (time_after(jiffies, end_jiffies)) {
487 pr_err("cp queue preemption time out.\n");
491 usleep_range(500, 1000);
498 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
499 unsigned int utimeout)
501 struct amdgpu_device *adev = get_amdgpu_device(kgd);
502 struct cik_sdma_rlc_registers *m;
503 uint32_t sdma_base_addr;
505 int timeout = utimeout;
507 m = get_sdma_mqd(mqd);
508 sdma_base_addr = get_sdma_base_addr(m);
510 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
511 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
512 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
515 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
516 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
524 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
525 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
526 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
527 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
532 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
536 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
538 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
539 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
542 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
546 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
548 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
549 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
552 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
554 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
556 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
559 static int kgd_address_watch_disable(struct kgd_dev *kgd)
564 static int kgd_address_watch_execute(struct kgd_dev *kgd,
565 unsigned int watch_point_id,
573 static int kgd_wave_control_execute(struct kgd_dev *kgd,
574 uint32_t gfx_index_val,
577 struct amdgpu_device *adev = get_amdgpu_device(kgd);
580 mutex_lock(&adev->grbm_idx_mutex);
582 WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
583 WREG32(mmSQ_CMD, sq_cmd);
585 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
586 INSTANCE_BROADCAST_WRITES, 1);
587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
588 SH_BROADCAST_WRITES, 1);
589 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
590 SE_BROADCAST_WRITES, 1);
592 WREG32(mmGRBM_GFX_INDEX, data);
593 mutex_unlock(&adev->grbm_idx_mutex);
598 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
599 unsigned int watch_point_id,
600 unsigned int reg_offset)
605 static void set_scratch_backing_va(struct kgd_dev *kgd,
606 uint64_t va, uint32_t vmid)
608 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
610 lock_srbm(kgd, 0, 0, 0, vmid);
611 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
615 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
617 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
618 const union amdgpu_firmware_header *hdr;
624 hdr = (const union amdgpu_firmware_header *)
625 adev->gfx.pfp_fw->data;
629 hdr = (const union amdgpu_firmware_header *)
630 adev->gfx.me_fw->data;
634 hdr = (const union amdgpu_firmware_header *)
635 adev->gfx.ce_fw->data;
638 case KGD_ENGINE_MEC1:
639 hdr = (const union amdgpu_firmware_header *)
640 adev->gfx.mec_fw->data;
643 case KGD_ENGINE_MEC2:
644 hdr = (const union amdgpu_firmware_header *)
645 adev->gfx.mec2_fw->data;
649 hdr = (const union amdgpu_firmware_header *)
650 adev->gfx.rlc_fw->data;
653 case KGD_ENGINE_SDMA1:
654 hdr = (const union amdgpu_firmware_header *)
655 adev->sdma.instance[0].fw->data;
658 case KGD_ENGINE_SDMA2:
659 hdr = (const union amdgpu_firmware_header *)
660 adev->sdma.instance[1].fw->data;
670 /* Only 12 bit in use*/
671 return hdr->common.ucode_version;