GNU Linux-libre 4.19.268-gnu1
[releases.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include <linux/module.h>
29
30 const struct kgd2kfd_calls *kgd2kfd;
31 bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
32
33 static const unsigned int compute_vmid_bitmap = 0xFF00;
34
35 int amdgpu_amdkfd_init(void)
36 {
37         int ret;
38
39 #if defined(CONFIG_HSA_AMD_MODULE)
40         int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
41
42         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
43
44         if (kgd2kfd_init_p == NULL)
45                 return -ENOENT;
46
47         ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
48         if (ret) {
49                 symbol_put(kgd2kfd_init);
50                 kgd2kfd = NULL;
51         }
52
53
54 #elif defined(CONFIG_HSA_AMD)
55
56         ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
57         if (ret)
58                 kgd2kfd = NULL;
59
60 #else
61         kgd2kfd = NULL;
62         ret = -ENOENT;
63 #endif
64
65 #if defined(CONFIG_HSA_AMD_MODULE) || defined(CONFIG_HSA_AMD)
66         amdgpu_amdkfd_gpuvm_init_mem_limits();
67 #endif
68
69         return ret;
70 }
71
72 void amdgpu_amdkfd_fini(void)
73 {
74         if (kgd2kfd) {
75                 kgd2kfd->exit();
76                 symbol_put(kgd2kfd_init);
77         }
78 }
79
80 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
81 {
82         const struct kfd2kgd_calls *kfd2kgd;
83
84         if (!kgd2kfd)
85                 return;
86
87         switch (adev->asic_type) {
88 #ifdef CONFIG_DRM_AMDGPU_CIK
89         case CHIP_KAVERI:
90         case CHIP_HAWAII:
91                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
92                 break;
93 #endif
94         case CHIP_CARRIZO:
95         case CHIP_TONGA:
96         case CHIP_FIJI:
97         case CHIP_POLARIS10:
98         case CHIP_POLARIS11:
99                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
100                 break;
101         case CHIP_VEGA10:
102         case CHIP_RAVEN:
103                 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
104                 break;
105         default:
106                 dev_info(adev->dev, "kfd not supported on this ASIC\n");
107                 return;
108         }
109
110         adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
111                                    adev->pdev, kfd2kgd);
112 }
113
114 /**
115  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
116  *                                setup amdkfd
117  *
118  * @adev: amdgpu_device pointer
119  * @aperture_base: output returning doorbell aperture base physical address
120  * @aperture_size: output returning doorbell aperture size in bytes
121  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
122  *
123  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
124  * takes doorbells required for its own rings and reports the setup to amdkfd.
125  * amdgpu reserved doorbells are at the start of the doorbell aperture.
126  */
127 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
128                                          phys_addr_t *aperture_base,
129                                          size_t *aperture_size,
130                                          size_t *start_offset)
131 {
132         /*
133          * The first num_doorbells are used by amdgpu.
134          * amdkfd takes whatever's left in the aperture.
135          */
136         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
137                 *aperture_base = adev->doorbell.base;
138                 *aperture_size = adev->doorbell.size;
139                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
140         } else {
141                 *aperture_base = 0;
142                 *aperture_size = 0;
143                 *start_offset = 0;
144         }
145 }
146
147 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
148 {
149         int i;
150         int last_valid_bit;
151         if (adev->kfd) {
152                 struct kgd2kfd_shared_resources gpu_resources = {
153                         .compute_vmid_bitmap = compute_vmid_bitmap,
154                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
155                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
156                         .gpuvm_size = min(adev->vm_manager.max_pfn
157                                           << AMDGPU_GPU_PAGE_SHIFT,
158                                           AMDGPU_VA_HOLE_START),
159                         .drm_render_minor = adev->ddev->render->index
160                 };
161
162                 /* this is going to have a few of the MSBs set that we need to
163                  * clear */
164                 bitmap_complement(gpu_resources.queue_bitmap,
165                                   adev->gfx.mec.queue_bitmap,
166                                   KGD_MAX_QUEUES);
167
168                 /* remove the KIQ bit as well */
169                 if (adev->gfx.kiq.ring.ready)
170                         clear_bit(amdgpu_gfx_queue_to_bit(adev,
171                                                           adev->gfx.kiq.ring.me - 1,
172                                                           adev->gfx.kiq.ring.pipe,
173                                                           adev->gfx.kiq.ring.queue),
174                                   gpu_resources.queue_bitmap);
175
176                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
177                  * nbits is not compile time constant */
178                 last_valid_bit = 1 /* only first MEC can have compute queues */
179                                 * adev->gfx.mec.num_pipe_per_mec
180                                 * adev->gfx.mec.num_queue_per_pipe;
181                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
182                         clear_bit(i, gpu_resources.queue_bitmap);
183
184                 amdgpu_doorbell_get_kfd_info(adev,
185                                 &gpu_resources.doorbell_physical_address,
186                                 &gpu_resources.doorbell_aperture_size,
187                                 &gpu_resources.doorbell_start_offset);
188                 if (adev->asic_type >= CHIP_VEGA10) {
189                         /* On SOC15 the BIF is involved in routing
190                          * doorbells using the low 12 bits of the
191                          * address. Communicate the assignments to
192                          * KFD. KFD uses two doorbell pages per
193                          * process in case of 64-bit doorbells so we
194                          * can use each doorbell assignment twice.
195                          */
196                         gpu_resources.sdma_doorbell[0][0] =
197                                 AMDGPU_DOORBELL64_sDMA_ENGINE0;
198                         gpu_resources.sdma_doorbell[0][1] =
199                                 AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
200                         gpu_resources.sdma_doorbell[1][0] =
201                                 AMDGPU_DOORBELL64_sDMA_ENGINE1;
202                         gpu_resources.sdma_doorbell[1][1] =
203                                 AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
204                         /* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
205                          * SDMA, IH and VCN. So don't use them for the CP.
206                          */
207                         gpu_resources.reserved_doorbell_mask = 0x1f0;
208                         gpu_resources.reserved_doorbell_val  = 0x0f0;
209                 }
210
211                 kgd2kfd->device_init(adev->kfd, &gpu_resources);
212         }
213 }
214
215 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
216 {
217         if (adev->kfd) {
218                 kgd2kfd->device_exit(adev->kfd);
219                 adev->kfd = NULL;
220         }
221 }
222
223 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
224                 const void *ih_ring_entry)
225 {
226         if (adev->kfd)
227                 kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
228 }
229
230 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
231 {
232         if (adev->kfd)
233                 kgd2kfd->suspend(adev->kfd);
234 }
235
236 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
237 {
238         int r = 0;
239
240         if (adev->kfd)
241                 r = kgd2kfd->resume(adev->kfd);
242
243         return r;
244 }
245
246 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
247 {
248         int r = 0;
249
250         if (adev->kfd)
251                 r = kgd2kfd->pre_reset(adev->kfd);
252
253         return r;
254 }
255
256 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
257 {
258         int r = 0;
259
260         if (adev->kfd)
261                 r = kgd2kfd->post_reset(adev->kfd);
262
263         return r;
264 }
265
266 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
267 {
268         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
269
270         amdgpu_device_gpu_recover(adev, NULL, false);
271 }
272
273 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
274                         void **mem_obj, uint64_t *gpu_addr,
275                         void **cpu_ptr, bool mqd_gfx9)
276 {
277         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
278         struct amdgpu_bo *bo = NULL;
279         struct amdgpu_bo_param bp;
280         int r;
281         void *cpu_ptr_tmp = NULL;
282
283         memset(&bp, 0, sizeof(bp));
284         bp.size = size;
285         bp.byte_align = PAGE_SIZE;
286         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
287         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
288         bp.type = ttm_bo_type_kernel;
289         bp.resv = NULL;
290
291         if (mqd_gfx9)
292                 bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
293
294         r = amdgpu_bo_create(adev, &bp, &bo);
295         if (r) {
296                 dev_err(adev->dev,
297                         "failed to allocate BO for amdkfd (%d)\n", r);
298                 return r;
299         }
300
301         /* map the buffer */
302         r = amdgpu_bo_reserve(bo, true);
303         if (r) {
304                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
305                 goto allocate_mem_reserve_bo_failed;
306         }
307
308         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
309         if (r) {
310                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
311                 goto allocate_mem_pin_bo_failed;
312         }
313
314         r = amdgpu_ttm_alloc_gart(&bo->tbo);
315         if (r) {
316                 dev_err(adev->dev, "%p bind failed\n", bo);
317                 goto allocate_mem_kmap_bo_failed;
318         }
319
320         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
321         if (r) {
322                 dev_err(adev->dev,
323                         "(%d) failed to map bo to kernel for amdkfd\n", r);
324                 goto allocate_mem_kmap_bo_failed;
325         }
326
327         *mem_obj = bo;
328         *gpu_addr = amdgpu_bo_gpu_offset(bo);
329         *cpu_ptr = cpu_ptr_tmp;
330
331         amdgpu_bo_unreserve(bo);
332
333         return 0;
334
335 allocate_mem_kmap_bo_failed:
336         amdgpu_bo_unpin(bo);
337 allocate_mem_pin_bo_failed:
338         amdgpu_bo_unreserve(bo);
339 allocate_mem_reserve_bo_failed:
340         amdgpu_bo_unref(&bo);
341
342         return r;
343 }
344
345 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
346 {
347         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
348
349         amdgpu_bo_reserve(bo, true);
350         amdgpu_bo_kunmap(bo);
351         amdgpu_bo_unpin(bo);
352         amdgpu_bo_unreserve(bo);
353         amdgpu_bo_unref(&(bo));
354 }
355
356 void get_local_mem_info(struct kgd_dev *kgd,
357                         struct kfd_local_mem_info *mem_info)
358 {
359         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
360         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
361                                              ~((1ULL << 32) - 1);
362         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
363
364         memset(mem_info, 0, sizeof(*mem_info));
365         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
366                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
367                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
368                                 adev->gmc.visible_vram_size;
369         } else {
370                 mem_info->local_mem_size_public = 0;
371                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
372         }
373         mem_info->vram_width = adev->gmc.vram_width;
374
375         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
376                         &adev->gmc.aper_base, &aper_limit,
377                         mem_info->local_mem_size_public,
378                         mem_info->local_mem_size_private);
379
380         if (amdgpu_sriov_vf(adev))
381                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
382         else if (adev->powerplay.pp_funcs)
383                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
384         else
385                 mem_info->mem_clk_max = 100;
386 }
387
388 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
389 {
390         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
391
392         if (adev->gfx.funcs->get_gpu_clock_counter)
393                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
394         return 0;
395 }
396
397 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
398 {
399         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
400
401         /* the sclk is in quantas of 10kHz */
402         if (amdgpu_sriov_vf(adev))
403                 return adev->clock.default_sclk / 100;
404         else if (adev->powerplay.pp_funcs)
405                 return amdgpu_dpm_get_sclk(adev, false) / 100;
406         else
407                 return 100;
408 }
409
410 void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
411 {
412         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
413         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
414
415         memset(cu_info, 0, sizeof(*cu_info));
416         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
417                 return;
418
419         cu_info->cu_active_number = acu_info.number;
420         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
421         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
422                sizeof(acu_info.bitmap));
423         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
424         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
425         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
426         cu_info->simd_per_cu = acu_info.simd_per_cu;
427         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
428         cu_info->wave_front_size = acu_info.wave_front_size;
429         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
430         cu_info->lds_size = acu_info.lds_size;
431 }
432
433 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
434 {
435         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
436
437         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
438 }
439
440 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
441                                 uint32_t vmid, uint64_t gpu_addr,
442                                 uint32_t *ib_cmd, uint32_t ib_len)
443 {
444         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
445         struct amdgpu_job *job;
446         struct amdgpu_ib *ib;
447         struct amdgpu_ring *ring;
448         struct dma_fence *f = NULL;
449         int ret;
450
451         switch (engine) {
452         case KGD_ENGINE_MEC1:
453                 ring = &adev->gfx.compute_ring[0];
454                 break;
455         case KGD_ENGINE_SDMA1:
456                 ring = &adev->sdma.instance[0].ring;
457                 break;
458         case KGD_ENGINE_SDMA2:
459                 ring = &adev->sdma.instance[1].ring;
460                 break;
461         default:
462                 pr_err("Invalid engine in IB submission: %d\n", engine);
463                 ret = -EINVAL;
464                 goto err;
465         }
466
467         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
468         if (ret)
469                 goto err;
470
471         ib = &job->ibs[0];
472         memset(ib, 0, sizeof(struct amdgpu_ib));
473
474         ib->gpu_addr = gpu_addr;
475         ib->ptr = ib_cmd;
476         ib->length_dw = ib_len;
477         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
478         job->vmid = vmid;
479
480         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
481         if (ret) {
482                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
483                 goto err_ib_sched;
484         }
485
486         ret = dma_fence_wait(f, false);
487
488 err_ib_sched:
489         dma_fence_put(f);
490         amdgpu_job_free(job);
491 err:
492         return ret;
493 }
494
495 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
496 {
497         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
498
499         if (adev->powerplay.pp_funcs &&
500             adev->powerplay.pp_funcs->switch_power_profile)
501                 amdgpu_dpm_switch_power_profile(adev,
502                                                 PP_SMC_POWER_PROFILE_COMPUTE,
503                                                 !idle);
504 }
505
506 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
507 {
508         if (adev->kfd) {
509                 if ((1 << vmid) & compute_vmid_bitmap)
510                         return true;
511         }
512
513         return false;
514 }
515
516 #if !defined(CONFIG_HSA_AMD_MODULE) && !defined(CONFIG_HSA_AMD)
517 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
518 {
519         return false;
520 }
521
522 void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
523 {
524 }
525
526 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
527                                         struct amdgpu_vm *vm)
528 {
529 }
530
531 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
532 {
533         return NULL;
534 }
535
536 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
537 {
538         return 0;
539 }
540
541 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
542 {
543         return NULL;
544 }
545
546 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
547 {
548         return NULL;
549 }
550
551 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
552 {
553         return NULL;
554 }
555 #endif