1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx gpio driver for xps/axi_gpio IP.
5 * Copyright 2008 - 2013 Xilinx, Inc.
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/slab.h>
23 /* Register Offset Definitions */
24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */
25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
27 #define XGPIO_CHANNEL0_OFFSET 0x0
28 #define XGPIO_CHANNEL1_OFFSET 0x8
30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31 #define XGPIO_GIER_IE BIT(31)
32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
35 /* Read/Write access to the GPIO registers */
36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37 # define xgpio_readreg(offset) readl(offset)
38 # define xgpio_writereg(offset, val) writel(val, offset)
40 # define xgpio_readreg(offset) __raw_readl(offset)
41 # define xgpio_writereg(offset, val) __raw_writel(val, offset)
45 * struct xgpio_instance - Stores information about GPIO device
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
55 * @enable: GPIO IRQ enable/disable bitfield
56 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
57 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
58 * @clk: clock resource for this driver
60 struct xgpio_instance {
63 DECLARE_BITMAP(hw_map, 64);
64 DECLARE_BITMAP(sw_map, 64);
65 DECLARE_BITMAP(state, 64);
66 DECLARE_BITMAP(last_irq_read, 64);
67 DECLARE_BITMAP(dir, 64);
68 spinlock_t gpio_lock; /* For serializing operations */
70 DECLARE_BITMAP(enable, 64);
71 DECLARE_BITMAP(rising_edge, 64);
72 DECLARE_BITMAP(falling_edge, 64);
76 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
78 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
81 static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
83 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
86 static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
88 const size_t index = BIT_WORD(bit);
89 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
91 return (map[index] >> offset) & 0xFFFFFFFFul;
94 static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
96 const size_t index = BIT_WORD(bit);
97 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
99 map[index] &= ~(0xFFFFFFFFul << offset);
100 map[index] |= (unsigned long)v << offset;
103 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
107 return XGPIO_CHANNEL0_OFFSET;
109 return XGPIO_CHANNEL1_OFFSET;
115 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
117 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
119 xgpio_set_value32(a, bit, xgpio_readreg(addr));
122 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
124 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
126 xgpio_writereg(addr, xgpio_get_value32(a, bit));
129 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
131 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
133 for (bit = 0; bit <= lastbit ; bit += 32)
134 xgpio_read_ch(chip, reg, bit, a);
137 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
139 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
141 for (bit = 0; bit <= lastbit ; bit += 32)
142 xgpio_write_ch(chip, reg, bit, a);
146 * xgpio_get - Read the specified signal of the GPIO device.
147 * @gc: Pointer to gpio_chip device structure.
148 * @gpio: GPIO signal number.
150 * This function reads the specified signal of the GPIO device.
153 * 0 if direction of GPIO signals is set as input otherwise it
154 * returns negative error value.
156 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
158 struct xgpio_instance *chip = gpiochip_get_data(gc);
159 int bit = xgpio_to_bit(chip, gpio);
160 DECLARE_BITMAP(state, 64);
162 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
164 return test_bit(bit, state);
168 * xgpio_set - Write the specified signal of the GPIO device.
169 * @gc: Pointer to gpio_chip device structure.
170 * @gpio: GPIO signal number.
171 * @val: Value to be written to specified signal.
173 * This function writes the specified value in to the specified signal of the
176 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
179 struct xgpio_instance *chip = gpiochip_get_data(gc);
180 int bit = xgpio_to_bit(chip, gpio);
182 spin_lock_irqsave(&chip->gpio_lock, flags);
184 /* Write to GPIO signal and set its direction to output */
185 __assign_bit(bit, chip->state, val);
187 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
189 spin_unlock_irqrestore(&chip->gpio_lock, flags);
193 * xgpio_set_multiple - Write the specified signals of the GPIO device.
194 * @gc: Pointer to gpio_chip device structure.
195 * @mask: Mask of the GPIOS to modify.
196 * @bits: Value to be wrote on each GPIO
198 * This function writes the specified values into the specified signals of the
201 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
204 DECLARE_BITMAP(hw_mask, 64);
205 DECLARE_BITMAP(hw_bits, 64);
206 DECLARE_BITMAP(state, 64);
208 struct xgpio_instance *chip = gpiochip_get_data(gc);
210 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
211 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
213 spin_lock_irqsave(&chip->gpio_lock, flags);
215 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
217 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
219 bitmap_copy(chip->state, state, 64);
221 spin_unlock_irqrestore(&chip->gpio_lock, flags);
225 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
226 * @gc: Pointer to gpio_chip device structure.
227 * @gpio: GPIO signal number.
230 * 0 - if direction of GPIO signals is set as input
231 * otherwise it returns negative error value.
233 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
236 struct xgpio_instance *chip = gpiochip_get_data(gc);
237 int bit = xgpio_to_bit(chip, gpio);
239 spin_lock_irqsave(&chip->gpio_lock, flags);
241 /* Set the GPIO bit in shadow register and set direction as input */
242 __set_bit(bit, chip->dir);
243 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
245 spin_unlock_irqrestore(&chip->gpio_lock, flags);
251 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
252 * @gc: Pointer to gpio_chip device structure.
253 * @gpio: GPIO signal number.
254 * @val: Value to be written to specified signal.
256 * This function sets the direction of specified GPIO signal as output.
259 * If all GPIO signals of GPIO chip is configured as input then it returns
260 * error otherwise it returns 0.
262 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
265 struct xgpio_instance *chip = gpiochip_get_data(gc);
266 int bit = xgpio_to_bit(chip, gpio);
268 spin_lock_irqsave(&chip->gpio_lock, flags);
270 /* Write state of GPIO signal */
271 __assign_bit(bit, chip->state, val);
272 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
274 /* Clear the GPIO bit in shadow register and set direction as output */
275 __clear_bit(bit, chip->dir);
276 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
278 spin_unlock_irqrestore(&chip->gpio_lock, flags);
284 * xgpio_save_regs - Set initial values of GPIO pins
285 * @chip: Pointer to GPIO instance
287 static void xgpio_save_regs(struct xgpio_instance *chip)
289 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
290 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
293 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
297 ret = pm_runtime_get_sync(chip->parent);
299 * If the device is already active pm_runtime_get() will return 1 on
300 * success, but gpio_request still needs to return 0.
302 return ret < 0 ? ret : 0;
305 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
307 pm_runtime_put(chip->parent);
310 static int __maybe_unused xgpio_suspend(struct device *dev)
312 struct xgpio_instance *gpio = dev_get_drvdata(dev);
313 struct irq_data *data = irq_get_irq_data(gpio->irq);
316 dev_dbg(dev, "IRQ not connected\n");
317 return pm_runtime_force_suspend(dev);
320 if (!irqd_is_wakeup_set(data))
321 return pm_runtime_force_suspend(dev);
327 * xgpio_remove - Remove method for the GPIO device.
328 * @pdev: pointer to the platform device
330 * This function remove gpiochips and frees all the allocated resources.
334 static void xgpio_remove(struct platform_device *pdev)
336 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
338 pm_runtime_get_sync(&pdev->dev);
339 pm_runtime_put_noidle(&pdev->dev);
340 pm_runtime_disable(&pdev->dev);
341 clk_disable_unprepare(gpio->clk);
345 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
346 * @irq_data: per IRQ and chip data passed down to chip functions
347 * This currently does nothing, but irq_ack is unconditionally called by
348 * handle_edge_irq and therefore must be defined.
350 static void xgpio_irq_ack(struct irq_data *irq_data)
354 static int __maybe_unused xgpio_resume(struct device *dev)
356 struct xgpio_instance *gpio = dev_get_drvdata(dev);
357 struct irq_data *data = irq_get_irq_data(gpio->irq);
360 dev_dbg(dev, "IRQ not connected\n");
361 return pm_runtime_force_resume(dev);
364 if (!irqd_is_wakeup_set(data))
365 return pm_runtime_force_resume(dev);
370 static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
372 struct xgpio_instance *gpio = dev_get_drvdata(dev);
374 clk_disable(gpio->clk);
379 static int __maybe_unused xgpio_runtime_resume(struct device *dev)
381 struct xgpio_instance *gpio = dev_get_drvdata(dev);
383 return clk_enable(gpio->clk);
386 static const struct dev_pm_ops xgpio_dev_pm_ops = {
387 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
388 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
389 xgpio_runtime_resume, NULL)
393 * xgpio_irq_mask - Write the specified signal of the GPIO device.
394 * @irq_data: per IRQ and chip data passed down to chip functions
396 static void xgpio_irq_mask(struct irq_data *irq_data)
399 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
400 int irq_offset = irqd_to_hwirq(irq_data);
401 int bit = xgpio_to_bit(chip, irq_offset);
402 u32 mask = BIT(bit / 32), temp;
404 spin_lock_irqsave(&chip->gpio_lock, flags);
406 __clear_bit(bit, chip->enable);
408 if (xgpio_get_value32(chip->enable, bit) == 0) {
409 /* Disable per channel interrupt */
410 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
412 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
414 spin_unlock_irqrestore(&chip->gpio_lock, flags);
416 gpiochip_disable_irq(&chip->gc, irq_offset);
420 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
421 * @irq_data: per IRQ and chip data passed down to chip functions
423 static void xgpio_irq_unmask(struct irq_data *irq_data)
426 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
427 int irq_offset = irqd_to_hwirq(irq_data);
428 int bit = xgpio_to_bit(chip, irq_offset);
429 u32 old_enable = xgpio_get_value32(chip->enable, bit);
430 u32 mask = BIT(bit / 32), val;
432 gpiochip_enable_irq(&chip->gc, irq_offset);
434 spin_lock_irqsave(&chip->gpio_lock, flags);
436 __set_bit(bit, chip->enable);
438 if (old_enable == 0) {
439 /* Clear any existing per-channel interrupts */
440 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
442 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
444 /* Update GPIO IRQ read data before enabling interrupt*/
445 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
447 /* Enable per channel interrupt */
448 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
450 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
453 spin_unlock_irqrestore(&chip->gpio_lock, flags);
457 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
458 * @irq_data: Per IRQ and chip data passed down to chip functions
459 * @type: Interrupt type that is to be set for the gpio pin
462 * 0 if interrupt type is supported otherwise -EINVAL
464 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
466 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
467 int irq_offset = irqd_to_hwirq(irq_data);
468 int bit = xgpio_to_bit(chip, irq_offset);
471 * The Xilinx GPIO hardware provides a single interrupt status
472 * indication for any state change in a given GPIO channel (bank).
473 * Therefore, only rising edge or falling edge triggers are
476 switch (type & IRQ_TYPE_SENSE_MASK) {
477 case IRQ_TYPE_EDGE_BOTH:
478 __set_bit(bit, chip->rising_edge);
479 __set_bit(bit, chip->falling_edge);
481 case IRQ_TYPE_EDGE_RISING:
482 __set_bit(bit, chip->rising_edge);
483 __clear_bit(bit, chip->falling_edge);
485 case IRQ_TYPE_EDGE_FALLING:
486 __clear_bit(bit, chip->rising_edge);
487 __set_bit(bit, chip->falling_edge);
493 irq_set_handler_locked(irq_data, handle_edge_irq);
498 * xgpio_irqhandler - Gpio interrupt service routine
499 * @desc: Pointer to interrupt description
501 static void xgpio_irqhandler(struct irq_desc *desc)
503 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
504 struct gpio_chip *gc = &chip->gc;
505 struct irq_chip *irqchip = irq_desc_get_chip(desc);
506 DECLARE_BITMAP(rising, 64);
507 DECLARE_BITMAP(falling, 64);
508 DECLARE_BITMAP(all, 64);
513 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
514 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
516 chained_irq_enter(irqchip, desc);
518 spin_lock(&chip->gpio_lock);
520 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
522 bitmap_complement(rising, chip->last_irq_read, 64);
523 bitmap_and(rising, rising, all, 64);
524 bitmap_and(rising, rising, chip->enable, 64);
525 bitmap_and(rising, rising, chip->rising_edge, 64);
527 bitmap_complement(falling, all, 64);
528 bitmap_and(falling, falling, chip->last_irq_read, 64);
529 bitmap_and(falling, falling, chip->enable, 64);
530 bitmap_and(falling, falling, chip->falling_edge, 64);
532 bitmap_copy(chip->last_irq_read, all, 64);
533 bitmap_or(all, rising, falling, 64);
535 spin_unlock(&chip->gpio_lock);
537 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
539 for_each_set_bit(bit, all, 64) {
540 irq_offset = xgpio_from_bit(chip, bit);
541 generic_handle_domain_irq(gc->irq.domain, irq_offset);
544 chained_irq_exit(irqchip, desc);
547 static const struct irq_chip xgpio_irq_chip = {
548 .name = "gpio-xilinx",
549 .irq_ack = xgpio_irq_ack,
550 .irq_mask = xgpio_irq_mask,
551 .irq_unmask = xgpio_irq_unmask,
552 .irq_set_type = xgpio_set_irq_type,
553 .flags = IRQCHIP_IMMUTABLE,
554 GPIOCHIP_IRQ_RESOURCE_HELPERS,
558 * xgpio_probe - Probe method for the GPIO device.
559 * @pdev: pointer to the platform device
562 * It returns 0, if the driver is bound to the GPIO device, or
563 * a negative value if there is an error.
565 static int xgpio_probe(struct platform_device *pdev)
567 struct xgpio_instance *chip;
569 struct device_node *np = pdev->dev.of_node;
574 struct gpio_irq_chip *girq;
577 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
581 platform_set_drvdata(pdev, chip);
583 /* First, check if the device is dual-channel */
584 of_property_read_u32(np, "xlnx,is-dual", &is_dual);
587 memset32(width, 0, ARRAY_SIZE(width));
588 memset32(state, 0, ARRAY_SIZE(state));
589 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
591 /* Update GPIO state shadow register with default value */
592 of_property_read_u32(np, "xlnx,dout-default", &state[0]);
593 of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
595 bitmap_from_arr32(chip->state, state, 64);
597 /* Update GPIO direction shadow register with default value */
598 of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
599 of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
601 bitmap_from_arr32(chip->dir, dir, 64);
604 * Check device node and parent device node for device width
605 * and assume default width of 32
607 if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
613 if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
619 /* Setup software pin mapping */
620 bitmap_set(chip->sw_map, 0, width[0] + width[1]);
622 /* Setup hardware pin mapping */
623 bitmap_set(chip->hw_map, 0, width[0]);
624 bitmap_set(chip->hw_map, 32, width[1]);
626 spin_lock_init(&chip->gpio_lock);
629 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
630 chip->gc.parent = &pdev->dev;
631 chip->gc.direction_input = xgpio_dir_in;
632 chip->gc.direction_output = xgpio_dir_out;
633 chip->gc.get = xgpio_get;
634 chip->gc.set = xgpio_set;
635 chip->gc.request = xgpio_request;
636 chip->gc.free = xgpio_free;
637 chip->gc.set_multiple = xgpio_set_multiple;
639 chip->gc.label = dev_name(&pdev->dev);
641 chip->regs = devm_platform_ioremap_resource(pdev, 0);
642 if (IS_ERR(chip->regs)) {
643 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
644 return PTR_ERR(chip->regs);
647 chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
648 if (IS_ERR(chip->clk))
649 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
651 status = clk_prepare_enable(chip->clk);
653 dev_err(&pdev->dev, "Failed to prepare clk\n");
656 pm_runtime_get_noresume(&pdev->dev);
657 pm_runtime_set_active(&pdev->dev);
658 pm_runtime_enable(&pdev->dev);
660 xgpio_save_regs(chip);
662 chip->irq = platform_get_irq_optional(pdev, 0);
666 /* Disable per-channel interrupts */
667 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
668 /* Clear any existing per-channel interrupts */
669 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
670 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
671 /* Enable global interrupts */
672 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
674 girq = &chip->gc.irq;
675 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip);
676 girq->parent_handler = xgpio_irqhandler;
677 girq->num_parents = 1;
678 girq->parents = devm_kcalloc(&pdev->dev, 1,
679 sizeof(*girq->parents),
681 if (!girq->parents) {
685 girq->parents[0] = chip->irq;
686 girq->default_type = IRQ_TYPE_NONE;
687 girq->handler = handle_bad_irq;
690 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
692 dev_err(&pdev->dev, "failed to add GPIO chip\n");
696 pm_runtime_put(&pdev->dev);
700 pm_runtime_disable(&pdev->dev);
701 pm_runtime_put_noidle(&pdev->dev);
702 clk_disable_unprepare(chip->clk);
706 static const struct of_device_id xgpio_of_match[] = {
707 { .compatible = "xlnx,xps-gpio-1.00.a", },
708 { /* end of list */ },
711 MODULE_DEVICE_TABLE(of, xgpio_of_match);
713 static struct platform_driver xgpio_plat_driver = {
714 .probe = xgpio_probe,
715 .remove_new = xgpio_remove,
717 .name = "gpio-xilinx",
718 .of_match_table = xgpio_of_match,
719 .pm = &xgpio_dev_pm_ops,
723 static int __init xgpio_init(void)
725 return platform_driver_register(&xgpio_plat_driver);
728 subsys_initcall(xgpio_init);
730 static void __exit xgpio_exit(void)
732 platform_driver_unregister(&xgpio_plat_driver);
734 module_exit(xgpio_exit);
736 MODULE_AUTHOR("Xilinx, Inc.");
737 MODULE_DESCRIPTION("Xilinx GPIO driver");
738 MODULE_LICENSE("GPL");