2 * Driver for NEC VR4100 series General-purpose I/O Unit.
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
24 #include <linux/gpio.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/spinlock.h>
33 #include <linux/types.h>
35 #include <asm/vr41xx/giu.h>
36 #include <asm/vr41xx/irq.h>
37 #include <asm/vr41xx/vr41xx.h>
39 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
40 MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
41 MODULE_LICENSE("GPL");
43 #define GIUIOSELL 0x00
44 #define GIUIOSELH 0x02
47 #define GIUINTSTATL 0x08
48 #define GIUINTSTATH 0x0a
49 #define GIUINTENL 0x0c
50 #define GIUINTENH 0x0e
51 #define GIUINTTYPL 0x10
52 #define GIUINTTYPH 0x12
53 #define GIUINTALSELL 0x14
54 #define GIUINTALSELH 0x16
55 #define GIUINTHTSELL 0x18
56 #define GIUINTHTSELH 0x1a
57 #define GIUPODATL 0x1c
58 #define GIUPODATEN 0x1c
59 #define GIUPODATH 0x1e
63 #define GIUFEDGEINHL 0x20
64 #define GIUFEDGEINHH 0x22
65 #define GIUREDGEINHL 0x24
66 #define GIUREDGEINHH 0x26
68 #define GIUUSEUPDN 0x1e0
69 #define GIUTERMUPDN 0x1e2
71 #define GPIO_HAS_PULLUPDOWN_IO 0x0001
72 #define GPIO_HAS_OUTPUT_ENABLE 0x0002
73 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
80 static DEFINE_SPINLOCK(giu_lock);
81 static unsigned long giu_flags;
83 static void __iomem *giu_base;
84 static struct gpio_chip vr41xx_gpio_chip;
86 #define giu_read(offset) readw(giu_base + (offset))
87 #define giu_write(offset, value) writew((value), giu_base + (offset))
89 #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90 #define GIUINT_HIGH_OFFSET 16
91 #define GIUINT_HIGH_MAX 32
93 static inline u16 giu_set(u16 offset, u16 set)
97 data = giu_read(offset);
99 giu_write(offset, data);
104 static inline u16 giu_clear(u16 offset, u16 clear)
108 data = giu_read(offset);
110 giu_write(offset, data);
115 static void ack_giuint_low(struct irq_data *d)
117 giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
120 static void mask_giuint_low(struct irq_data *d)
122 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
125 static void mask_ack_giuint_low(struct irq_data *d)
129 pin = GPIO_PIN_OF_IRQ(d->irq);
130 giu_clear(GIUINTENL, 1 << pin);
131 giu_write(GIUINTSTATL, 1 << pin);
134 static void unmask_giuint_low(struct irq_data *d)
136 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
139 static unsigned int startup_giuint(struct irq_data *data)
143 ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data));
145 dev_err(vr41xx_gpio_chip.parent,
146 "unable to lock HW IRQ %lu for IRQ\n",
151 /* Satisfy the .enable semantics by unmasking the line */
152 unmask_giuint_low(data);
156 static void shutdown_giuint(struct irq_data *data)
158 mask_giuint_low(data);
159 gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
162 static struct irq_chip giuint_low_irq_chip = {
164 .irq_ack = ack_giuint_low,
165 .irq_mask = mask_giuint_low,
166 .irq_mask_ack = mask_ack_giuint_low,
167 .irq_unmask = unmask_giuint_low,
168 .irq_startup = startup_giuint,
169 .irq_shutdown = shutdown_giuint,
172 static void ack_giuint_high(struct irq_data *d)
174 giu_write(GIUINTSTATH,
175 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
178 static void mask_giuint_high(struct irq_data *d)
180 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
183 static void mask_ack_giuint_high(struct irq_data *d)
187 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
188 giu_clear(GIUINTENH, 1 << pin);
189 giu_write(GIUINTSTATH, 1 << pin);
192 static void unmask_giuint_high(struct irq_data *d)
194 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
197 static struct irq_chip giuint_high_irq_chip = {
199 .irq_ack = ack_giuint_high,
200 .irq_mask = mask_giuint_high,
201 .irq_mask_ack = mask_ack_giuint_high,
202 .irq_unmask = unmask_giuint_high,
205 static int giu_get_irq(unsigned int irq)
207 u16 pendl, pendh, maskl, maskh;
210 pendl = giu_read(GIUINTSTATL);
211 pendh = giu_read(GIUINTSTATH);
212 maskl = giu_read(GIUINTENL);
213 maskh = giu_read(GIUINTENH);
219 for (i = 0; i < 16; i++) {
220 if (maskl & (1 << i))
224 for (i = 0; i < 16; i++) {
225 if (maskh & (1 << i))
226 return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
230 printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
231 maskl, pendl, maskh, pendh);
233 atomic_inc(&irq_err_count);
238 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
243 if (pin < GIUINT_HIGH_OFFSET) {
245 if (trigger != IRQ_TRIGGER_LEVEL) {
246 giu_set(GIUINTTYPL, mask);
247 if (signal == IRQ_SIGNAL_HOLD)
248 giu_set(GIUINTHTSELL, mask);
250 giu_clear(GIUINTHTSELL, mask);
251 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
253 case IRQ_TRIGGER_EDGE_FALLING:
254 giu_set(GIUFEDGEINHL, mask);
255 giu_clear(GIUREDGEINHL, mask);
257 case IRQ_TRIGGER_EDGE_RISING:
258 giu_clear(GIUFEDGEINHL, mask);
259 giu_set(GIUREDGEINHL, mask);
262 giu_set(GIUFEDGEINHL, mask);
263 giu_set(GIUREDGEINHL, mask);
267 irq_set_chip_and_handler(GIU_IRQ(pin),
268 &giuint_low_irq_chip,
271 giu_clear(GIUINTTYPL, mask);
272 giu_clear(GIUINTHTSELL, mask);
273 irq_set_chip_and_handler(GIU_IRQ(pin),
274 &giuint_low_irq_chip,
277 giu_write(GIUINTSTATL, mask);
278 } else if (pin < GIUINT_HIGH_MAX) {
279 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
280 if (trigger != IRQ_TRIGGER_LEVEL) {
281 giu_set(GIUINTTYPH, mask);
282 if (signal == IRQ_SIGNAL_HOLD)
283 giu_set(GIUINTHTSELH, mask);
285 giu_clear(GIUINTHTSELH, mask);
286 if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
288 case IRQ_TRIGGER_EDGE_FALLING:
289 giu_set(GIUFEDGEINHH, mask);
290 giu_clear(GIUREDGEINHH, mask);
292 case IRQ_TRIGGER_EDGE_RISING:
293 giu_clear(GIUFEDGEINHH, mask);
294 giu_set(GIUREDGEINHH, mask);
297 giu_set(GIUFEDGEINHH, mask);
298 giu_set(GIUREDGEINHH, mask);
302 irq_set_chip_and_handler(GIU_IRQ(pin),
303 &giuint_high_irq_chip,
306 giu_clear(GIUINTTYPH, mask);
307 giu_clear(GIUINTHTSELH, mask);
308 irq_set_chip_and_handler(GIU_IRQ(pin),
309 &giuint_high_irq_chip,
312 giu_write(GIUINTSTATH, mask);
315 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
317 void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
321 if (pin < GIUINT_HIGH_OFFSET) {
323 if (level == IRQ_LEVEL_HIGH)
324 giu_set(GIUINTALSELL, mask);
326 giu_clear(GIUINTALSELL, mask);
327 giu_write(GIUINTSTATL, mask);
328 } else if (pin < GIUINT_HIGH_MAX) {
329 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
330 if (level == IRQ_LEVEL_HIGH)
331 giu_set(GIUINTALSELH, mask);
333 giu_clear(GIUINTALSELH, mask);
334 giu_write(GIUINTSTATH, mask);
337 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
339 static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
341 u16 offset, mask, reg;
344 if (pin >= chip->ngpio)
350 } else if (pin < 32) {
352 mask = 1 << (pin - 16);
354 if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
356 mask = 1 << (pin - 32);
373 spin_lock_irqsave(&giu_lock, flags);
375 reg = giu_read(offset);
376 if (dir == GPIO_OUTPUT)
380 giu_write(offset, reg);
382 spin_unlock_irqrestore(&giu_lock, flags);
387 int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
392 if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
400 spin_lock_irqsave(&giu_lock, flags);
402 if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
403 reg = giu_read(GIUTERMUPDN);
404 if (pull == GPIO_PULL_UP)
408 giu_write(GIUTERMUPDN, reg);
410 reg = giu_read(GIUUSEUPDN);
412 giu_write(GIUUSEUPDN, reg);
414 reg = giu_read(GIUUSEUPDN);
416 giu_write(GIUUSEUPDN, reg);
419 spin_unlock_irqrestore(&giu_lock, flags);
423 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
425 static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
429 if (pin >= chip->ngpio)
433 reg = giu_read(GIUPIODL);
435 } else if (pin < 32) {
436 reg = giu_read(GIUPIODH);
437 mask = 1 << (pin - 16);
438 } else if (pin < 48) {
439 reg = giu_read(GIUPODATL);
440 mask = 1 << (pin - 32);
442 reg = giu_read(GIUPODATH);
443 mask = 1 << (pin - 48);
452 static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
455 u16 offset, mask, reg;
458 if (pin >= chip->ngpio)
464 } else if (pin < 32) {
466 mask = 1 << (pin - 16);
467 } else if (pin < 48) {
469 mask = 1 << (pin - 32);
472 mask = 1 << (pin - 48);
475 spin_lock_irqsave(&giu_lock, flags);
477 reg = giu_read(offset);
482 giu_write(offset, reg);
484 spin_unlock_irqrestore(&giu_lock, flags);
488 static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
490 return giu_set_direction(chip, offset, GPIO_INPUT);
493 static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
496 vr41xx_gpio_set(chip, offset, value);
498 return giu_set_direction(chip, offset, GPIO_OUTPUT);
501 static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
503 if (offset >= chip->ngpio)
506 return GIU_IRQ_BASE + offset;
509 static struct gpio_chip vr41xx_gpio_chip = {
511 .owner = THIS_MODULE,
512 .direction_input = vr41xx_gpio_direction_input,
513 .get = vr41xx_gpio_get,
514 .direction_output = vr41xx_gpio_direction_output,
515 .set = vr41xx_gpio_set,
516 .to_irq = vr41xx_gpio_to_irq,
519 static int giu_probe(struct platform_device *pdev)
521 struct resource *res;
522 unsigned int trigger, i, pin;
523 struct irq_chip *chip;
527 case GPIO_50PINS_PULLUPDOWN:
528 giu_flags = GPIO_HAS_PULLUPDOWN_IO;
529 vr41xx_gpio_chip.ngpio = 50;
532 vr41xx_gpio_chip.ngpio = 36;
534 case GPIO_48PINS_EDGE_SELECT:
535 giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
536 vr41xx_gpio_chip.ngpio = 48;
539 dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
543 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
547 giu_base = ioremap(res->start, resource_size(res));
551 vr41xx_gpio_chip.parent = &pdev->dev;
553 ret = gpiochip_add_data(&vr41xx_gpio_chip, NULL);
559 giu_write(GIUINTENL, 0);
560 giu_write(GIUINTENH, 0);
562 trigger = giu_read(GIUINTTYPH) << 16;
563 trigger |= giu_read(GIUINTTYPL);
564 for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
565 pin = GPIO_PIN_OF_IRQ(i);
566 if (pin < GIUINT_HIGH_OFFSET)
567 chip = &giuint_low_irq_chip;
569 chip = &giuint_high_irq_chip;
571 if (trigger & (1 << pin))
572 irq_set_chip_and_handler(i, chip, handle_edge_irq);
574 irq_set_chip_and_handler(i, chip, handle_level_irq);
578 irq = platform_get_irq(pdev, 0);
579 if (irq < 0 || irq >= nr_irqs)
582 return cascade_irq(irq, giu_get_irq);
585 static int giu_remove(struct platform_device *pdev)
595 static struct platform_driver giu_device_driver = {
597 .remove = giu_remove,
603 module_platform_driver(giu_device_driver);