2 * Freescale vf610 GPIO support through PORT and GPIO
4 * Copyright (c) 2014 Toradex AG.
6 * Author: Stefan Agner <stefan@agner.ch>.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/bitops.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/platform_device.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
31 #define VF610_GPIO_PER_PORT 32
33 struct fsl_gpio_soc_data {
34 /* SoCs has a Port Data Direction Register (PDDR) */
38 struct vf610_gpio_port {
42 void __iomem *gpio_base;
43 const struct fsl_gpio_soc_data *sdata;
44 u8 irqc[VF610_GPIO_PER_PORT];
48 #define GPIO_PDOR 0x00
49 #define GPIO_PSOR 0x04
50 #define GPIO_PCOR 0x08
51 #define GPIO_PTOR 0x0c
52 #define GPIO_PDIR 0x10
53 #define GPIO_PDDR 0x14
55 #define PORT_PCR(n) ((n) * 0x4)
56 #define PORT_PCR_IRQC_OFFSET 16
58 #define PORT_ISFR 0xa0
59 #define PORT_DFER 0xc0
60 #define PORT_DFCR 0xc4
61 #define PORT_DFWR 0xc8
63 #define PORT_INT_OFF 0x0
64 #define PORT_INT_LOGIC_ZERO 0x8
65 #define PORT_INT_RISING_EDGE 0x9
66 #define PORT_INT_FALLING_EDGE 0xa
67 #define PORT_INT_EITHER_EDGE 0xb
68 #define PORT_INT_LOGIC_ONE 0xc
70 static const struct fsl_gpio_soc_data imx_data = {
74 static const struct of_device_id vf610_gpio_dt_ids[] = {
75 { .compatible = "fsl,vf610-gpio", .data = NULL, },
76 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
80 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
82 writel_relaxed(val, reg);
85 static inline u32 vf610_gpio_readl(void __iomem *reg)
87 return readl_relaxed(reg);
90 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
92 struct vf610_gpio_port *port = gpiochip_get_data(gc);
93 unsigned long mask = BIT(gpio);
96 if (port->sdata && port->sdata->have_paddr) {
97 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
98 addr = mask ? port->gpio_base + GPIO_PDOR :
99 port->gpio_base + GPIO_PDIR;
100 return !!(vf610_gpio_readl(addr) & BIT(gpio));
102 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
107 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
109 struct vf610_gpio_port *port = gpiochip_get_data(gc);
110 unsigned long mask = BIT(gpio);
113 vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
115 vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
118 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
120 struct vf610_gpio_port *port = gpiochip_get_data(chip);
121 unsigned long mask = BIT(gpio);
124 if (port->sdata && port->sdata->have_paddr) {
125 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
127 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
130 return pinctrl_gpio_direction_input(chip->base + gpio);
133 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
136 struct vf610_gpio_port *port = gpiochip_get_data(chip);
137 unsigned long mask = BIT(gpio);
140 if (port->sdata && port->sdata->have_paddr) {
141 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
143 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
146 vf610_gpio_set(chip, gpio, value);
148 return pinctrl_gpio_direction_output(chip->base + gpio);
151 static void vf610_gpio_irq_handler(struct irq_desc *desc)
153 struct vf610_gpio_port *port =
154 gpiochip_get_data(irq_desc_get_handler_data(desc));
155 struct irq_chip *chip = irq_desc_get_chip(desc);
157 unsigned long irq_isfr;
159 chained_irq_enter(chip, desc);
161 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
163 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
164 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
166 generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
169 chained_irq_exit(chip, desc);
172 static void vf610_gpio_irq_ack(struct irq_data *d)
174 struct vf610_gpio_port *port =
175 gpiochip_get_data(irq_data_get_irq_chip_data(d));
178 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
181 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
183 struct vf610_gpio_port *port =
184 gpiochip_get_data(irq_data_get_irq_chip_data(d));
188 case IRQ_TYPE_EDGE_RISING:
189 irqc = PORT_INT_RISING_EDGE;
191 case IRQ_TYPE_EDGE_FALLING:
192 irqc = PORT_INT_FALLING_EDGE;
194 case IRQ_TYPE_EDGE_BOTH:
195 irqc = PORT_INT_EITHER_EDGE;
197 case IRQ_TYPE_LEVEL_LOW:
198 irqc = PORT_INT_LOGIC_ZERO;
200 case IRQ_TYPE_LEVEL_HIGH:
201 irqc = PORT_INT_LOGIC_ONE;
207 port->irqc[d->hwirq] = irqc;
209 if (type & IRQ_TYPE_LEVEL_MASK)
210 irq_set_handler_locked(d, handle_level_irq);
212 irq_set_handler_locked(d, handle_edge_irq);
217 static void vf610_gpio_irq_mask(struct irq_data *d)
219 struct vf610_gpio_port *port =
220 gpiochip_get_data(irq_data_get_irq_chip_data(d));
221 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
223 vf610_gpio_writel(0, pcr_base);
226 static void vf610_gpio_irq_unmask(struct irq_data *d)
228 struct vf610_gpio_port *port =
229 gpiochip_get_data(irq_data_get_irq_chip_data(d));
230 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
232 vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
236 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
238 struct vf610_gpio_port *port =
239 gpiochip_get_data(irq_data_get_irq_chip_data(d));
242 enable_irq_wake(port->irq);
244 disable_irq_wake(port->irq);
249 static int vf610_gpio_probe(struct platform_device *pdev)
251 struct device *dev = &pdev->dev;
252 struct device_node *np = dev->of_node;
253 struct vf610_gpio_port *port;
254 struct resource *iores;
255 struct gpio_chip *gc;
260 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
264 port->sdata = of_device_get_match_data(dev);
265 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
266 port->base = devm_ioremap_resource(dev, iores);
267 if (IS_ERR(port->base))
268 return PTR_ERR(port->base);
270 iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
271 port->gpio_base = devm_ioremap_resource(dev, iores);
272 if (IS_ERR(port->gpio_base))
273 return PTR_ERR(port->gpio_base);
275 port->irq = platform_get_irq(pdev, 0);
282 gc->label = "vf610-gpio";
283 gc->ngpio = VF610_GPIO_PER_PORT;
284 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
286 gc->request = gpiochip_generic_request;
287 gc->free = gpiochip_generic_free;
288 gc->direction_input = vf610_gpio_direction_input;
289 gc->get = vf610_gpio_get;
290 gc->direction_output = vf610_gpio_direction_output;
291 gc->set = vf610_gpio_set;
294 ic->name = "gpio-vf610";
295 ic->irq_ack = vf610_gpio_irq_ack;
296 ic->irq_mask = vf610_gpio_irq_mask;
297 ic->irq_unmask = vf610_gpio_irq_unmask;
298 ic->irq_set_type = vf610_gpio_irq_set_type;
299 ic->irq_set_wake = vf610_gpio_irq_set_wake;
301 ret = gpiochip_add_data(gc, port);
305 /* Mask all GPIO interrupts */
306 for (i = 0; i < gc->ngpio; i++)
307 vf610_gpio_writel(0, port->base + PORT_PCR(i));
309 /* Clear the interrupt status register for all GPIO's */
310 vf610_gpio_writel(~0, port->base + PORT_ISFR);
312 ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
314 dev_err(dev, "failed to add irqchip\n");
318 gpiochip_set_chained_irqchip(gc, ic, port->irq,
319 vf610_gpio_irq_handler);
324 static struct platform_driver vf610_gpio_driver = {
326 .name = "gpio-vf610",
327 .of_match_table = vf610_gpio_dt_ids,
329 .probe = vf610_gpio_probe,
332 builtin_platform_driver(vf610_gpio_driver);