2 * Timberdale FPGA GPIO driver
3 * Author: Mocean Laboratories
4 * Copyright (c) 2009 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Timberdale FPGA GPIO
24 #include <linux/init.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 #include <linux/irq.h>
29 #include <linux/timb_gpio.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
33 #define DRIVER_NAME "timb-gpio"
37 #define TGPIO_IER 0x08
38 #define TGPIO_ISR 0x0c
39 #define TGPIO_IPR 0x10
40 #define TGPIO_ICR 0x14
41 #define TGPIO_FLR 0x18
42 #define TGPIO_LVR 0x1c
43 #define TGPIO_VER 0x20
44 #define TGPIO_BFLR 0x24
47 void __iomem *membase;
48 spinlock_t lock; /* mutual exclusion */
49 struct gpio_chip gpio;
51 unsigned long last_ier;
54 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
55 unsigned offset, bool enabled)
57 struct timbgpio *tgpio = gpiochip_get_data(gpio);
61 spin_lock_irqsave(&tgpio->lock, flags);
62 reg = ioread32(tgpio->membase + offset);
69 iowrite32(reg, tgpio->membase + offset);
70 spin_unlock_irqrestore(&tgpio->lock, flags);
75 static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
77 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
80 static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
82 struct timbgpio *tgpio = gpiochip_get_data(gpio);
85 value = ioread32(tgpio->membase + TGPIOVAL);
86 return (value & (1 << nr)) ? 1 : 0;
89 static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
92 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
95 static void timbgpio_gpio_set(struct gpio_chip *gpio,
98 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
101 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
103 struct timbgpio *tgpio = gpiochip_get_data(gpio);
105 if (tgpio->irq_base <= 0)
108 return tgpio->irq_base + offset;
114 static void timbgpio_irq_disable(struct irq_data *d)
116 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
117 int offset = d->irq - tgpio->irq_base;
120 spin_lock_irqsave(&tgpio->lock, flags);
121 tgpio->last_ier &= ~(1UL << offset);
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
123 spin_unlock_irqrestore(&tgpio->lock, flags);
126 static void timbgpio_irq_enable(struct irq_data *d)
128 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
129 int offset = d->irq - tgpio->irq_base;
132 spin_lock_irqsave(&tgpio->lock, flags);
133 tgpio->last_ier |= 1UL << offset;
134 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
135 spin_unlock_irqrestore(&tgpio->lock, flags);
138 static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
140 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
141 int offset = d->irq - tgpio->irq_base;
143 u32 lvr, flr, bflr = 0;
147 if (offset < 0 || offset > tgpio->gpio.ngpio)
150 ver = ioread32(tgpio->membase + TGPIO_VER);
152 spin_lock_irqsave(&tgpio->lock, flags);
154 lvr = ioread32(tgpio->membase + TGPIO_LVR);
155 flr = ioread32(tgpio->membase + TGPIO_FLR);
157 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
159 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
160 bflr &= ~(1 << offset);
161 flr &= ~(1 << offset);
162 if (trigger & IRQ_TYPE_LEVEL_HIGH)
165 lvr &= ~(1 << offset);
168 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
177 bflr &= ~(1 << offset);
179 if (trigger & IRQ_TYPE_EDGE_FALLING)
180 lvr &= ~(1 << offset);
185 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
186 iowrite32(flr, tgpio->membase + TGPIO_FLR);
188 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
190 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
193 spin_unlock_irqrestore(&tgpio->lock, flags);
197 static void timbgpio_irq(struct irq_desc *desc)
199 struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
200 struct irq_data *data = irq_desc_get_irq_data(desc);
204 data->chip->irq_ack(data);
205 ipr = ioread32(tgpio->membase + TGPIO_IPR);
206 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
209 * Some versions of the hardware trash the IER register if more than
210 * one interrupt is received simultaneously.
212 iowrite32(0, tgpio->membase + TGPIO_IER);
214 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
215 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
217 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
220 static struct irq_chip timbgpio_irqchip = {
222 .irq_enable = timbgpio_irq_enable,
223 .irq_disable = timbgpio_irq_disable,
224 .irq_set_type = timbgpio_irq_type,
227 static int timbgpio_probe(struct platform_device *pdev)
230 struct device *dev = &pdev->dev;
231 struct gpio_chip *gc;
232 struct timbgpio *tgpio;
233 struct resource *iomem;
234 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
235 int irq = platform_get_irq(pdev, 0);
237 if (!pdata || pdata->nr_pins > 32) {
238 dev_err(dev, "Invalid platform data\n");
242 tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
244 dev_err(dev, "Memory alloc failed\n");
247 tgpio->irq_base = pdata->irq_base;
249 spin_lock_init(&tgpio->lock);
251 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252 tgpio->membase = devm_ioremap_resource(dev, iomem);
253 if (IS_ERR(tgpio->membase))
254 return PTR_ERR(tgpio->membase);
258 gc->label = dev_name(&pdev->dev);
259 gc->owner = THIS_MODULE;
260 gc->parent = &pdev->dev;
261 gc->direction_input = timbgpio_gpio_direction_input;
262 gc->get = timbgpio_gpio_get;
263 gc->direction_output = timbgpio_gpio_direction_output;
264 gc->set = timbgpio_gpio_set;
265 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
267 gc->base = pdata->gpio_base;
268 gc->ngpio = pdata->nr_pins;
269 gc->can_sleep = false;
271 err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
275 platform_set_drvdata(pdev, tgpio);
277 /* make sure to disable interrupts */
278 iowrite32(0x0, tgpio->membase + TGPIO_IER);
280 if (irq < 0 || tgpio->irq_base <= 0)
283 for (i = 0; i < pdata->nr_pins; i++) {
284 irq_set_chip_and_handler(tgpio->irq_base + i,
285 &timbgpio_irqchip, handle_simple_irq);
286 irq_set_chip_data(tgpio->irq_base + i, tgpio);
287 irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
290 irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
295 static struct platform_driver timbgpio_platform_driver = {
298 .suppress_bind_attrs = true,
300 .probe = timbgpio_probe,
303 /*--------------------------------------------------------------------------*/
305 builtin_platform_driver(timbgpio_platform_driver);