1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
18 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
19 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
20 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
21 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
22 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
23 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
24 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
25 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
26 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
27 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
29 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
30 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
32 #define TEGRA186_GPIO_INPUT 0x08
33 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
35 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
36 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
38 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
39 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
41 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
43 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
45 struct tegra_gpio_port {
52 struct tegra_gpio_soc {
53 const struct tegra_gpio_port *ports;
54 unsigned int num_ports;
59 struct gpio_chip gpio;
64 const struct tegra_gpio_soc *soc;
69 static const struct tegra_gpio_port *
70 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
72 unsigned int start = 0, i;
74 for (i = 0; i < gpio->soc->num_ports; i++) {
75 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
77 if (*pin >= start && *pin < start + port->pins) {
88 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
91 const struct tegra_gpio_port *port;
93 port = tegra186_gpio_get_port(gpio, &pin);
97 return gpio->base + port->offset + pin * 0x20;
100 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
103 struct tegra_gpio *gpio = gpiochip_get_data(chip);
107 base = tegra186_gpio_get_base(gpio, offset);
108 if (WARN_ON(base == NULL))
111 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
112 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
118 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
121 struct tegra_gpio *gpio = gpiochip_get_data(chip);
125 base = tegra186_gpio_get_base(gpio, offset);
126 if (WARN_ON(base == NULL))
129 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
130 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
131 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
133 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
134 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
135 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
136 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
141 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
142 unsigned int offset, int level)
144 struct tegra_gpio *gpio = gpiochip_get_data(chip);
148 /* configure output level first */
149 chip->set(chip, offset, level);
151 base = tegra186_gpio_get_base(gpio, offset);
152 if (WARN_ON(base == NULL))
155 /* set the direction */
156 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
157 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
158 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
160 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
161 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
162 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
163 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
168 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
170 struct tegra_gpio *gpio = gpiochip_get_data(chip);
174 base = tegra186_gpio_get_base(gpio, offset);
175 if (WARN_ON(base == NULL))
178 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
179 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
180 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
182 value = readl(base + TEGRA186_GPIO_INPUT);
184 return value & BIT(0);
187 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
190 struct tegra_gpio *gpio = gpiochip_get_data(chip);
194 base = tegra186_gpio_get_base(gpio, offset);
195 if (WARN_ON(base == NULL))
198 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
200 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
202 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
204 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
207 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
208 const struct of_phandle_args *spec,
211 struct tegra_gpio *gpio = gpiochip_get_data(chip);
212 unsigned int port, pin, i, offset = 0;
214 if (WARN_ON(chip->of_gpio_n_cells < 2))
217 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
220 port = spec->args[0] / 8;
221 pin = spec->args[0] % 8;
223 if (port >= gpio->soc->num_ports) {
224 dev_err(chip->parent, "invalid port number: %u\n", port);
228 for (i = 0; i < port; i++)
229 offset += gpio->soc->ports[i].pins;
232 *flags = spec->args[1];
237 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
239 static void tegra186_irq_ack(struct irq_data *data)
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
242 struct tegra_gpio *gpio = to_tegra_gpio(gc);
245 base = tegra186_gpio_get_base(gpio, data->hwirq);
246 if (WARN_ON(base == NULL))
249 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
252 static void tegra186_irq_mask(struct irq_data *data)
254 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
255 struct tegra_gpio *gpio = to_tegra_gpio(gc);
259 base = tegra186_gpio_get_base(gpio, data->hwirq);
260 if (WARN_ON(base == NULL))
263 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
264 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
268 static void tegra186_irq_unmask(struct irq_data *data)
270 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
271 struct tegra_gpio *gpio = to_tegra_gpio(gc);
275 base = tegra186_gpio_get_base(gpio, data->hwirq);
276 if (WARN_ON(base == NULL))
279 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
280 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
281 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
284 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
286 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
287 struct tegra_gpio *gpio = to_tegra_gpio(gc);
291 base = tegra186_gpio_get_base(gpio, data->hwirq);
292 if (WARN_ON(base == NULL))
295 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
296 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
297 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
299 switch (type & IRQ_TYPE_SENSE_MASK) {
303 case IRQ_TYPE_EDGE_RISING:
304 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
305 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
308 case IRQ_TYPE_EDGE_FALLING:
309 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
312 case IRQ_TYPE_EDGE_BOTH:
313 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
316 case IRQ_TYPE_LEVEL_HIGH:
317 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
318 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
321 case IRQ_TYPE_LEVEL_LOW:
322 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
329 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
331 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
332 irq_set_handler_locked(data, handle_level_irq);
334 irq_set_handler_locked(data, handle_edge_irq);
339 static void tegra186_gpio_irq(struct irq_desc *desc)
341 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
342 struct irq_domain *domain = gpio->gpio.irq.domain;
343 struct irq_chip *chip = irq_desc_get_chip(desc);
344 unsigned int parent = irq_desc_get_irq(desc);
345 unsigned int i, offset = 0;
347 chained_irq_enter(chip, desc);
349 for (i = 0; i < gpio->soc->num_ports; i++) {
350 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
351 void __iomem *base = gpio->base + port->offset;
352 unsigned int pin, irq;
355 /* skip ports that are not associated with this controller */
356 if (parent != gpio->irq[port->irq])
359 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
361 for_each_set_bit(pin, &value, port->pins) {
362 irq = irq_find_mapping(domain, offset + pin);
363 if (WARN_ON(irq == 0))
366 generic_handle_irq(irq);
370 offset += port->pins;
373 chained_irq_exit(chip, desc);
376 static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain,
377 struct device_node *np,
378 const u32 *spec, unsigned int size,
379 unsigned long *hwirq,
382 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
383 unsigned int port, pin, i, offset = 0;
391 if (port >= gpio->soc->num_ports) {
392 dev_err(gpio->gpio.parent, "invalid port number: %u\n", port);
396 for (i = 0; i < port; i++)
397 offset += gpio->soc->ports[i].pins;
399 *type = spec[1] & IRQ_TYPE_SENSE_MASK;
400 *hwirq = offset + pin;
405 static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = {
406 .map = gpiochip_irq_map,
407 .unmap = gpiochip_irq_unmap,
408 .xlate = tegra186_gpio_irq_domain_xlate,
411 static int tegra186_gpio_probe(struct platform_device *pdev)
413 unsigned int i, j, offset;
414 struct gpio_irq_chip *irq;
415 struct tegra_gpio *gpio;
416 struct resource *res;
420 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
424 gpio->soc = of_device_get_match_data(&pdev->dev);
426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
427 gpio->base = devm_ioremap_resource(&pdev->dev, res);
428 if (IS_ERR(gpio->base))
429 return PTR_ERR(gpio->base);
431 err = platform_irq_count(pdev);
437 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
442 for (i = 0; i < gpio->num_irq; i++) {
443 err = platform_get_irq(pdev, i);
450 gpio->gpio.label = gpio->soc->name;
451 gpio->gpio.parent = &pdev->dev;
453 gpio->gpio.get_direction = tegra186_gpio_get_direction;
454 gpio->gpio.direction_input = tegra186_gpio_direction_input;
455 gpio->gpio.direction_output = tegra186_gpio_direction_output;
456 gpio->gpio.get = tegra186_gpio_get,
457 gpio->gpio.set = tegra186_gpio_set;
459 gpio->gpio.base = -1;
461 for (i = 0; i < gpio->soc->num_ports; i++)
462 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
464 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
465 sizeof(*names), GFP_KERNEL);
469 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
470 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
473 for (j = 0; j < port->pins; j++) {
474 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
475 "P%s.%02x", port->name, j);
479 names[offset + j] = name;
482 offset += port->pins;
485 gpio->gpio.names = (const char * const *)names;
487 gpio->gpio.of_node = pdev->dev.of_node;
488 gpio->gpio.of_gpio_n_cells = 2;
489 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
491 gpio->intc.name = pdev->dev.of_node->name;
492 gpio->intc.irq_ack = tegra186_irq_ack;
493 gpio->intc.irq_mask = tegra186_irq_mask;
494 gpio->intc.irq_unmask = tegra186_irq_unmask;
495 gpio->intc.irq_set_type = tegra186_irq_set_type;
497 irq = &gpio->gpio.irq;
498 irq->chip = &gpio->intc;
499 irq->domain_ops = &tegra186_gpio_irq_domain_ops;
500 irq->handler = handle_simple_irq;
501 irq->default_type = IRQ_TYPE_NONE;
502 irq->parent_handler = tegra186_gpio_irq;
503 irq->parent_handler_data = gpio;
504 irq->num_parents = gpio->num_irq;
505 irq->parents = gpio->irq;
507 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
508 sizeof(*irq->map), GFP_KERNEL);
512 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
513 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
515 for (j = 0; j < port->pins; j++)
516 irq->map[offset + j] = irq->parents[port->irq];
518 offset += port->pins;
521 platform_set_drvdata(pdev, gpio);
523 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
530 static int tegra186_gpio_remove(struct platform_device *pdev)
535 #define TEGRA186_MAIN_GPIO_PORT(port, base, count, controller) \
536 [TEGRA186_MAIN_GPIO_PORT_##port] = { \
543 static const struct tegra_gpio_port tegra186_main_ports[] = {
544 TEGRA186_MAIN_GPIO_PORT( A, 0x2000, 7, 2),
545 TEGRA186_MAIN_GPIO_PORT( B, 0x3000, 7, 3),
546 TEGRA186_MAIN_GPIO_PORT( C, 0x3200, 7, 3),
547 TEGRA186_MAIN_GPIO_PORT( D, 0x3400, 6, 3),
548 TEGRA186_MAIN_GPIO_PORT( E, 0x2200, 8, 2),
549 TEGRA186_MAIN_GPIO_PORT( F, 0x2400, 6, 2),
550 TEGRA186_MAIN_GPIO_PORT( G, 0x4200, 6, 4),
551 TEGRA186_MAIN_GPIO_PORT( H, 0x1000, 7, 1),
552 TEGRA186_MAIN_GPIO_PORT( I, 0x0800, 8, 0),
553 TEGRA186_MAIN_GPIO_PORT( J, 0x5000, 8, 5),
554 TEGRA186_MAIN_GPIO_PORT( K, 0x5200, 1, 5),
555 TEGRA186_MAIN_GPIO_PORT( L, 0x1200, 8, 1),
556 TEGRA186_MAIN_GPIO_PORT( M, 0x5600, 6, 5),
557 TEGRA186_MAIN_GPIO_PORT( N, 0x0000, 7, 0),
558 TEGRA186_MAIN_GPIO_PORT( O, 0x0200, 4, 0),
559 TEGRA186_MAIN_GPIO_PORT( P, 0x4000, 7, 4),
560 TEGRA186_MAIN_GPIO_PORT( Q, 0x0400, 6, 0),
561 TEGRA186_MAIN_GPIO_PORT( R, 0x0a00, 6, 0),
562 TEGRA186_MAIN_GPIO_PORT( T, 0x0600, 4, 0),
563 TEGRA186_MAIN_GPIO_PORT( X, 0x1400, 8, 1),
564 TEGRA186_MAIN_GPIO_PORT( Y, 0x1600, 7, 1),
565 TEGRA186_MAIN_GPIO_PORT(BB, 0x2600, 2, 2),
566 TEGRA186_MAIN_GPIO_PORT(CC, 0x5400, 4, 5),
569 static const struct tegra_gpio_soc tegra186_main_soc = {
570 .num_ports = ARRAY_SIZE(tegra186_main_ports),
571 .ports = tegra186_main_ports,
572 .name = "tegra186-gpio",
575 #define TEGRA186_AON_GPIO_PORT(port, base, count, controller) \
576 [TEGRA186_AON_GPIO_PORT_##port] = { \
583 static const struct tegra_gpio_port tegra186_aon_ports[] = {
584 TEGRA186_AON_GPIO_PORT( S, 0x0200, 5, 0),
585 TEGRA186_AON_GPIO_PORT( U, 0x0400, 6, 0),
586 TEGRA186_AON_GPIO_PORT( V, 0x0800, 8, 0),
587 TEGRA186_AON_GPIO_PORT( W, 0x0a00, 8, 0),
588 TEGRA186_AON_GPIO_PORT( Z, 0x0e00, 4, 0),
589 TEGRA186_AON_GPIO_PORT(AA, 0x0c00, 8, 0),
590 TEGRA186_AON_GPIO_PORT(EE, 0x0600, 3, 0),
591 TEGRA186_AON_GPIO_PORT(FF, 0x0000, 5, 0),
594 static const struct tegra_gpio_soc tegra186_aon_soc = {
595 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
596 .ports = tegra186_aon_ports,
597 .name = "tegra186-gpio-aon",
600 #define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \
601 [TEGRA194_MAIN_GPIO_PORT_##port] = { \
608 static const struct tegra_gpio_port tegra194_main_ports[] = {
609 TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1),
610 TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4),
611 TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4),
612 TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4),
613 TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4),
614 TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4),
615 TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4),
616 TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4),
617 TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4),
618 TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5),
619 TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3),
620 TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3),
621 TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2),
622 TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2),
623 TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5),
624 TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2),
625 TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2),
626 TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2),
627 TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3),
628 TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3),
629 TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3),
630 TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1),
631 TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1),
632 TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2),
633 TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2),
634 TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2),
635 TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3),
636 TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0)
639 static const struct tegra_gpio_soc tegra194_main_soc = {
640 .num_ports = ARRAY_SIZE(tegra194_main_ports),
641 .ports = tegra194_main_ports,
642 .name = "tegra194-gpio",
645 #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \
646 [TEGRA194_AON_GPIO_PORT_##port] = { \
653 static const struct tegra_gpio_port tegra194_aon_ports[] = {
654 TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0),
655 TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0),
656 TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0),
657 TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0),
658 TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0)
661 static const struct tegra_gpio_soc tegra194_aon_soc = {
662 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
663 .ports = tegra194_aon_ports,
664 .name = "tegra194-gpio-aon",
667 static const struct of_device_id tegra186_gpio_of_match[] = {
669 .compatible = "nvidia,tegra186-gpio",
670 .data = &tegra186_main_soc
672 .compatible = "nvidia,tegra186-gpio-aon",
673 .data = &tegra186_aon_soc
675 .compatible = "nvidia,tegra194-gpio",
676 .data = &tegra194_main_soc
678 .compatible = "nvidia,tegra194-gpio-aon",
679 .data = &tegra194_aon_soc
685 static struct platform_driver tegra186_gpio_driver = {
687 .name = "tegra186-gpio",
688 .of_match_table = tegra186_gpio_of_match,
690 .probe = tegra186_gpio_probe,
691 .remove = tegra186_gpio_remove,
693 module_platform_driver(tegra186_gpio_driver);
695 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
696 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
697 MODULE_LICENSE("GPL v2");