2 * arch/arm/mach-tegra/gpio.c
4 * Copyright (c) 2010 Google, Inc
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
25 #include <linux/gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
60 #define GPIO_INT_LVL_MASK 0x010101
61 #define GPIO_INT_LVL_EDGE_RISING 0x000101
62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
67 struct tegra_gpio_info;
69 struct tegra_gpio_bank {
72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74 #ifdef CONFIG_PM_SLEEP
84 struct tegra_gpio_info *tgi;
87 struct tegra_gpio_soc_config {
88 bool debounce_supported;
93 struct tegra_gpio_info {
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
104 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
107 __raw_writel(val, tgi->regs + reg);
110 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
112 return __raw_readl(tgi->regs + reg);
115 static int tegra_gpio_compose(int bank, int port, int bit)
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
120 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
125 val = 0x100 << GPIO_BIT(gpio);
127 val |= 1 << GPIO_BIT(gpio);
128 tegra_gpio_writel(tgi, val, reg);
131 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
136 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
141 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
143 return pinctrl_request_gpio(offset);
146 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
148 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150 pinctrl_free_gpio(offset);
151 tegra_gpio_disable(tgi, offset);
154 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
161 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
164 int bval = BIT(GPIO_BIT(offset));
166 /* If gpio is in output mode then read from the out value */
167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
168 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
173 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
175 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
177 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
178 tegra_gpio_enable(tgi, offset);
182 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
185 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
187 tegra_gpio_set(chip, offset, value);
188 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
189 tegra_gpio_enable(tgi, offset);
193 static int tegra_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
196 u32 pin_mask = BIT(GPIO_BIT(offset));
199 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
200 if (!(cnf & pin_mask))
203 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
205 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
208 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
209 unsigned int debounce)
211 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
212 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
213 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
218 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
223 debounce_ms = min(debounce_ms, 255U);
224 port = GPIO_PORT(offset);
226 /* There is only one debounce count register per port and hence
227 * set the maximum of current and requested debounce time.
229 spin_lock_irqsave(&bank->dbc_lock[port], flags);
230 if (bank->dbc_cnt[port] < debounce_ms) {
231 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
232 bank->dbc_cnt[port] = debounce_ms;
234 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
236 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
241 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
243 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
245 return irq_find_mapping(tgi->irq_domain, offset);
248 static void tegra_gpio_irq_ack(struct irq_data *d)
250 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
251 struct tegra_gpio_info *tgi = bank->tgi;
254 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
257 static void tegra_gpio_irq_mask(struct irq_data *d)
259 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
260 struct tegra_gpio_info *tgi = bank->tgi;
263 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
266 static void tegra_gpio_irq_unmask(struct irq_data *d)
268 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
269 struct tegra_gpio_info *tgi = bank->tgi;
272 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
275 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
279 struct tegra_gpio_info *tgi = bank->tgi;
280 int port = GPIO_PORT(gpio);
286 switch (type & IRQ_TYPE_SENSE_MASK) {
287 case IRQ_TYPE_EDGE_RISING:
288 lvl_type = GPIO_INT_LVL_EDGE_RISING;
291 case IRQ_TYPE_EDGE_FALLING:
292 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
295 case IRQ_TYPE_EDGE_BOTH:
296 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
299 case IRQ_TYPE_LEVEL_HIGH:
300 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
303 case IRQ_TYPE_LEVEL_LOW:
304 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
311 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
314 "unable to lock Tegra GPIO %d as IRQ\n", gpio);
318 spin_lock_irqsave(&bank->lvl_lock[port], flags);
320 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
321 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
322 val |= lvl_type << GPIO_BIT(gpio);
323 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
325 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
327 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
328 tegra_gpio_enable(tgi, gpio);
330 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
331 irq_set_handler_locked(d, handle_level_irq);
332 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
333 irq_set_handler_locked(d, handle_edge_irq);
338 static void tegra_gpio_irq_shutdown(struct irq_data *d)
340 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
341 struct tegra_gpio_info *tgi = bank->tgi;
344 tegra_gpio_irq_mask(d);
345 gpiochip_unlock_as_irq(&tgi->gc, gpio);
348 static void tegra_gpio_irq_handler(struct irq_desc *desc)
356 struct irq_chip *chip = irq_desc_get_chip(desc);
357 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
358 struct tegra_gpio_info *tgi = bank->tgi;
360 chained_irq_enter(chip, desc);
362 for (port = 0; port < 4; port++) {
363 gpio = tegra_gpio_compose(bank->bank, port, 0);
364 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
365 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
366 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
368 for_each_set_bit(pin, &sta, 8) {
369 tegra_gpio_writel(tgi, 1 << pin,
370 GPIO_INT_CLR(tgi, gpio));
372 /* if gpio is edge triggered, clear condition
373 * before executing the handler so that we don't
376 if (lvl & (0x100 << pin)) {
378 chained_irq_exit(chip, desc);
381 generic_handle_irq(gpio_to_irq(gpio + pin));
386 chained_irq_exit(chip, desc);
390 #ifdef CONFIG_PM_SLEEP
391 static int tegra_gpio_resume(struct device *dev)
393 struct platform_device *pdev = to_platform_device(dev);
394 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
399 local_irq_save(flags);
401 for (b = 0; b < tgi->bank_count; b++) {
402 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
404 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
405 unsigned int gpio = (b<<5) | (p<<3);
406 tegra_gpio_writel(tgi, bank->cnf[p],
407 GPIO_CNF(tgi, gpio));
409 if (tgi->soc->debounce_supported) {
410 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
411 GPIO_DBC_CNT(tgi, gpio));
412 tegra_gpio_writel(tgi, bank->dbc_enb[p],
413 GPIO_MSK_DBC_EN(tgi, gpio));
416 tegra_gpio_writel(tgi, bank->out[p],
417 GPIO_OUT(tgi, gpio));
418 tegra_gpio_writel(tgi, bank->oe[p],
420 tegra_gpio_writel(tgi, bank->int_lvl[p],
421 GPIO_INT_LVL(tgi, gpio));
422 tegra_gpio_writel(tgi, bank->int_enb[p],
423 GPIO_INT_ENB(tgi, gpio));
427 local_irq_restore(flags);
431 static int tegra_gpio_suspend(struct device *dev)
433 struct platform_device *pdev = to_platform_device(dev);
434 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
439 local_irq_save(flags);
440 for (b = 0; b < tgi->bank_count; b++) {
441 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
443 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
444 unsigned int gpio = (b<<5) | (p<<3);
445 bank->cnf[p] = tegra_gpio_readl(tgi,
446 GPIO_CNF(tgi, gpio));
447 bank->out[p] = tegra_gpio_readl(tgi,
448 GPIO_OUT(tgi, gpio));
449 bank->oe[p] = tegra_gpio_readl(tgi,
451 if (tgi->soc->debounce_supported) {
452 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
453 GPIO_MSK_DBC_EN(tgi, gpio));
454 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
458 bank->int_enb[p] = tegra_gpio_readl(tgi,
459 GPIO_INT_ENB(tgi, gpio));
460 bank->int_lvl[p] = tegra_gpio_readl(tgi,
461 GPIO_INT_LVL(tgi, gpio));
463 /* Enable gpio irq for wake up source */
464 tegra_gpio_writel(tgi, bank->wake_enb[p],
465 GPIO_INT_ENB(tgi, gpio));
468 local_irq_restore(flags);
472 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
474 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
478 port = GPIO_PORT(gpio);
479 bit = GPIO_BIT(gpio);
483 bank->wake_enb[port] |= mask;
485 bank->wake_enb[port] &= ~mask;
487 return irq_set_irq_wake(bank->irq, enable);
491 #ifdef CONFIG_DEBUG_FS
493 #include <linux/debugfs.h>
494 #include <linux/seq_file.h>
496 static int dbg_gpio_show(struct seq_file *s, void *unused)
498 struct tegra_gpio_info *tgi = s->private;
502 for (i = 0; i < tgi->bank_count; i++) {
503 for (j = 0; j < 4; j++) {
504 int gpio = tegra_gpio_compose(i, j, 0);
506 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
508 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
509 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
510 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
511 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
512 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
513 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
514 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
520 static int dbg_gpio_open(struct inode *inode, struct file *file)
522 return single_open(file, dbg_gpio_show, inode->i_private);
525 static const struct file_operations debug_fops = {
526 .open = dbg_gpio_open,
529 .release = single_release,
532 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
534 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
535 NULL, tgi, &debug_fops);
540 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
546 static const struct dev_pm_ops tegra_gpio_pm_ops = {
547 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
551 * This lock class tells lockdep that GPIO irqs are in a different category
552 * than their parents, so it won't report false recursion.
554 static struct lock_class_key gpio_lock_class;
556 static int tegra_gpio_probe(struct platform_device *pdev)
558 const struct tegra_gpio_soc_config *config;
559 struct tegra_gpio_info *tgi;
560 struct resource *res;
561 struct tegra_gpio_bank *bank;
567 config = of_device_get_match_data(&pdev->dev);
569 dev_err(&pdev->dev, "Error: No device match found\n");
573 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
578 tgi->dev = &pdev->dev;
581 res = platform_get_resource(pdev, IORESOURCE_IRQ,
587 if (!tgi->bank_count) {
588 dev_err(&pdev->dev, "Missing IRQ resource\n");
592 tgi->gc.label = "tegra-gpio";
593 tgi->gc.request = tegra_gpio_request;
594 tgi->gc.free = tegra_gpio_free;
595 tgi->gc.direction_input = tegra_gpio_direction_input;
596 tgi->gc.get = tegra_gpio_get;
597 tgi->gc.direction_output = tegra_gpio_direction_output;
598 tgi->gc.set = tegra_gpio_set;
599 tgi->gc.get_direction = tegra_gpio_get_direction;
600 tgi->gc.to_irq = tegra_gpio_to_irq;
602 tgi->gc.ngpio = tgi->bank_count * 32;
603 tgi->gc.parent = &pdev->dev;
604 tgi->gc.of_node = pdev->dev.of_node;
606 tgi->ic.name = "GPIO";
607 tgi->ic.irq_ack = tegra_gpio_irq_ack;
608 tgi->ic.irq_mask = tegra_gpio_irq_mask;
609 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
610 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
611 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
612 #ifdef CONFIG_PM_SLEEP
613 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
616 platform_set_drvdata(pdev, tgi);
618 if (config->debounce_supported)
619 tgi->gc.set_debounce = tegra_gpio_set_debounce;
621 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count *
622 sizeof(*tgi->bank_info), GFP_KERNEL);
626 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
628 &irq_domain_simple_ops, NULL);
629 if (!tgi->irq_domain)
632 for (i = 0; i < tgi->bank_count; i++) {
633 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
635 dev_err(&pdev->dev, "Missing IRQ resource\n");
639 bank = &tgi->bank_info[i];
641 bank->irq = res->start;
645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
647 if (IS_ERR(tgi->regs))
648 return PTR_ERR(tgi->regs);
650 for (i = 0; i < tgi->bank_count; i++) {
651 for (j = 0; j < 4; j++) {
652 int gpio = tegra_gpio_compose(i, j, 0);
653 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
657 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
659 irq_domain_remove(tgi->irq_domain);
663 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
664 int irq = irq_create_mapping(tgi->irq_domain, gpio);
665 /* No validity check; all Tegra GPIOs are valid IRQs */
667 bank = &tgi->bank_info[GPIO_BANK(gpio)];
669 irq_set_lockdep_class(irq, &gpio_lock_class);
670 irq_set_chip_data(irq, bank);
671 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
674 for (i = 0; i < tgi->bank_count; i++) {
675 bank = &tgi->bank_info[i];
677 irq_set_chained_handler_and_data(bank->irq,
678 tegra_gpio_irq_handler, bank);
680 for (j = 0; j < 4; j++) {
681 spin_lock_init(&bank->lvl_lock[j]);
682 spin_lock_init(&bank->dbc_lock[j]);
686 tegra_gpio_debuginit(tgi);
691 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
693 .upper_offset = 0x800,
696 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
697 .bank_stride = 0x100,
698 .upper_offset = 0x80,
701 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
702 .debounce_supported = true,
703 .bank_stride = 0x100,
704 .upper_offset = 0x80,
707 static const struct of_device_id tegra_gpio_of_match[] = {
708 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
709 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
710 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
714 static struct platform_driver tegra_gpio_driver = {
716 .name = "tegra-gpio",
717 .pm = &tegra_gpio_pm_ops,
718 .of_match_table = tegra_gpio_of_match,
720 .probe = tegra_gpio_probe,
723 static int __init tegra_gpio_init(void)
725 return platform_driver_register(&tegra_gpio_driver);
727 subsys_initcall(tegra_gpio_init);