1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/gpio/driver.h>
14 #include <linux/interrupt.h>
15 #include <linux/mfd/tc3589x.h>
16 #include <linux/bitops.h>
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
22 enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
24 #define CACHE_NR_REGS 5
25 #define CACHE_NR_BANKS 3
28 struct gpio_chip chip;
29 struct tc3589x *tc3589x;
31 struct mutex irq_lock;
32 /* Caches of interrupt control registers for bus_lock */
33 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
34 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
39 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
40 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
41 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
42 u8 mask = BIT(offset % 8);
45 ret = tc3589x_reg_read(tc3589x, reg);
49 return !!(ret & mask);
52 static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
54 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
55 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
56 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
57 unsigned int pos = offset % 8;
58 u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
60 tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
63 static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
64 unsigned int offset, int val)
66 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
67 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
68 u8 reg = TC3589x_GPIODIR0 + offset / 8;
69 unsigned int pos = offset % 8;
71 tc3589x_gpio_set(chip, offset, val);
73 return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
76 static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
79 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
80 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
81 u8 reg = TC3589x_GPIODIR0 + offset / 8;
82 unsigned int pos = offset % 8;
84 return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
87 static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
90 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
91 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
92 u8 reg = TC3589x_GPIODIR0 + offset / 8;
93 unsigned int pos = offset % 8;
96 ret = tc3589x_reg_read(tc3589x, reg);
101 return GPIO_LINE_DIRECTION_OUT;
103 return GPIO_LINE_DIRECTION_IN;
106 static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
107 unsigned long config)
109 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
110 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
112 * These registers are alterated at each second address
113 * ODM bit 0 = drive to GND or Hi-Z (open drain)
114 * ODM bit 1 = drive to VDD or Hi-Z (open source)
116 u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
117 u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
118 unsigned int pos = offset % 8;
121 switch (pinconf_to_config_param(config)) {
122 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
123 /* Set open drain mode */
124 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
127 /* Enable open drain/source mode */
128 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
129 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
130 /* Set open source mode */
131 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
134 /* Enable open drain/source mode */
135 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
136 case PIN_CONFIG_DRIVE_PUSH_PULL:
137 /* Disable open drain/source mode */
138 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
145 static const struct gpio_chip template_chip = {
147 .owner = THIS_MODULE,
148 .get = tc3589x_gpio_get,
149 .set = tc3589x_gpio_set,
150 .direction_output = tc3589x_gpio_direction_output,
151 .direction_input = tc3589x_gpio_direction_input,
152 .get_direction = tc3589x_gpio_get_direction,
153 .set_config = tc3589x_gpio_set_config,
157 static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
159 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
161 int offset = d->hwirq;
162 int regoffset = offset / 8;
163 int mask = BIT(offset % 8);
165 if (type == IRQ_TYPE_EDGE_BOTH) {
166 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
170 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
172 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
173 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
175 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
177 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
178 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
180 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
185 static void tc3589x_gpio_irq_lock(struct irq_data *d)
187 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
188 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
190 mutex_lock(&tc3589x_gpio->irq_lock);
193 static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
195 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
196 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
197 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
198 static const u8 regmap[] = {
199 [REG_IBE] = TC3589x_GPIOIBE0,
200 [REG_IEV] = TC3589x_GPIOIEV0,
201 [REG_IS] = TC3589x_GPIOIS0,
202 [REG_IE] = TC3589x_GPIOIE0,
203 [REG_DIRECT] = TC3589x_DIRECT0,
207 for (i = 0; i < CACHE_NR_REGS; i++) {
208 for (j = 0; j < CACHE_NR_BANKS; j++) {
209 u8 old = tc3589x_gpio->oldregs[i][j];
210 u8 new = tc3589x_gpio->regs[i][j];
215 tc3589x_gpio->oldregs[i][j] = new;
216 tc3589x_reg_write(tc3589x, regmap[i] + j, new);
220 mutex_unlock(&tc3589x_gpio->irq_lock);
223 static void tc3589x_gpio_irq_mask(struct irq_data *d)
225 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
226 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
227 int offset = d->hwirq;
228 int regoffset = offset / 8;
229 int mask = BIT(offset % 8);
231 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
232 tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
235 static void tc3589x_gpio_irq_unmask(struct irq_data *d)
237 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
238 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
239 int offset = d->hwirq;
240 int regoffset = offset / 8;
241 int mask = BIT(offset % 8);
243 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
244 tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
247 static struct irq_chip tc3589x_gpio_irq_chip = {
248 .name = "tc3589x-gpio",
249 .irq_bus_lock = tc3589x_gpio_irq_lock,
250 .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
251 .irq_mask = tc3589x_gpio_irq_mask,
252 .irq_unmask = tc3589x_gpio_irq_unmask,
253 .irq_set_type = tc3589x_gpio_irq_set_type,
256 static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
258 struct tc3589x_gpio *tc3589x_gpio = dev;
259 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
260 u8 status[CACHE_NR_BANKS];
264 ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
265 ARRAY_SIZE(status), status);
269 for (i = 0; i < ARRAY_SIZE(status); i++) {
270 unsigned int stat = status[i];
275 int bit = __ffs(stat);
276 int line = i * 8 + bit;
277 int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
280 handle_nested_irq(irq);
284 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
290 static int tc3589x_gpio_probe(struct platform_device *pdev)
292 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
293 struct device_node *np = pdev->dev.of_node;
294 struct tc3589x_gpio *tc3589x_gpio;
295 struct gpio_irq_chip *girq;
300 dev_err(&pdev->dev, "No Device Tree node found\n");
304 irq = platform_get_irq(pdev, 0);
308 tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
313 mutex_init(&tc3589x_gpio->irq_lock);
315 tc3589x_gpio->dev = &pdev->dev;
316 tc3589x_gpio->tc3589x = tc3589x;
318 tc3589x_gpio->chip = template_chip;
319 tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
320 tc3589x_gpio->chip.parent = &pdev->dev;
321 tc3589x_gpio->chip.base = -1;
323 girq = &tc3589x_gpio->chip.irq;
324 girq->chip = &tc3589x_gpio_irq_chip;
325 /* This will let us handle the parent IRQ in the driver */
326 girq->parent_handler = NULL;
327 girq->num_parents = 0;
328 girq->parents = NULL;
329 girq->default_type = IRQ_TYPE_NONE;
330 girq->handler = handle_simple_irq;
331 girq->threaded = true;
333 /* Bring the GPIO module out of reset */
334 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
335 TC3589x_RSTCTRL_GPIRST, 0);
339 /* For tc35894, have to disable Direct KBD interrupts,
340 * else IRQST will always be 0x20, IRQN low level, can't
341 * clear the irq status.
342 * TODO: need more test on other tc3589x chip.
345 ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
346 TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
350 ret = devm_request_threaded_irq(&pdev->dev,
351 irq, NULL, tc3589x_gpio_irq,
352 IRQF_ONESHOT, "tc3589x-gpio",
355 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
359 return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio);
362 static struct platform_driver tc3589x_gpio_driver = {
363 .driver.name = "tc3589x-gpio",
364 .probe = tc3589x_gpio_probe,
367 static int __init tc3589x_gpio_init(void)
369 return platform_driver_register(&tc3589x_gpio_driver);
371 subsys_initcall(tc3589x_gpio_init);