2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 static LIST_HEAD(omap_gpio_list);
52 struct list_head node;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
75 int context_loss_count;
77 bool workaround_enabled;
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
82 struct omap_gpio_reg_offs *regs;
85 #define GPIO_MOD_CTRL_BIT BIT(0)
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
90 static void omap_gpio_unmask_irq(struct irq_data *d);
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return gpiochip_get_data(chip);
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
101 void __iomem *reg = bank->base;
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
119 void __iomem *reg = bank->base;
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
130 writel_relaxed(l, reg);
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
141 l = readl_relaxed(reg);
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
152 void __iomem *reg = bank->base + bank->regs->datain;
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
159 void __iomem *reg = bank->base + bank->regs->dataout;
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
166 int l = readl_relaxed(base + reg);
173 writel_relaxed(l, base + reg);
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
212 * Return: 0 on success, negative error otherwise.
214 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
220 bool enable = !!debounce;
222 if (!bank->dbck_flag)
226 debounce = DIV_ROUND_UP(debounce, 31) - 1;
227 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
233 clk_enable(bank->dbck);
234 reg = bank->base + bank->regs->debounce;
235 writel_relaxed(debounce, reg);
237 reg = bank->base + bank->regs->debounce_en;
238 val = readl_relaxed(reg);
244 bank->dbck_enable_mask = val;
246 writel_relaxed(val, reg);
247 clk_disable(bank->dbck);
249 * Enable debounce clock per module.
250 * This call is mandatory because in omap_gpio_request() when
251 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
252 * runtime callbck fails to turn on dbck because dbck_enable_mask
253 * used within _gpio_dbck_enable() is still not initialized at
254 * that point. Therefore we have to enable dbck here.
256 omap_gpio_dbck_enable(bank);
257 if (bank->dbck_enable_mask) {
258 bank->context.debounce = debounce;
259 bank->context.debounce_en = val;
266 * omap_clear_gpio_debounce - clear debounce settings for a gpio
267 * @bank: the gpio bank we're acting upon
268 * @offset: the gpio number on this @bank
270 * If a gpio is using debounce, then clear the debounce enable bit and if
271 * this is the only gpio in this bank using debounce, then clear the debounce
272 * time too. The debounce clock will also be disabled when calling this function
273 * if this is the only gpio in the bank using debounce.
275 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
277 u32 gpio_bit = BIT(offset);
279 if (!bank->dbck_flag)
282 if (!(bank->dbck_enable_mask & gpio_bit))
285 bank->dbck_enable_mask &= ~gpio_bit;
286 bank->context.debounce_en &= ~gpio_bit;
287 writel_relaxed(bank->context.debounce_en,
288 bank->base + bank->regs->debounce_en);
290 if (!bank->dbck_enable_mask) {
291 bank->context.debounce = 0;
292 writel_relaxed(bank->context.debounce, bank->base +
293 bank->regs->debounce);
294 clk_disable(bank->dbck);
295 bank->dbck_enabled = false;
300 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
301 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
302 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
303 * are capable waking up the system from off mode.
305 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
307 u32 no_wake = bank->non_wakeup_gpios;
310 return !!(~no_wake & gpio_mask);
315 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
318 void __iomem *base = bank->base;
319 u32 gpio_bit = BIT(gpio);
321 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
322 trigger & IRQ_TYPE_LEVEL_LOW);
323 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
324 trigger & IRQ_TYPE_LEVEL_HIGH);
325 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
326 trigger & IRQ_TYPE_EDGE_RISING);
327 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
328 trigger & IRQ_TYPE_EDGE_FALLING);
330 bank->context.leveldetect0 =
331 readl_relaxed(bank->base + bank->regs->leveldetect0);
332 bank->context.leveldetect1 =
333 readl_relaxed(bank->base + bank->regs->leveldetect1);
334 bank->context.risingdetect =
335 readl_relaxed(bank->base + bank->regs->risingdetect);
336 bank->context.fallingdetect =
337 readl_relaxed(bank->base + bank->regs->fallingdetect);
339 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
340 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
341 bank->context.wake_en =
342 readl_relaxed(bank->base + bank->regs->wkup_en);
345 /* This part needs to be executed always for OMAP{34xx, 44xx} */
346 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
348 * Log the edge gpio and manually trigger the IRQ
349 * after resume if the input level changes
350 * to avoid irq lost during PER RET/OFF mode
351 * Applies for omap2 non-wakeup gpio and all omap3 gpios
353 if (trigger & IRQ_TYPE_EDGE_BOTH)
354 bank->enabled_non_wakeup_gpios |= gpio_bit;
356 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
360 readl_relaxed(bank->base + bank->regs->leveldetect0) |
361 readl_relaxed(bank->base + bank->regs->leveldetect1);
364 #ifdef CONFIG_ARCH_OMAP1
366 * This only applies to chips that can't do both rising and falling edge
367 * detection at once. For all other chips, this function is a noop.
369 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
371 void __iomem *reg = bank->base;
374 if (!bank->regs->irqctrl)
377 reg += bank->regs->irqctrl;
379 l = readl_relaxed(reg);
385 writel_relaxed(l, reg);
388 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
391 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
394 void __iomem *reg = bank->base;
395 void __iomem *base = bank->base;
398 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
399 omap_set_gpio_trigger(bank, gpio, trigger);
400 } else if (bank->regs->irqctrl) {
401 reg += bank->regs->irqctrl;
403 l = readl_relaxed(reg);
404 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
405 bank->toggle_mask |= BIT(gpio);
406 if (trigger & IRQ_TYPE_EDGE_RISING)
408 else if (trigger & IRQ_TYPE_EDGE_FALLING)
413 writel_relaxed(l, reg);
414 } else if (bank->regs->edgectrl1) {
416 reg += bank->regs->edgectrl2;
418 reg += bank->regs->edgectrl1;
421 l = readl_relaxed(reg);
422 l &= ~(3 << (gpio << 1));
423 if (trigger & IRQ_TYPE_EDGE_RISING)
424 l |= 2 << (gpio << 1);
425 if (trigger & IRQ_TYPE_EDGE_FALLING)
428 /* Enable wake-up during idle for dynamic tick */
429 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
430 bank->context.wake_en =
431 readl_relaxed(bank->base + bank->regs->wkup_en);
432 writel_relaxed(l, reg);
437 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
439 if (bank->regs->pinctrl) {
440 void __iomem *reg = bank->base + bank->regs->pinctrl;
442 /* Claim the pin for MPU */
443 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
446 if (bank->regs->ctrl && !BANK_USED(bank)) {
447 void __iomem *reg = bank->base + bank->regs->ctrl;
450 ctrl = readl_relaxed(reg);
451 /* Module is enabled, clocks are not gated */
452 ctrl &= ~GPIO_MOD_CTRL_BIT;
453 writel_relaxed(ctrl, reg);
454 bank->context.ctrl = ctrl;
458 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
460 void __iomem *base = bank->base;
462 if (bank->regs->wkup_en &&
463 !LINE_USED(bank->mod_usage, offset) &&
464 !LINE_USED(bank->irq_usage, offset)) {
465 /* Disable wake-up during idle for dynamic tick */
466 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
467 bank->context.wake_en =
468 readl_relaxed(bank->base + bank->regs->wkup_en);
471 if (bank->regs->ctrl && !BANK_USED(bank)) {
472 void __iomem *reg = bank->base + bank->regs->ctrl;
475 ctrl = readl_relaxed(reg);
476 /* Module is disabled, clocks are gated */
477 ctrl |= GPIO_MOD_CTRL_BIT;
478 writel_relaxed(ctrl, reg);
479 bank->context.ctrl = ctrl;
483 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
485 void __iomem *reg = bank->base + bank->regs->direction;
487 return readl_relaxed(reg) & BIT(offset);
490 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
492 if (!LINE_USED(bank->mod_usage, offset)) {
493 omap_enable_gpio_module(bank, offset);
494 omap_set_gpio_direction(bank, offset, 1);
496 bank->irq_usage |= BIT(offset);
499 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
501 struct gpio_bank *bank = omap_irq_data_get_bank(d);
504 unsigned offset = d->hwirq;
506 if (type & ~IRQ_TYPE_SENSE_MASK)
509 if (!bank->regs->leveldetect0 &&
510 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
513 raw_spin_lock_irqsave(&bank->lock, flags);
514 retval = omap_set_gpio_triggering(bank, offset, type);
516 raw_spin_unlock_irqrestore(&bank->lock, flags);
519 omap_gpio_init_irq(bank, offset);
520 if (!omap_gpio_is_input(bank, offset)) {
521 raw_spin_unlock_irqrestore(&bank->lock, flags);
525 raw_spin_unlock_irqrestore(&bank->lock, flags);
527 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
528 irq_set_handler_locked(d, handle_level_irq);
529 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
530 irq_set_handler_locked(d, handle_edge_irq);
538 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
540 void __iomem *reg = bank->base;
542 reg += bank->regs->irqstatus;
543 writel_relaxed(gpio_mask, reg);
545 /* Workaround for clearing DSP GPIO interrupts to allow retention */
546 if (bank->regs->irqstatus2) {
547 reg = bank->base + bank->regs->irqstatus2;
548 writel_relaxed(gpio_mask, reg);
551 /* Flush posted write for the irq status to avoid spurious interrupts */
555 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
558 omap_clear_gpio_irqbank(bank, BIT(offset));
561 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
563 void __iomem *reg = bank->base;
565 u32 mask = (BIT(bank->width)) - 1;
567 reg += bank->regs->irqenable;
568 l = readl_relaxed(reg);
569 if (bank->regs->irqenable_inv)
575 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
577 void __iomem *reg = bank->base;
580 if (bank->regs->set_irqenable) {
581 reg += bank->regs->set_irqenable;
583 bank->context.irqenable1 |= gpio_mask;
585 reg += bank->regs->irqenable;
586 l = readl_relaxed(reg);
587 if (bank->regs->irqenable_inv)
591 bank->context.irqenable1 = l;
594 writel_relaxed(l, reg);
597 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
599 void __iomem *reg = bank->base;
602 if (bank->regs->clr_irqenable) {
603 reg += bank->regs->clr_irqenable;
605 bank->context.irqenable1 &= ~gpio_mask;
607 reg += bank->regs->irqenable;
608 l = readl_relaxed(reg);
609 if (bank->regs->irqenable_inv)
613 bank->context.irqenable1 = l;
616 writel_relaxed(l, reg);
619 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
620 unsigned offset, int enable)
623 omap_enable_gpio_irqbank(bank, BIT(offset));
625 omap_disable_gpio_irqbank(bank, BIT(offset));
628 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
629 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
631 struct gpio_bank *bank = omap_irq_data_get_bank(d);
633 return irq_set_irq_wake(bank->irq, enable);
636 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
638 struct gpio_bank *bank = gpiochip_get_data(chip);
642 * If this is the first gpio_request for the bank,
643 * enable the bank module.
645 if (!BANK_USED(bank))
646 pm_runtime_get_sync(chip->parent);
648 raw_spin_lock_irqsave(&bank->lock, flags);
649 omap_enable_gpio_module(bank, offset);
650 bank->mod_usage |= BIT(offset);
651 raw_spin_unlock_irqrestore(&bank->lock, flags);
656 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
658 struct gpio_bank *bank = gpiochip_get_data(chip);
661 raw_spin_lock_irqsave(&bank->lock, flags);
662 bank->mod_usage &= ~(BIT(offset));
663 if (!LINE_USED(bank->irq_usage, offset)) {
664 omap_set_gpio_direction(bank, offset, 1);
665 omap_clear_gpio_debounce(bank, offset);
667 omap_disable_gpio_module(bank, offset);
668 raw_spin_unlock_irqrestore(&bank->lock, flags);
671 * If this is the last gpio to be freed in the bank,
672 * disable the bank module.
674 if (!BANK_USED(bank))
675 pm_runtime_put(chip->parent);
679 * We need to unmask the GPIO bank interrupt as soon as possible to
680 * avoid missing GPIO interrupts for other lines in the bank.
681 * Then we need to mask-read-clear-unmask the triggered GPIO lines
682 * in the bank to avoid missing nested interrupts for a GPIO line.
683 * If we wait to unmask individual GPIO lines in the bank after the
684 * line's interrupt handler has been run, we may miss some nested
687 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
689 void __iomem *isr_reg = NULL;
692 struct gpio_bank *bank = gpiobank;
693 unsigned long wa_lock_flags;
694 unsigned long lock_flags;
696 isr_reg = bank->base + bank->regs->irqstatus;
697 if (WARN_ON(!isr_reg))
700 pm_runtime_get_sync(bank->chip.parent);
703 u32 isr_saved, level_mask = 0;
706 raw_spin_lock_irqsave(&bank->lock, lock_flags);
708 enabled = omap_get_gpio_irqbank_mask(bank);
709 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
711 if (bank->level_mask)
712 level_mask = bank->level_mask & enabled;
714 /* clear edge sensitive interrupts before handler(s) are
715 called so that we don't miss any interrupt occurred while
717 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
718 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
719 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
721 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
730 raw_spin_lock_irqsave(&bank->lock, lock_flags);
732 * Some chips can't respond to both rising and falling
733 * at the same time. If this irq was requested with
734 * both flags, we need to flip the ICR data for the IRQ
735 * to respond to the IRQ for the opposite direction.
736 * This will be indicated in the bank toggle_mask.
738 if (bank->toggle_mask & (BIT(bit)))
739 omap_toggle_gpio_edge_triggering(bank, bit);
741 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
743 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
745 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
748 raw_spin_unlock_irqrestore(&bank->wa_lock,
753 pm_runtime_put(bank->chip.parent);
757 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
759 struct gpio_bank *bank = omap_irq_data_get_bank(d);
761 unsigned offset = d->hwirq;
763 raw_spin_lock_irqsave(&bank->lock, flags);
765 if (!LINE_USED(bank->mod_usage, offset))
766 omap_set_gpio_direction(bank, offset, 1);
767 else if (!omap_gpio_is_input(bank, offset))
769 omap_enable_gpio_module(bank, offset);
770 bank->irq_usage |= BIT(offset);
772 raw_spin_unlock_irqrestore(&bank->lock, flags);
773 omap_gpio_unmask_irq(d);
777 raw_spin_unlock_irqrestore(&bank->lock, flags);
781 static void omap_gpio_irq_shutdown(struct irq_data *d)
783 struct gpio_bank *bank = omap_irq_data_get_bank(d);
785 unsigned offset = d->hwirq;
787 raw_spin_lock_irqsave(&bank->lock, flags);
788 bank->irq_usage &= ~(BIT(offset));
789 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
790 omap_clear_gpio_irqstatus(bank, offset);
791 omap_set_gpio_irqenable(bank, offset, 0);
792 if (!LINE_USED(bank->mod_usage, offset))
793 omap_clear_gpio_debounce(bank, offset);
794 omap_disable_gpio_module(bank, offset);
795 raw_spin_unlock_irqrestore(&bank->lock, flags);
798 static void omap_gpio_irq_bus_lock(struct irq_data *data)
800 struct gpio_bank *bank = omap_irq_data_get_bank(data);
802 if (!BANK_USED(bank))
803 pm_runtime_get_sync(bank->chip.parent);
806 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
808 struct gpio_bank *bank = omap_irq_data_get_bank(data);
811 * If this is the last IRQ to be freed in the bank,
812 * disable the bank module.
814 if (!BANK_USED(bank))
815 pm_runtime_put(bank->chip.parent);
818 static void omap_gpio_ack_irq(struct irq_data *d)
820 struct gpio_bank *bank = omap_irq_data_get_bank(d);
821 unsigned offset = d->hwirq;
823 omap_clear_gpio_irqstatus(bank, offset);
826 static void omap_gpio_mask_irq(struct irq_data *d)
828 struct gpio_bank *bank = omap_irq_data_get_bank(d);
829 unsigned offset = d->hwirq;
832 raw_spin_lock_irqsave(&bank->lock, flags);
833 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
834 omap_set_gpio_irqenable(bank, offset, 0);
835 raw_spin_unlock_irqrestore(&bank->lock, flags);
838 static void omap_gpio_unmask_irq(struct irq_data *d)
840 struct gpio_bank *bank = omap_irq_data_get_bank(d);
841 unsigned offset = d->hwirq;
842 u32 trigger = irqd_get_trigger_type(d);
845 raw_spin_lock_irqsave(&bank->lock, flags);
846 omap_set_gpio_irqenable(bank, offset, 1);
849 * For level-triggered GPIOs, clearing must be done after the source
850 * is cleared, thus after the handler has run. OMAP4 needs this done
851 * after enabing the interrupt to clear the wakeup status.
853 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
854 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
855 omap_clear_gpio_irqstatus(bank, offset);
858 omap_set_gpio_triggering(bank, offset, trigger);
860 raw_spin_unlock_irqrestore(&bank->lock, flags);
863 /*---------------------------------------------------------------------*/
865 static int omap_mpuio_suspend_noirq(struct device *dev)
867 struct platform_device *pdev = to_platform_device(dev);
868 struct gpio_bank *bank = platform_get_drvdata(pdev);
869 void __iomem *mask_reg = bank->base +
870 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
873 raw_spin_lock_irqsave(&bank->lock, flags);
874 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
875 raw_spin_unlock_irqrestore(&bank->lock, flags);
880 static int omap_mpuio_resume_noirq(struct device *dev)
882 struct platform_device *pdev = to_platform_device(dev);
883 struct gpio_bank *bank = platform_get_drvdata(pdev);
884 void __iomem *mask_reg = bank->base +
885 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
888 raw_spin_lock_irqsave(&bank->lock, flags);
889 writel_relaxed(bank->context.wake_en, mask_reg);
890 raw_spin_unlock_irqrestore(&bank->lock, flags);
895 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
896 .suspend_noirq = omap_mpuio_suspend_noirq,
897 .resume_noirq = omap_mpuio_resume_noirq,
900 /* use platform_driver for this. */
901 static struct platform_driver omap_mpuio_driver = {
904 .pm = &omap_mpuio_dev_pm_ops,
908 static struct platform_device omap_mpuio_device = {
912 .driver = &omap_mpuio_driver.driver,
914 /* could list the /proc/iomem resources */
917 static inline void omap_mpuio_init(struct gpio_bank *bank)
919 platform_set_drvdata(&omap_mpuio_device, bank);
921 if (platform_driver_register(&omap_mpuio_driver) == 0)
922 (void) platform_device_register(&omap_mpuio_device);
925 /*---------------------------------------------------------------------*/
927 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
929 struct gpio_bank *bank;
934 bank = gpiochip_get_data(chip);
935 reg = bank->base + bank->regs->direction;
936 raw_spin_lock_irqsave(&bank->lock, flags);
937 dir = !!(readl_relaxed(reg) & BIT(offset));
938 raw_spin_unlock_irqrestore(&bank->lock, flags);
942 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
944 struct gpio_bank *bank;
947 bank = gpiochip_get_data(chip);
948 raw_spin_lock_irqsave(&bank->lock, flags);
949 omap_set_gpio_direction(bank, offset, 1);
950 raw_spin_unlock_irqrestore(&bank->lock, flags);
954 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
956 struct gpio_bank *bank;
958 bank = gpiochip_get_data(chip);
960 if (omap_gpio_is_input(bank, offset))
961 return omap_get_gpio_datain(bank, offset);
963 return omap_get_gpio_dataout(bank, offset);
966 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
968 struct gpio_bank *bank;
971 bank = gpiochip_get_data(chip);
972 raw_spin_lock_irqsave(&bank->lock, flags);
973 bank->set_dataout(bank, offset, value);
974 omap_set_gpio_direction(bank, offset, 0);
975 raw_spin_unlock_irqrestore(&bank->lock, flags);
979 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
982 struct gpio_bank *bank;
986 bank = gpiochip_get_data(chip);
988 raw_spin_lock_irqsave(&bank->lock, flags);
989 ret = omap2_set_gpio_debounce(bank, offset, debounce);
990 raw_spin_unlock_irqrestore(&bank->lock, flags);
993 dev_info(chip->parent,
994 "Could not set line %u debounce to %u microseconds (%d)",
995 offset, debounce, ret);
1000 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1002 struct gpio_bank *bank;
1003 unsigned long flags;
1005 bank = gpiochip_get_data(chip);
1006 raw_spin_lock_irqsave(&bank->lock, flags);
1007 bank->set_dataout(bank, offset, value);
1008 raw_spin_unlock_irqrestore(&bank->lock, flags);
1011 /*---------------------------------------------------------------------*/
1013 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1018 if (called || bank->regs->revision == USHRT_MAX)
1021 rev = readw_relaxed(bank->base + bank->regs->revision);
1022 pr_info("OMAP GPIO hardware version %d.%d\n",
1023 (rev >> 4) & 0x0f, rev & 0x0f);
1028 static void omap_gpio_mod_init(struct gpio_bank *bank)
1030 void __iomem *base = bank->base;
1033 if (bank->width == 16)
1036 if (bank->is_mpuio) {
1037 writel_relaxed(l, bank->base + bank->regs->irqenable);
1041 omap_gpio_rmw(base, bank->regs->irqenable, l,
1042 bank->regs->irqenable_inv);
1043 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1044 !bank->regs->irqenable_inv);
1045 if (bank->regs->debounce_en)
1046 writel_relaxed(0, base + bank->regs->debounce_en);
1048 /* Save OE default value (0xffffffff) in the context */
1049 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1050 /* Initialize interface clk ungated, module enabled */
1051 if (bank->regs->ctrl)
1052 writel_relaxed(0, base + bank->regs->ctrl);
1055 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1062 * REVISIT eventually switch from OMAP-specific gpio structs
1063 * over to the generic ones
1065 bank->chip.request = omap_gpio_request;
1066 bank->chip.free = omap_gpio_free;
1067 bank->chip.get_direction = omap_gpio_get_direction;
1068 bank->chip.direction_input = omap_gpio_input;
1069 bank->chip.get = omap_gpio_get;
1070 bank->chip.direction_output = omap_gpio_output;
1071 bank->chip.set_debounce = omap_gpio_debounce;
1072 bank->chip.set = omap_gpio_set;
1073 if (bank->is_mpuio) {
1074 bank->chip.label = "mpuio";
1075 if (bank->regs->wkup_en)
1076 bank->chip.parent = &omap_mpuio_device.dev;
1077 bank->chip.base = OMAP_MPUIO(0);
1079 bank->chip.label = "gpio";
1080 bank->chip.base = gpio;
1082 bank->chip.ngpio = bank->width;
1084 ret = gpiochip_add_data(&bank->chip, bank);
1086 dev_err(bank->chip.parent,
1087 "Could not register gpio chip %d\n", ret);
1091 if (!bank->is_mpuio)
1092 gpio += bank->width;
1094 #ifdef CONFIG_ARCH_OMAP1
1096 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1097 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1099 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1101 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1106 /* MPUIO is a bit different, reading IRQ status clears it */
1107 if (bank->is_mpuio) {
1108 irqc->irq_ack = dummy_irq_chip.irq_ack;
1109 if (!bank->regs->wkup_en)
1110 irqc->irq_set_wake = NULL;
1113 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1114 irq_base, handle_bad_irq,
1118 dev_err(bank->chip.parent,
1119 "Couldn't add irqchip to gpiochip %d\n", ret);
1120 gpiochip_remove(&bank->chip);
1124 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1126 ret = devm_request_irq(bank->chip.parent, bank->irq,
1127 omap_gpio_irq_handler,
1128 0, dev_name(bank->chip.parent), bank);
1130 gpiochip_remove(&bank->chip);
1135 static const struct of_device_id omap_gpio_match[];
1137 static int omap_gpio_probe(struct platform_device *pdev)
1139 struct device *dev = &pdev->dev;
1140 struct device_node *node = dev->of_node;
1141 const struct of_device_id *match;
1142 const struct omap_gpio_platform_data *pdata;
1143 struct resource *res;
1144 struct gpio_bank *bank;
1145 struct irq_chip *irqc;
1148 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1150 pdata = match ? match->data : dev_get_platdata(dev);
1154 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1156 dev_err(dev, "Memory alloc failed\n");
1160 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1164 irqc->irq_startup = omap_gpio_irq_startup,
1165 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1166 irqc->irq_ack = omap_gpio_ack_irq,
1167 irqc->irq_mask = omap_gpio_mask_irq,
1168 irqc->irq_unmask = omap_gpio_unmask_irq,
1169 irqc->irq_set_type = omap_gpio_irq_type,
1170 irqc->irq_set_wake = omap_gpio_wake_enable,
1171 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1172 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1173 irqc->name = dev_name(&pdev->dev);
1174 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1176 bank->irq = platform_get_irq(pdev, 0);
1177 if (bank->irq <= 0) {
1180 if (bank->irq != -EPROBE_DEFER)
1182 "can't get irq resource ret=%d\n", bank->irq);
1186 bank->chip.parent = dev;
1187 bank->chip.owner = THIS_MODULE;
1188 bank->dbck_flag = pdata->dbck_flag;
1189 bank->stride = pdata->bank_stride;
1190 bank->width = pdata->bank_width;
1191 bank->is_mpuio = pdata->is_mpuio;
1192 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1193 bank->regs = pdata->regs;
1194 #ifdef CONFIG_OF_GPIO
1195 bank->chip.of_node = of_node_get(node);
1198 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1199 bank->loses_context = true;
1201 bank->loses_context = pdata->loses_context;
1203 if (bank->loses_context)
1204 bank->get_context_loss_count =
1205 pdata->get_context_loss_count;
1208 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1209 bank->set_dataout = omap_set_gpio_dataout_reg;
1211 bank->set_dataout = omap_set_gpio_dataout_mask;
1213 raw_spin_lock_init(&bank->lock);
1214 raw_spin_lock_init(&bank->wa_lock);
1216 /* Static mapping, never released */
1217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218 bank->base = devm_ioremap_resource(dev, res);
1219 if (IS_ERR(bank->base)) {
1220 return PTR_ERR(bank->base);
1223 if (bank->dbck_flag) {
1224 bank->dbck = devm_clk_get(dev, "dbclk");
1225 if (IS_ERR(bank->dbck)) {
1227 "Could not get gpio dbck. Disable debounce\n");
1228 bank->dbck_flag = false;
1230 clk_prepare(bank->dbck);
1234 platform_set_drvdata(pdev, bank);
1236 pm_runtime_enable(dev);
1237 pm_runtime_irq_safe(dev);
1238 pm_runtime_get_sync(dev);
1241 omap_mpuio_init(bank);
1243 omap_gpio_mod_init(bank);
1245 ret = omap_gpio_chip_init(bank, irqc);
1247 pm_runtime_put_sync(dev);
1248 pm_runtime_disable(dev);
1252 omap_gpio_show_rev(bank);
1254 pm_runtime_put(dev);
1256 list_add_tail(&bank->node, &omap_gpio_list);
1261 static int omap_gpio_remove(struct platform_device *pdev)
1263 struct gpio_bank *bank = platform_get_drvdata(pdev);
1265 list_del(&bank->node);
1266 gpiochip_remove(&bank->chip);
1267 pm_runtime_disable(&pdev->dev);
1268 if (bank->dbck_flag)
1269 clk_unprepare(bank->dbck);
1274 #ifdef CONFIG_ARCH_OMAP2PLUS
1276 #if defined(CONFIG_PM)
1277 static void omap_gpio_restore_context(struct gpio_bank *bank);
1279 static int omap_gpio_runtime_suspend(struct device *dev)
1281 struct platform_device *pdev = to_platform_device(dev);
1282 struct gpio_bank *bank = platform_get_drvdata(pdev);
1284 unsigned long flags;
1285 u32 wake_low, wake_hi;
1287 raw_spin_lock_irqsave(&bank->lock, flags);
1290 * Only edges can generate a wakeup event to the PRCM.
1292 * Therefore, ensure any wake-up capable GPIOs have
1293 * edge-detection enabled before going idle to ensure a wakeup
1294 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1297 * The normal values will be restored upon ->runtime_resume()
1298 * by writing back the values saved in bank->context.
1300 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1302 writel_relaxed(wake_low | bank->context.fallingdetect,
1303 bank->base + bank->regs->fallingdetect);
1304 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1306 writel_relaxed(wake_hi | bank->context.risingdetect,
1307 bank->base + bank->regs->risingdetect);
1309 if (!bank->enabled_non_wakeup_gpios)
1310 goto update_gpio_context_count;
1312 if (bank->power_mode != OFF_MODE) {
1313 bank->power_mode = 0;
1314 goto update_gpio_context_count;
1317 * If going to OFF, remove triggering for all
1318 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1319 * generated. See OMAP2420 Errata item 1.101.
1321 bank->saved_datain = readl_relaxed(bank->base +
1322 bank->regs->datain);
1323 l1 = bank->context.fallingdetect;
1324 l2 = bank->context.risingdetect;
1326 l1 &= ~bank->enabled_non_wakeup_gpios;
1327 l2 &= ~bank->enabled_non_wakeup_gpios;
1329 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1330 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1332 bank->workaround_enabled = true;
1334 update_gpio_context_count:
1335 if (bank->get_context_loss_count)
1336 bank->context_loss_count =
1337 bank->get_context_loss_count(dev);
1339 omap_gpio_dbck_disable(bank);
1340 raw_spin_unlock_irqrestore(&bank->lock, flags);
1345 static void omap_gpio_init_context(struct gpio_bank *p);
1347 static int omap_gpio_runtime_resume(struct device *dev)
1349 struct platform_device *pdev = to_platform_device(dev);
1350 struct gpio_bank *bank = platform_get_drvdata(pdev);
1351 u32 l = 0, gen, gen0, gen1;
1352 unsigned long flags;
1355 raw_spin_lock_irqsave(&bank->lock, flags);
1358 * On the first resume during the probe, the context has not
1359 * been initialised and so initialise it now. Also initialise
1360 * the context loss count.
1362 if (bank->loses_context && !bank->context_valid) {
1363 omap_gpio_init_context(bank);
1365 if (bank->get_context_loss_count)
1366 bank->context_loss_count =
1367 bank->get_context_loss_count(dev);
1370 omap_gpio_dbck_enable(bank);
1373 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1374 * GPIOs were set to edge trigger also in order to be able to
1375 * generate a PRCM wakeup. Here we restore the
1376 * pre-runtime_suspend() values for edge triggering.
1378 writel_relaxed(bank->context.fallingdetect,
1379 bank->base + bank->regs->fallingdetect);
1380 writel_relaxed(bank->context.risingdetect,
1381 bank->base + bank->regs->risingdetect);
1383 if (bank->loses_context) {
1384 if (!bank->get_context_loss_count) {
1385 omap_gpio_restore_context(bank);
1387 c = bank->get_context_loss_count(dev);
1388 if (c != bank->context_loss_count) {
1389 omap_gpio_restore_context(bank);
1391 raw_spin_unlock_irqrestore(&bank->lock, flags);
1397 if (!bank->workaround_enabled) {
1398 raw_spin_unlock_irqrestore(&bank->lock, flags);
1402 l = readl_relaxed(bank->base + bank->regs->datain);
1405 * Check if any of the non-wakeup interrupt GPIOs have changed
1406 * state. If so, generate an IRQ by software. This is
1407 * horribly racy, but it's the best we can do to work around
1410 l ^= bank->saved_datain;
1411 l &= bank->enabled_non_wakeup_gpios;
1414 * No need to generate IRQs for the rising edge for gpio IRQs
1415 * configured with falling edge only; and vice versa.
1417 gen0 = l & bank->context.fallingdetect;
1418 gen0 &= bank->saved_datain;
1420 gen1 = l & bank->context.risingdetect;
1421 gen1 &= ~(bank->saved_datain);
1423 /* FIXME: Consider GPIO IRQs with level detections properly! */
1424 gen = l & (~(bank->context.fallingdetect) &
1425 ~(bank->context.risingdetect));
1426 /* Consider all GPIO IRQs needed to be updated */
1432 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1433 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1435 if (!bank->regs->irqstatus_raw0) {
1436 writel_relaxed(old0 | gen, bank->base +
1437 bank->regs->leveldetect0);
1438 writel_relaxed(old1 | gen, bank->base +
1439 bank->regs->leveldetect1);
1442 if (bank->regs->irqstatus_raw0) {
1443 writel_relaxed(old0 | l, bank->base +
1444 bank->regs->leveldetect0);
1445 writel_relaxed(old1 | l, bank->base +
1446 bank->regs->leveldetect1);
1448 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1449 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1452 bank->workaround_enabled = false;
1453 raw_spin_unlock_irqrestore(&bank->lock, flags);
1457 #endif /* CONFIG_PM */
1459 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1460 void omap2_gpio_prepare_for_idle(int pwr_mode)
1462 struct gpio_bank *bank;
1464 list_for_each_entry(bank, &omap_gpio_list, node) {
1465 if (!BANK_USED(bank) || !bank->loses_context)
1468 bank->power_mode = pwr_mode;
1470 pm_runtime_put_sync_suspend(bank->chip.parent);
1474 void omap2_gpio_resume_after_idle(void)
1476 struct gpio_bank *bank;
1478 list_for_each_entry(bank, &omap_gpio_list, node) {
1479 if (!BANK_USED(bank) || !bank->loses_context)
1482 pm_runtime_get_sync(bank->chip.parent);
1487 #if defined(CONFIG_PM)
1488 static void omap_gpio_init_context(struct gpio_bank *p)
1490 struct omap_gpio_reg_offs *regs = p->regs;
1491 void __iomem *base = p->base;
1493 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1494 p->context.oe = readl_relaxed(base + regs->direction);
1495 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1496 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1497 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1498 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1499 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1500 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1501 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1503 if (regs->set_dataout && p->regs->clr_dataout)
1504 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1506 p->context.dataout = readl_relaxed(base + regs->dataout);
1508 p->context_valid = true;
1511 static void omap_gpio_restore_context(struct gpio_bank *bank)
1513 writel_relaxed(bank->context.wake_en,
1514 bank->base + bank->regs->wkup_en);
1515 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1516 writel_relaxed(bank->context.leveldetect0,
1517 bank->base + bank->regs->leveldetect0);
1518 writel_relaxed(bank->context.leveldetect1,
1519 bank->base + bank->regs->leveldetect1);
1520 writel_relaxed(bank->context.risingdetect,
1521 bank->base + bank->regs->risingdetect);
1522 writel_relaxed(bank->context.fallingdetect,
1523 bank->base + bank->regs->fallingdetect);
1524 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1525 writel_relaxed(bank->context.dataout,
1526 bank->base + bank->regs->set_dataout);
1528 writel_relaxed(bank->context.dataout,
1529 bank->base + bank->regs->dataout);
1530 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1532 if (bank->dbck_enable_mask) {
1533 writel_relaxed(bank->context.debounce, bank->base +
1534 bank->regs->debounce);
1535 writel_relaxed(bank->context.debounce_en,
1536 bank->base + bank->regs->debounce_en);
1539 writel_relaxed(bank->context.irqenable1,
1540 bank->base + bank->regs->irqenable);
1541 writel_relaxed(bank->context.irqenable2,
1542 bank->base + bank->regs->irqenable2);
1544 #endif /* CONFIG_PM */
1546 #define omap_gpio_runtime_suspend NULL
1547 #define omap_gpio_runtime_resume NULL
1548 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1551 static const struct dev_pm_ops gpio_pm_ops = {
1552 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1556 #if defined(CONFIG_OF)
1557 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1558 .revision = OMAP24XX_GPIO_REVISION,
1559 .direction = OMAP24XX_GPIO_OE,
1560 .datain = OMAP24XX_GPIO_DATAIN,
1561 .dataout = OMAP24XX_GPIO_DATAOUT,
1562 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1563 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1564 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1565 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1566 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1567 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1568 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1569 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1570 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1571 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1572 .ctrl = OMAP24XX_GPIO_CTRL,
1573 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1574 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1575 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1576 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1577 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1580 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1581 .revision = OMAP4_GPIO_REVISION,
1582 .direction = OMAP4_GPIO_OE,
1583 .datain = OMAP4_GPIO_DATAIN,
1584 .dataout = OMAP4_GPIO_DATAOUT,
1585 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1586 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1587 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1588 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1589 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1590 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1591 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1592 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1593 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1594 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1595 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1596 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1597 .ctrl = OMAP4_GPIO_CTRL,
1598 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1599 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1600 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1601 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1602 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1605 static const struct omap_gpio_platform_data omap2_pdata = {
1606 .regs = &omap2_gpio_regs,
1611 static const struct omap_gpio_platform_data omap3_pdata = {
1612 .regs = &omap2_gpio_regs,
1617 static const struct omap_gpio_platform_data omap4_pdata = {
1618 .regs = &omap4_gpio_regs,
1623 static const struct of_device_id omap_gpio_match[] = {
1625 .compatible = "ti,omap4-gpio",
1626 .data = &omap4_pdata,
1629 .compatible = "ti,omap3-gpio",
1630 .data = &omap3_pdata,
1633 .compatible = "ti,omap2-gpio",
1634 .data = &omap2_pdata,
1638 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1641 static struct platform_driver omap_gpio_driver = {
1642 .probe = omap_gpio_probe,
1643 .remove = omap_gpio_remove,
1645 .name = "omap_gpio",
1647 .of_match_table = of_match_ptr(omap_gpio_match),
1652 * gpio driver register needs to be done before
1653 * machine_init functions access gpio APIs.
1654 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1656 static int __init omap_gpio_drv_reg(void)
1658 return platform_driver_register(&omap_gpio_driver);
1660 postcore_initcall(omap_gpio_drv_reg);
1662 static void __exit omap_gpio_exit(void)
1664 platform_driver_unregister(&omap_gpio_driver);
1666 module_exit(omap_gpio_exit);
1668 MODULE_DESCRIPTION("omap gpio driver");
1669 MODULE_ALIAS("platform:gpio-omap");
1670 MODULE_LICENSE("GPL v2");