1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM Serial GPIO Driver
5 * Copyright (C) 2021 Nuvoton Technologies
8 #include <linux/bitfield.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hashtable.h>
12 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/units.h>
20 #define MAX_NR_HW_SGPIO 64
22 #define NPCM_IOXCFG1 0x2A
23 #define NPCM_IOXCFG1_SFT_CLK GENMASK(3, 0)
24 #define NPCM_IOXCFG1_SCLK_POL BIT(4)
25 #define NPCM_IOXCFG1_LDSH_POL BIT(5)
27 #define NPCM_IOXCTS 0x28
28 #define NPCM_IOXCTS_IOXIF_EN BIT(7)
29 #define NPCM_IOXCTS_RD_MODE GENMASK(2, 1)
30 #define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2)
32 #define NPCM_IOXCFG2 0x2B
33 #define NPCM_IOXCFG2_PORT GENMASK(3, 0)
35 #define NPCM_IXOEVCFG_MASK GENMASK(1, 0)
36 #define NPCM_IXOEVCFG_FALLING BIT(1)
37 #define NPCM_IXOEVCFG_RISING BIT(0)
38 #define NPCM_IXOEVCFG_BOTH (NPCM_IXOEVCFG_FALLING | NPCM_IXOEVCFG_RISING)
40 #define NPCM_CLK_MHZ (8 * HZ_PER_MHZ)
41 #define NPCM_750_OPT 6
42 #define NPCM_845_OPT 5
44 #define GPIO_BANK(x) ((x) / 8)
45 #define GPIO_BIT(x) ((x) % 8)
48 * Select the frequency of shift clock.
49 * The shift clock is a division of the APB clock.
52 unsigned int *sft_clk;
53 unsigned int *clk_sel;
58 struct gpio_chip chip;
69 u8 int_type[MAX_NR_HW_SGPIO];
72 struct npcm_sgpio_bank {
86 static const struct npcm_sgpio_bank npcm_sgpio_banks[] = {
102 .event_config = 0x14,
103 .event_status = 0x22,
108 .event_config = 0x16,
109 .event_status = 0x23,
114 .event_config = 0x18,
115 .event_status = 0x24,
120 .event_config = 0x1a,
121 .event_status = 0x25,
126 .event_config = 0x1c,
127 .event_status = 0x26,
132 .event_config = 0x1e,
133 .event_status = 0x27,
137 static void __iomem *bank_reg(struct npcm_sgpio *gpio,
138 const struct npcm_sgpio_bank *bank,
139 const enum npcm_sgpio_reg reg)
143 return gpio->base + bank->rdata_reg;
145 return gpio->base + bank->wdata_reg;
147 return gpio->base + bank->event_config;
149 return gpio->base + bank->event_status;
151 /* actually if code runs to here, it's an error case */
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition");
157 static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset)
159 unsigned int bank = GPIO_BANK(offset);
161 return &npcm_sgpio_banks[bank];
164 static void npcm_sgpio_irqd_to_data(struct irq_data *d,
165 struct npcm_sgpio **gpio,
166 const struct npcm_sgpio_bank **bank,
167 u8 *bit, unsigned int *offset)
169 struct npcm_sgpio *internal;
171 *offset = irqd_to_hwirq(d);
172 internal = irq_data_get_irq_chip_data(d);
175 *offset -= internal->nout_sgpio;
176 *bank = offset_to_bank(*offset);
177 *bit = GPIO_BIT(*offset);
180 static int npcm_sgpio_init_port(struct npcm_sgpio *gpio)
182 u8 in_port, out_port, set_port, reg;
184 in_port = GPIO_BANK(gpio->nin_sgpio);
185 if (GPIO_BIT(gpio->nin_sgpio) > 0)
188 out_port = GPIO_BANK(gpio->nout_sgpio);
189 if (GPIO_BIT(gpio->nout_sgpio) > 0)
192 gpio->in_port = in_port;
193 gpio->out_port = out_port;
194 set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 |
195 (in_port & NPCM_IOXCFG2_PORT);
196 iowrite8(set_port, gpio->base + NPCM_IOXCFG2);
198 reg = ioread8(gpio->base + NPCM_IOXCFG2);
200 return reg == set_port ? 0 : -EINVAL;
204 static int npcm_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
206 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
208 return offset < gpio->nout_sgpio ? -EINVAL : 0;
212 static int npcm_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
214 gc->set(gc, offset, val);
219 static int npcm_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
221 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
223 if (offset < gpio->nout_sgpio)
224 return GPIO_LINE_DIRECTION_OUT;
226 return GPIO_LINE_DIRECTION_IN;
229 static void npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
231 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
232 const struct npcm_sgpio_bank *bank = offset_to_bank(offset);
236 addr = bank_reg(gpio, bank, WRITE_DATA);
240 reg |= BIT(GPIO_BIT(offset));
242 reg &= ~BIT(GPIO_BIT(offset));
247 static int npcm_sgpio_get(struct gpio_chip *gc, unsigned int offset)
249 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
250 const struct npcm_sgpio_bank *bank;
254 if (offset < gpio->nout_sgpio) {
255 bank = offset_to_bank(offset);
256 addr = bank_reg(gpio, bank, WRITE_DATA);
258 offset -= gpio->nout_sgpio;
259 bank = offset_to_bank(offset);
260 addr = bank_reg(gpio, bank, READ_DATA);
265 return !!(reg & BIT(GPIO_BIT(offset)));
268 static void npcm_sgpio_setup_enable(struct npcm_sgpio *gpio, bool enable)
272 reg = ioread8(gpio->base + NPCM_IOXCTS);
273 reg = (reg & ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC;
276 reg |= NPCM_IOXCTS_IOXIF_EN;
278 reg &= ~NPCM_IOXCTS_IOXIF_EN;
280 iowrite8(reg, gpio->base + NPCM_IOXCTS);
283 static int npcm_sgpio_setup_clk(struct npcm_sgpio *gpio,
284 const struct npcm_clk_cfg *clk_cfg)
286 unsigned long apb_freq;
291 apb_freq = clk_get_rate(gpio->pclk);
292 tmp = ioread8(gpio->base + NPCM_IOXCFG1) & ~NPCM_IOXCFG1_SFT_CLK;
294 for (i = clk_cfg->cfg_opt-1; i > 0; i--) {
295 val = apb_freq / clk_cfg->sft_clk[i];
296 if (NPCM_CLK_MHZ > val) {
297 iowrite8(clk_cfg->clk_sel[i] | tmp,
298 gpio->base + NPCM_IOXCFG1);
306 static void npcm_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
307 unsigned long *valid_mask,
310 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
312 /* input GPIOs in the high range */
313 bitmap_set(valid_mask, gpio->nout_sgpio, gpio->nin_sgpio);
314 bitmap_clear(valid_mask, 0, gpio->nout_sgpio);
317 static void npcm_sgpio_irq_set_mask(struct irq_data *d, bool set)
319 const struct npcm_sgpio_bank *bank;
320 struct npcm_sgpio *gpio;
327 npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
328 addr = bank_reg(gpio, bank, EVENT_CFG);
330 reg = ioread16(addr);
332 reg &= ~(NPCM_IXOEVCFG_MASK << (bit * 2));
334 type = gpio->int_type[offset];
335 reg |= (type << (bit * 2));
338 raw_spin_lock_irqsave(&gpio->lock, flags);
340 npcm_sgpio_setup_enable(gpio, false);
342 iowrite16(reg, addr);
344 npcm_sgpio_setup_enable(gpio, true);
346 addr = bank_reg(gpio, bank, EVENT_STS);
351 raw_spin_unlock_irqrestore(&gpio->lock, flags);
354 static void npcm_sgpio_irq_ack(struct irq_data *d)
356 const struct npcm_sgpio_bank *bank;
357 struct npcm_sgpio *gpio;
359 void __iomem *status_addr;
363 npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
364 status_addr = bank_reg(gpio, bank, EVENT_STS);
365 raw_spin_lock_irqsave(&gpio->lock, flags);
366 iowrite8(BIT(bit), status_addr);
367 raw_spin_unlock_irqrestore(&gpio->lock, flags);
370 static void npcm_sgpio_irq_mask(struct irq_data *d)
372 npcm_sgpio_irq_set_mask(d, true);
375 static void npcm_sgpio_irq_unmask(struct irq_data *d)
377 npcm_sgpio_irq_set_mask(d, false);
380 static int npcm_sgpio_set_type(struct irq_data *d, unsigned int type)
382 const struct npcm_sgpio_bank *bank;
383 irq_flow_handler_t handler;
384 struct npcm_sgpio *gpio;
391 npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
393 switch (type & IRQ_TYPE_SENSE_MASK) {
394 case IRQ_TYPE_EDGE_BOTH:
395 val = NPCM_IXOEVCFG_BOTH;
397 case IRQ_TYPE_EDGE_RISING:
398 case IRQ_TYPE_LEVEL_HIGH:
399 val = NPCM_IXOEVCFG_RISING;
401 case IRQ_TYPE_EDGE_FALLING:
402 case IRQ_TYPE_LEVEL_LOW:
403 val = NPCM_IXOEVCFG_FALLING;
409 if (type & IRQ_TYPE_LEVEL_MASK)
410 handler = handle_level_irq;
412 handler = handle_edge_irq;
414 gpio->int_type[offset] = val;
416 raw_spin_lock_irqsave(&gpio->lock, flags);
417 npcm_sgpio_setup_enable(gpio, false);
418 addr = bank_reg(gpio, bank, EVENT_CFG);
419 reg = ioread16(addr);
421 reg |= (val << (bit * 2));
423 iowrite16(reg, addr);
424 npcm_sgpio_setup_enable(gpio, true);
425 raw_spin_unlock_irqrestore(&gpio->lock, flags);
427 irq_set_handler_locked(d, handler);
432 static void npcm_sgpio_irq_handler(struct irq_desc *desc)
434 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
435 struct irq_chip *ic = irq_desc_get_chip(desc);
436 struct npcm_sgpio *gpio = gpiochip_get_data(gc);
437 unsigned int i, j, girq;
440 chained_irq_enter(ic, desc);
442 for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
443 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
445 reg = ioread8(bank_reg(gpio, bank, EVENT_STS));
446 for_each_set_bit(j, ®, 8) {
447 girq = irq_find_mapping(gc->irq.domain,
448 i * 8 + gpio->nout_sgpio + j);
449 generic_handle_domain_irq(gc->irq.domain, girq);
453 chained_irq_exit(ic, desc);
456 static const struct irq_chip sgpio_irq_chip = {
458 .irq_ack = npcm_sgpio_irq_ack,
459 .irq_mask = npcm_sgpio_irq_mask,
460 .irq_unmask = npcm_sgpio_irq_unmask,
461 .irq_set_type = npcm_sgpio_set_type,
462 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
463 GPIOCHIP_IRQ_RESOURCE_HELPERS,
466 static int npcm_sgpio_setup_irqs(struct npcm_sgpio *gpio,
467 struct platform_device *pdev)
470 struct gpio_irq_chip *irq;
472 rc = platform_get_irq(pdev, 0);
478 npcm_sgpio_setup_enable(gpio, false);
480 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
481 for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
482 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
484 iowrite16(0, bank_reg(gpio, bank, EVENT_CFG));
485 iowrite8(0xff, bank_reg(gpio, bank, EVENT_STS));
488 irq = &gpio->chip.irq;
489 gpio_irq_chip_set_chip(irq, &sgpio_irq_chip);
490 irq->init_valid_mask = npcm_sgpio_irq_init_valid_mask;
491 irq->handler = handle_bad_irq;
492 irq->default_type = IRQ_TYPE_NONE;
493 irq->parent_handler = npcm_sgpio_irq_handler;
494 irq->parent_handler_data = gpio;
495 irq->parents = &gpio->irq;
496 irq->num_parents = 1;
501 static int npcm_sgpio_probe(struct platform_device *pdev)
503 struct npcm_sgpio *gpio;
504 const struct npcm_clk_cfg *clk_cfg;
506 u32 nin_gpios, nout_gpios;
508 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
512 gpio->base = devm_platform_ioremap_resource(pdev, 0);
513 if (IS_ERR(gpio->base))
514 return PTR_ERR(gpio->base);
516 clk_cfg = device_get_match_data(&pdev->dev);
520 rc = device_property_read_u32(&pdev->dev, "nuvoton,input-ngpios",
523 return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
525 rc = device_property_read_u32(&pdev->dev, "nuvoton,output-ngpios",
528 return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
530 gpio->nin_sgpio = nin_gpios;
531 gpio->nout_sgpio = nout_gpios;
532 if (gpio->nin_sgpio > MAX_NR_HW_SGPIO ||
533 gpio->nout_sgpio > MAX_NR_HW_SGPIO)
534 return dev_err_probe(&pdev->dev, -EINVAL, "Number of GPIOs exceeds the maximum of %d: input: %d output: %d\n", MAX_NR_HW_SGPIO, nin_gpios, nout_gpios);
536 gpio->pclk = devm_clk_get(&pdev->dev, NULL);
537 if (IS_ERR(gpio->pclk))
538 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->pclk), "Could not get pclk\n");
540 rc = npcm_sgpio_setup_clk(gpio, clk_cfg);
542 return dev_err_probe(&pdev->dev, rc, "Failed to setup clock\n");
544 raw_spin_lock_init(&gpio->lock);
545 gpio->chip.parent = &pdev->dev;
546 gpio->chip.ngpio = gpio->nin_sgpio + gpio->nout_sgpio;
547 gpio->chip.direction_input = npcm_sgpio_dir_in;
548 gpio->chip.direction_output = npcm_sgpio_dir_out;
549 gpio->chip.get_direction = npcm_sgpio_get_direction;
550 gpio->chip.get = npcm_sgpio_get;
551 gpio->chip.set = npcm_sgpio_set;
552 gpio->chip.label = dev_name(&pdev->dev);
553 gpio->chip.base = -1;
555 rc = npcm_sgpio_init_port(gpio);
559 rc = npcm_sgpio_setup_irqs(gpio, pdev);
563 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
565 return dev_err_probe(&pdev->dev, rc, "GPIO registering failed\n");
567 npcm_sgpio_setup_enable(gpio, true);
572 static unsigned int npcm750_SFT_CLK[NPCM_750_OPT] = {
573 1024, 32, 8, 4, 3, 2,
576 static unsigned int npcm750_CLK_SEL[NPCM_750_OPT] = {
577 0x00, 0x05, 0x07, 0x0C, 0x0D, 0x0E,
580 static unsigned int npcm845_SFT_CLK[NPCM_845_OPT] = {
584 static unsigned int npcm845_CLK_SEL[NPCM_845_OPT] = {
585 0x00, 0x05, 0x06, 0x07, 0x0C,
588 static struct npcm_clk_cfg npcm750_sgpio_pdata = {
589 .sft_clk = npcm750_SFT_CLK,
590 .clk_sel = npcm750_CLK_SEL,
591 .cfg_opt = NPCM_750_OPT,
594 static const struct npcm_clk_cfg npcm845_sgpio_pdata = {
595 .sft_clk = npcm845_SFT_CLK,
596 .clk_sel = npcm845_CLK_SEL,
597 .cfg_opt = NPCM_845_OPT,
600 static const struct of_device_id npcm_sgpio_of_table[] = {
601 { .compatible = "nuvoton,npcm750-sgpio", .data = &npcm750_sgpio_pdata, },
602 { .compatible = "nuvoton,npcm845-sgpio", .data = &npcm845_sgpio_pdata, },
605 MODULE_DEVICE_TABLE(of, npcm_sgpio_of_table);
607 static struct platform_driver npcm_sgpio_driver = {
609 .name = KBUILD_MODNAME,
610 .of_match_table = npcm_sgpio_of_table,
612 .probe = npcm_sgpio_probe,
614 module_platform_driver(npcm_sgpio_driver);
616 MODULE_AUTHOR("Jim Liu <jjliu0@nuvoton.com>");
617 MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
618 MODULE_DESCRIPTION("Nuvoton NPCM Serial GPIO Driver");
619 MODULE_LICENSE("GPL v2");