2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio.h>
40 #include <linux/init.h>
42 #include <linux/irq.h>
43 #include <linux/irqchip/chained_irq.h>
44 #include <linux/irqdomain.h>
45 #include <linux/mfd/syscon.h>
46 #include <linux/of_device.h>
47 #include <linux/of_irq.h>
48 #include <linux/pinctrl/consumer.h>
49 #include <linux/platform_device.h>
50 #include <linux/pwm.h>
51 #include <linux/regmap.h>
52 #include <linux/slab.h>
57 * GPIO unit register offsets.
59 #define GPIO_OUT_OFF 0x0000
60 #define GPIO_IO_CONF_OFF 0x0004
61 #define GPIO_BLINK_EN_OFF 0x0008
62 #define GPIO_IN_POL_OFF 0x000c
63 #define GPIO_DATA_IN_OFF 0x0010
64 #define GPIO_EDGE_CAUSE_OFF 0x0014
65 #define GPIO_EDGE_MASK_OFF 0x0018
66 #define GPIO_LEVEL_MASK_OFF 0x001c
67 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
70 * PWM register offsets.
72 #define PWM_BLINK_ON_DURATION_OFF 0x0
73 #define PWM_BLINK_OFF_DURATION_OFF 0x4
76 /* The MV78200 has per-CPU registers for edge mask and level mask */
77 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
78 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
81 * The Armada XP has per-CPU registers for interrupt cause, interrupt
82 * mask and interrupt level mask. Those are relative to the
85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
89 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
90 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
92 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
94 #define MVEBU_MAX_GPIO_PER_BANK 32
97 void __iomem *membase;
98 unsigned long clk_rate;
99 struct gpio_desc *gpiod;
100 struct pwm_chip chip;
102 struct mvebu_gpio_chip *mvchip;
104 /* Used to preserve GPIO/PWM registers across suspend/resume */
106 u32 blink_on_duration;
107 u32 blink_off_duration;
110 struct mvebu_gpio_chip {
111 struct gpio_chip chip;
114 struct regmap *percpu_regs;
116 struct irq_domain *domain;
119 /* Used for PWM support */
121 struct mvebu_pwm *mvpwm;
123 /* Used to preserve GPIO registers across suspend/resume */
128 u32 edge_mask_regs[4];
129 u32 level_mask_regs[4];
133 * Functions returning addresses of individual registers for a given
137 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
138 struct regmap **map, unsigned int *offset)
142 switch (mvchip->soc_variant) {
143 case MVEBU_GPIO_SOC_VARIANT_ORION:
144 case MVEBU_GPIO_SOC_VARIANT_MV78200:
145 case MVEBU_GPIO_SOC_VARIANT_A8K:
147 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
149 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
150 cpu = smp_processor_id();
151 *map = mvchip->percpu_regs;
152 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
160 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
166 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
167 regmap_read(map, offset, &val);
173 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
178 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
179 regmap_write(map, offset, val);
183 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
184 struct regmap **map, unsigned int *offset)
188 switch (mvchip->soc_variant) {
189 case MVEBU_GPIO_SOC_VARIANT_ORION:
190 case MVEBU_GPIO_SOC_VARIANT_A8K:
192 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
194 case MVEBU_GPIO_SOC_VARIANT_MV78200:
195 cpu = smp_processor_id();
197 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
199 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
200 cpu = smp_processor_id();
201 *map = mvchip->percpu_regs;
202 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
210 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
216 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
217 regmap_read(map, offset, &val);
223 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
228 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
229 regmap_write(map, offset, val);
233 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
234 struct regmap **map, unsigned int *offset)
238 switch (mvchip->soc_variant) {
239 case MVEBU_GPIO_SOC_VARIANT_ORION:
240 case MVEBU_GPIO_SOC_VARIANT_A8K:
242 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
244 case MVEBU_GPIO_SOC_VARIANT_MV78200:
245 cpu = smp_processor_id();
247 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
249 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
250 cpu = smp_processor_id();
251 *map = mvchip->percpu_regs;
252 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
260 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
266 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
267 regmap_read(map, offset, &val);
273 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
278 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
279 regmap_write(map, offset, val);
283 * Functions returning addresses of individual registers for a given
286 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
288 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
291 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
293 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
297 * Functions implementing the gpio_chip methods
299 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
301 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
303 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
304 BIT(pin), value ? BIT(pin) : 0);
307 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
309 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
312 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
317 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
319 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
321 u = data_in ^ in_pol;
323 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
326 return (u >> pin) & 1;
329 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
332 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
334 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
335 BIT(pin), value ? BIT(pin) : 0);
338 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
340 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
344 * Check with the pinctrl driver whether this pin is usable as
347 ret = pinctrl_gpio_direction_input(chip->base + pin);
351 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
357 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
360 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
364 * Check with the pinctrl driver whether this pin is usable as
367 ret = pinctrl_gpio_direction_output(chip->base + pin);
371 mvebu_gpio_blink(chip, pin, 0);
372 mvebu_gpio_set(chip, pin, value);
374 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
380 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
382 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
384 return irq_create_mapping(mvchip->domain, pin);
388 * Functions implementing the irq_chip methods
390 static void mvebu_gpio_irq_ack(struct irq_data *d)
392 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
393 struct mvebu_gpio_chip *mvchip = gc->private;
397 mvebu_gpio_write_edge_cause(mvchip, ~mask);
401 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
403 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
404 struct mvebu_gpio_chip *mvchip = gc->private;
405 struct irq_chip_type *ct = irq_data_get_chip_type(d);
409 ct->mask_cache_priv &= ~mask;
410 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
414 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
416 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
417 struct mvebu_gpio_chip *mvchip = gc->private;
418 struct irq_chip_type *ct = irq_data_get_chip_type(d);
422 ct->mask_cache_priv |= mask;
423 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
427 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
429 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
430 struct mvebu_gpio_chip *mvchip = gc->private;
431 struct irq_chip_type *ct = irq_data_get_chip_type(d);
435 ct->mask_cache_priv &= ~mask;
436 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
440 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
443 struct mvebu_gpio_chip *mvchip = gc->private;
444 struct irq_chip_type *ct = irq_data_get_chip_type(d);
448 ct->mask_cache_priv |= mask;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
453 /*****************************************************************************
456 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
457 * value of the line or the opposite value.
459 * Level IRQ handlers: DATA_IN is used directly as cause register.
460 * Interrupt are masked by LEVEL_MASK registers.
461 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
462 * Interrupt are masked by EDGE_MASK registers.
463 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
464 * the polarity to catch the next line transaction.
465 * This is a race condition that might not perfectly
466 * work on some use cases.
468 * Every eight GPIO lines are grouped (OR'ed) before going up to main
472 * data-in /--------| |-----| |----\
473 * -----| |----- ---- to main cause reg
474 * X \----------------| |----/
475 * polarity LEVEL mask
477 ****************************************************************************/
479 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
481 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
482 struct irq_chip_type *ct = irq_data_get_chip_type(d);
483 struct mvebu_gpio_chip *mvchip = gc->private;
489 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
490 if ((u & BIT(pin)) == 0)
493 type &= IRQ_TYPE_SENSE_MASK;
494 if (type == IRQ_TYPE_NONE)
497 /* Check if we need to change chip and handler */
498 if (!(ct->type & type))
499 if (irq_setup_alt_chip(d, type))
503 * Configure interrupt polarity.
506 case IRQ_TYPE_EDGE_RISING:
507 case IRQ_TYPE_LEVEL_HIGH:
508 regmap_update_bits(mvchip->regs,
509 GPIO_IN_POL_OFF + mvchip->offset,
512 case IRQ_TYPE_EDGE_FALLING:
513 case IRQ_TYPE_LEVEL_LOW:
514 regmap_update_bits(mvchip->regs,
515 GPIO_IN_POL_OFF + mvchip->offset,
518 case IRQ_TYPE_EDGE_BOTH: {
519 u32 data_in, in_pol, val;
521 regmap_read(mvchip->regs,
522 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
523 regmap_read(mvchip->regs,
524 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
527 * set initial polarity based on current input level
529 if ((data_in ^ in_pol) & BIT(pin))
530 val = BIT(pin); /* falling */
532 val = 0; /* raising */
534 regmap_update_bits(mvchip->regs,
535 GPIO_IN_POL_OFF + mvchip->offset,
543 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
545 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
546 struct irq_chip *chip = irq_desc_get_chip(desc);
547 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
553 chained_irq_enter(chip, desc);
555 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
556 level_mask = mvebu_gpio_read_level_mask(mvchip);
557 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
558 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
560 cause = (data_in & level_mask) | (edge_cause & edge_mask);
562 for (i = 0; i < mvchip->chip.ngpio; i++) {
565 irq = irq_find_mapping(mvchip->domain, i);
567 if (!(cause & BIT(i)))
570 type = irq_get_trigger_type(irq);
571 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
572 /* Swap polarity (race with GPIO line) */
575 regmap_read(mvchip->regs,
576 GPIO_IN_POL_OFF + mvchip->offset,
579 regmap_write(mvchip->regs,
580 GPIO_IN_POL_OFF + mvchip->offset,
584 generic_handle_irq(irq);
587 chained_irq_exit(chip, desc);
591 * Functions implementing the pwm_chip methods
593 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
595 return container_of(chip, struct mvebu_pwm, chip);
598 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
600 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
601 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
602 struct gpio_desc *desc;
606 spin_lock_irqsave(&mvpwm->lock, flags);
611 desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm);
617 ret = gpiod_request(desc, "mvebu-pwm");
621 ret = gpiod_direction_output(desc, 0);
630 spin_unlock_irqrestore(&mvpwm->lock, flags);
634 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
636 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
639 spin_lock_irqsave(&mvpwm->lock, flags);
640 gpiod_free(mvpwm->gpiod);
642 spin_unlock_irqrestore(&mvpwm->lock, flags);
645 static void mvebu_pwm_get_state(struct pwm_chip *chip,
646 struct pwm_device *pwm,
647 struct pwm_state *state) {
649 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
650 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
651 unsigned long long val;
655 spin_lock_irqsave(&mvpwm->lock, flags);
657 u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
658 val = (unsigned long long) u * NSEC_PER_SEC;
659 do_div(val, mvpwm->clk_rate);
661 state->duty_cycle = UINT_MAX;
663 state->duty_cycle = val;
665 state->duty_cycle = 1;
667 val = (unsigned long long) u; /* on duration */
668 /* period = on + off duration */
669 val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
671 do_div(val, mvpwm->clk_rate);
673 state->period = UINT_MAX;
679 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
681 state->enabled = true;
683 state->enabled = false;
685 spin_unlock_irqrestore(&mvpwm->lock, flags);
688 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
689 struct pwm_state *state)
691 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
692 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
693 unsigned long long val;
695 unsigned int on, off;
697 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
698 do_div(val, NSEC_PER_SEC);
706 val = (unsigned long long) mvpwm->clk_rate *
707 (state->period - state->duty_cycle);
708 do_div(val, NSEC_PER_SEC);
716 spin_lock_irqsave(&mvpwm->lock, flags);
718 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
719 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
721 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
723 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
725 spin_unlock_irqrestore(&mvpwm->lock, flags);
730 static const struct pwm_ops mvebu_pwm_ops = {
731 .request = mvebu_pwm_request,
732 .free = mvebu_pwm_free,
733 .get_state = mvebu_pwm_get_state,
734 .apply = mvebu_pwm_apply,
735 .owner = THIS_MODULE,
738 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
740 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
742 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
743 &mvpwm->blink_select);
744 mvpwm->blink_on_duration =
745 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
746 mvpwm->blink_off_duration =
747 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
750 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
752 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
754 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
755 mvpwm->blink_select);
756 writel_relaxed(mvpwm->blink_on_duration,
757 mvebu_pwmreg_blink_on_duration(mvpwm));
758 writel_relaxed(mvpwm->blink_off_duration,
759 mvebu_pwmreg_blink_off_duration(mvpwm));
762 static int mvebu_pwm_probe(struct platform_device *pdev,
763 struct mvebu_gpio_chip *mvchip,
766 struct device *dev = &pdev->dev;
767 struct mvebu_pwm *mvpwm;
768 struct resource *res;
771 if (!of_device_is_compatible(mvchip->chip.of_node,
772 "marvell,armada-370-gpio"))
776 * There are only two sets of PWM configuration registers for
777 * all the GPIO lines on those SoCs which this driver reserves
778 * for the first two GPIO chips. So if the resource is missing
779 * we can't treat it as an error.
781 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
785 if (IS_ERR(mvchip->clk))
786 return PTR_ERR(mvchip->clk);
789 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
790 * with id 1. Don't allow further GPIO chips to be used for PWM.
798 regmap_write(mvchip->regs,
799 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
801 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
804 mvchip->mvpwm = mvpwm;
805 mvpwm->mvchip = mvchip;
807 mvpwm->membase = devm_ioremap_resource(dev, res);
808 if (IS_ERR(mvpwm->membase))
809 return PTR_ERR(mvpwm->membase);
811 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
812 if (!mvpwm->clk_rate) {
813 dev_err(dev, "failed to get clock rate\n");
817 mvpwm->chip.dev = dev;
818 mvpwm->chip.ops = &mvebu_pwm_ops;
819 mvpwm->chip.npwm = mvchip->chip.ngpio;
821 * There may already be some PWM allocated, so we can't force
822 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
823 * So, we let pwmchip_add() do the numbering and take the next free
826 mvpwm->chip.base = -1;
828 spin_lock_init(&mvpwm->lock);
830 return pwmchip_add(&mvpwm->chip);
833 #ifdef CONFIG_DEBUG_FS
834 #include <linux/seq_file.h>
836 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
838 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
839 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
842 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
843 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
844 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
845 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
846 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
847 cause = mvebu_gpio_read_edge_cause(mvchip);
848 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
849 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
851 for (i = 0; i < chip->ngpio; i++) {
856 label = gpiochip_is_requested(chip, i);
861 is_out = !(io_conf & msk);
863 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
866 seq_printf(s, " out %s %s\n",
867 out & msk ? "hi" : "lo",
868 blink & msk ? "(blink )" : "");
872 seq_printf(s, " in %s (act %s) - IRQ",
873 (data_in ^ in_pol) & msk ? "hi" : "lo",
874 in_pol & msk ? "lo" : "hi");
875 if (!((edg_msk | lvl_msk) & msk)) {
876 seq_puts(s, " disabled\n");
880 seq_puts(s, " edge ");
882 seq_puts(s, " level");
883 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
887 #define mvebu_gpio_dbg_show NULL
890 static const struct of_device_id mvebu_gpio_of_match[] = {
892 .compatible = "marvell,orion-gpio",
893 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
896 .compatible = "marvell,mv78200-gpio",
897 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
900 .compatible = "marvell,armadaxp-gpio",
901 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
904 .compatible = "marvell,armada-370-gpio",
905 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
908 .compatible = "marvell,armada-8k-gpio",
909 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
916 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
918 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
921 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
923 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
924 &mvchip->io_conf_reg);
925 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
926 &mvchip->blink_en_reg);
927 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
928 &mvchip->in_pol_reg);
930 switch (mvchip->soc_variant) {
931 case MVEBU_GPIO_SOC_VARIANT_ORION:
932 case MVEBU_GPIO_SOC_VARIANT_A8K:
933 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
934 &mvchip->edge_mask_regs[0]);
935 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
936 &mvchip->level_mask_regs[0]);
938 case MVEBU_GPIO_SOC_VARIANT_MV78200:
939 for (i = 0; i < 2; i++) {
940 regmap_read(mvchip->regs,
941 GPIO_EDGE_MASK_MV78200_OFF(i),
942 &mvchip->edge_mask_regs[i]);
943 regmap_read(mvchip->regs,
944 GPIO_LEVEL_MASK_MV78200_OFF(i),
945 &mvchip->level_mask_regs[i]);
948 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
949 for (i = 0; i < 4; i++) {
950 regmap_read(mvchip->regs,
951 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
952 &mvchip->edge_mask_regs[i]);
953 regmap_read(mvchip->regs,
954 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
955 &mvchip->level_mask_regs[i]);
962 if (IS_ENABLED(CONFIG_PWM))
963 mvebu_pwm_suspend(mvchip);
968 static int mvebu_gpio_resume(struct platform_device *pdev)
970 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
973 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
975 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
976 mvchip->io_conf_reg);
977 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
978 mvchip->blink_en_reg);
979 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
982 switch (mvchip->soc_variant) {
983 case MVEBU_GPIO_SOC_VARIANT_ORION:
984 case MVEBU_GPIO_SOC_VARIANT_A8K:
985 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
986 mvchip->edge_mask_regs[0]);
987 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
988 mvchip->level_mask_regs[0]);
990 case MVEBU_GPIO_SOC_VARIANT_MV78200:
991 for (i = 0; i < 2; i++) {
992 regmap_write(mvchip->regs,
993 GPIO_EDGE_MASK_MV78200_OFF(i),
994 mvchip->edge_mask_regs[i]);
995 regmap_write(mvchip->regs,
996 GPIO_LEVEL_MASK_MV78200_OFF(i),
997 mvchip->level_mask_regs[i]);
1000 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1001 for (i = 0; i < 4; i++) {
1002 regmap_write(mvchip->regs,
1003 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1004 mvchip->edge_mask_regs[i]);
1005 regmap_write(mvchip->regs,
1006 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1007 mvchip->level_mask_regs[i]);
1014 if (IS_ENABLED(CONFIG_PWM))
1015 mvebu_pwm_resume(mvchip);
1020 static const struct regmap_config mvebu_gpio_regmap_config = {
1027 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1028 struct mvebu_gpio_chip *mvchip)
1030 struct resource *res;
1033 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034 base = devm_ioremap_resource(&pdev->dev, res);
1036 return PTR_ERR(base);
1038 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1039 &mvebu_gpio_regmap_config);
1040 if (IS_ERR(mvchip->regs))
1041 return PTR_ERR(mvchip->regs);
1044 * For the legacy SoCs, the regmap directly maps to the GPIO
1045 * registers, so no offset is needed.
1050 * The Armada XP has a second range of registers for the
1053 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1055 base = devm_ioremap_resource(&pdev->dev, res);
1057 return PTR_ERR(base);
1059 mvchip->percpu_regs =
1060 devm_regmap_init_mmio(&pdev->dev, base,
1061 &mvebu_gpio_regmap_config);
1062 if (IS_ERR(mvchip->percpu_regs))
1063 return PTR_ERR(mvchip->percpu_regs);
1069 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1070 struct mvebu_gpio_chip *mvchip)
1072 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1073 if (IS_ERR(mvchip->regs))
1074 return PTR_ERR(mvchip->regs);
1076 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1082 static int mvebu_gpio_probe(struct platform_device *pdev)
1084 struct mvebu_gpio_chip *mvchip;
1085 const struct of_device_id *match;
1086 struct device_node *np = pdev->dev.of_node;
1087 struct irq_chip_generic *gc;
1088 struct irq_chip_type *ct;
1089 unsigned int ngpios;
1095 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1097 soc_variant = (unsigned long) match->data;
1099 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1101 /* Some gpio controllers do not provide irq support */
1102 have_irqs = of_irq_count(np) != 0;
1104 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1109 platform_set_drvdata(pdev, mvchip);
1111 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1112 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1116 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1118 dev_err(&pdev->dev, "Couldn't get OF id\n");
1122 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1123 /* Not all SoCs require a clock.*/
1124 if (!IS_ERR(mvchip->clk))
1125 clk_prepare_enable(mvchip->clk);
1127 mvchip->soc_variant = soc_variant;
1128 mvchip->chip.label = dev_name(&pdev->dev);
1129 mvchip->chip.parent = &pdev->dev;
1130 mvchip->chip.request = gpiochip_generic_request;
1131 mvchip->chip.free = gpiochip_generic_free;
1132 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1133 mvchip->chip.get = mvebu_gpio_get;
1134 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1135 mvchip->chip.set = mvebu_gpio_set;
1137 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1138 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1139 mvchip->chip.ngpio = ngpios;
1140 mvchip->chip.can_sleep = false;
1141 mvchip->chip.of_node = np;
1142 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1144 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1145 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1147 err = mvebu_gpio_probe_raw(pdev, mvchip);
1153 * Mask and clear GPIO interrupts.
1155 switch (soc_variant) {
1156 case MVEBU_GPIO_SOC_VARIANT_ORION:
1157 case MVEBU_GPIO_SOC_VARIANT_A8K:
1158 regmap_write(mvchip->regs,
1159 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1160 regmap_write(mvchip->regs,
1161 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1162 regmap_write(mvchip->regs,
1163 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1165 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1166 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1167 for (cpu = 0; cpu < 2; cpu++) {
1168 regmap_write(mvchip->regs,
1169 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1170 regmap_write(mvchip->regs,
1171 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1174 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1175 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1176 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1177 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1178 for (cpu = 0; cpu < 4; cpu++) {
1179 regmap_write(mvchip->percpu_regs,
1180 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1181 regmap_write(mvchip->percpu_regs,
1182 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1183 regmap_write(mvchip->percpu_regs,
1184 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1191 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1193 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1194 if (IS_ENABLED(CONFIG_PWM)) {
1195 err = mvebu_pwm_probe(pdev, mvchip, id);
1200 /* Some gpio controllers do not provide irq support */
1205 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1206 if (!mvchip->domain) {
1207 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1208 mvchip->chip.label);
1213 err = irq_alloc_domain_generic_chips(
1214 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1215 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1217 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1218 mvchip->chip.label);
1223 * NOTE: The common accessors cannot be used because of the percpu
1224 * access to the mask registers
1226 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1227 gc->private = mvchip;
1228 ct = &gc->chip_types[0];
1229 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1230 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1231 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1232 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1233 ct->chip.name = mvchip->chip.label;
1235 ct = &gc->chip_types[1];
1236 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1237 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1238 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1239 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1240 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1241 ct->handler = handle_edge_irq;
1242 ct->chip.name = mvchip->chip.label;
1245 * Setup the interrupt handlers. Each chip can have up to 4
1246 * interrupt handlers, with each handler dealing with 8 GPIO
1249 for (i = 0; i < 4; i++) {
1250 int irq = platform_get_irq(pdev, i);
1254 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1261 irq_domain_remove(mvchip->domain);
1263 pwmchip_remove(&mvchip->mvpwm->chip);
1268 static struct platform_driver mvebu_gpio_driver = {
1270 .name = "mvebu-gpio",
1271 .of_match_table = mvebu_gpio_of_match,
1273 .probe = mvebu_gpio_probe,
1274 .suspend = mvebu_gpio_suspend,
1275 .resume = mvebu_gpio_resume,
1277 builtin_platform_driver(mvebu_gpio_driver);