2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
25 #define MPC8XXX_GPIO_PINS 32
33 #define GPIO_ICR2 0x18
35 struct mpc8xxx_gpio_chip {
40 int (*direction_output)(struct gpio_chip *chip,
41 unsigned offset, int value);
43 struct irq_domain *irq;
47 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
48 * defined as output cannot be determined by reading GPDAT register,
49 * so we use shadow data register instead. The status of input pins
50 * is determined by reading GPDAT register.
52 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
55 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
56 u32 out_mask, out_shadow;
58 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
59 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
60 out_shadow = gc->bgpio_data & out_mask;
62 return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
65 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
66 unsigned int gpio, int val)
68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
69 /* GPIO 28..31 are input only on MPC5121 */
73 return mpc8xxx_gc->direction_output(gc, gpio, val);
76 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 0..3 are input only on MPC5125 */
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
87 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
91 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
92 return irq_create_mapping(mpc8xxx_gc->irq, offset);
97 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
99 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
100 struct irq_chip *chip = irq_desc_get_chip(desc);
101 struct gpio_chip *gc = &mpc8xxx_gc->gc;
104 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
105 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
107 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
110 chip->irq_eoi(&desc->irq_data);
113 static void mpc8xxx_irq_unmask(struct irq_data *d)
115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
119 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
121 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
122 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
123 | gc->pin2mask(gc, irqd_to_hwirq(d)));
125 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
128 static void mpc8xxx_irq_mask(struct irq_data *d)
130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
138 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
143 static void mpc8xxx_irq_ack(struct irq_data *d)
145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
149 gc->pin2mask(gc, irqd_to_hwirq(d)));
152 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
155 struct gpio_chip *gc = &mpc8xxx_gc->gc;
159 case IRQ_TYPE_EDGE_FALLING:
160 case IRQ_TYPE_LEVEL_LOW:
161 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
162 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
163 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
164 | gc->pin2mask(gc, irqd_to_hwirq(d)));
165 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
168 case IRQ_TYPE_EDGE_BOTH:
169 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
170 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
171 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
172 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
173 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
183 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
185 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
186 struct gpio_chip *gc = &mpc8xxx_gc->gc;
187 unsigned long gpio = irqd_to_hwirq(d);
193 reg = mpc8xxx_gc->regs + GPIO_ICR;
194 shift = (15 - gpio) * 2;
196 reg = mpc8xxx_gc->regs + GPIO_ICR2;
197 shift = (15 - (gpio % 16)) * 2;
201 case IRQ_TYPE_EDGE_FALLING:
202 case IRQ_TYPE_LEVEL_LOW:
203 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
204 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
206 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
209 case IRQ_TYPE_EDGE_RISING:
210 case IRQ_TYPE_LEVEL_HIGH:
211 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
212 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
214 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
217 case IRQ_TYPE_EDGE_BOTH:
218 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
220 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
230 static struct irq_chip mpc8xxx_irq_chip = {
231 .name = "mpc8xxx-gpio",
232 .irq_unmask = mpc8xxx_irq_unmask,
233 .irq_mask = mpc8xxx_irq_mask,
234 .irq_ack = mpc8xxx_irq_ack,
235 /* this might get overwritten in mpc8xxx_probe() */
236 .irq_set_type = mpc8xxx_irq_set_type,
239 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
240 irq_hw_number_t hwirq)
242 irq_set_chip_data(irq, h->host_data);
243 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
248 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
249 .map = mpc8xxx_gpio_irq_map,
250 .xlate = irq_domain_xlate_twocell,
253 struct mpc8xxx_gpio_devtype {
254 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
255 int (*gpio_get)(struct gpio_chip *, unsigned int);
256 int (*irq_set_type)(struct irq_data *, unsigned int);
259 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
260 .gpio_dir_out = mpc5121_gpio_dir_out,
261 .irq_set_type = mpc512x_irq_set_type,
264 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
265 .gpio_dir_out = mpc5125_gpio_dir_out,
266 .irq_set_type = mpc512x_irq_set_type,
269 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
270 .gpio_get = mpc8572_gpio_get,
273 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
274 .irq_set_type = mpc8xxx_irq_set_type,
277 static const struct of_device_id mpc8xxx_gpio_ids[] = {
278 { .compatible = "fsl,mpc8349-gpio", },
279 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
280 { .compatible = "fsl,mpc8610-gpio", },
281 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
282 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
283 { .compatible = "fsl,pq3-gpio", },
284 { .compatible = "fsl,qoriq-gpio", },
288 static int mpc8xxx_probe(struct platform_device *pdev)
290 struct device_node *np = pdev->dev.of_node;
291 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
292 struct gpio_chip *gc;
293 const struct mpc8xxx_gpio_devtype *devtype =
294 of_device_get_match_data(&pdev->dev);
297 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
301 platform_set_drvdata(pdev, mpc8xxx_gc);
303 raw_spin_lock_init(&mpc8xxx_gc->lock);
305 mpc8xxx_gc->regs = of_iomap(np, 0);
306 if (!mpc8xxx_gc->regs)
309 gc = &mpc8xxx_gc->gc;
310 gc->parent = &pdev->dev;
312 if (of_property_read_bool(np, "little-endian")) {
313 ret = bgpio_init(gc, &pdev->dev, 4,
314 mpc8xxx_gc->regs + GPIO_DAT,
316 mpc8xxx_gc->regs + GPIO_DIR, NULL,
320 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
322 ret = bgpio_init(gc, &pdev->dev, 4,
323 mpc8xxx_gc->regs + GPIO_DAT,
325 mpc8xxx_gc->regs + GPIO_DIR, NULL,
327 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
330 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
333 mpc8xxx_gc->direction_output = gc->direction_output;
336 devtype = &mpc8xxx_gpio_devtype_default;
339 * It's assumed that only a single type of gpio controller is available
340 * on the current machine, so overwriting global data is fine.
342 if (devtype->irq_set_type)
343 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
345 if (devtype->gpio_dir_out)
346 gc->direction_output = devtype->gpio_dir_out;
347 if (devtype->gpio_get)
348 gc->get = devtype->gpio_get;
350 gc->to_irq = mpc8xxx_gpio_to_irq;
352 ret = gpiochip_add_data(gc, mpc8xxx_gc);
354 pr_err("%pOF: GPIO chip registration failed with status %d\n",
359 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
360 if (!mpc8xxx_gc->irqn)
363 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
364 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
365 if (!mpc8xxx_gc->irq)
368 /* ack and mask all irqs */
369 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
370 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
372 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
373 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
376 iounmap(mpc8xxx_gc->regs);
380 static int mpc8xxx_remove(struct platform_device *pdev)
382 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
384 if (mpc8xxx_gc->irq) {
385 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
386 irq_domain_remove(mpc8xxx_gc->irq);
389 gpiochip_remove(&mpc8xxx_gc->gc);
390 iounmap(mpc8xxx_gc->regs);
395 static struct platform_driver mpc8xxx_plat_driver = {
396 .probe = mpc8xxx_probe,
397 .remove = mpc8xxx_remove,
399 .name = "gpio-mpc8xxx",
400 .of_match_table = mpc8xxx_gpio_ids,
404 static int __init mpc8xxx_init(void)
406 return platform_driver_register(&mpc8xxx_plat_driver);
409 arch_initcall(mpc8xxx_init);