2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/module.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/reboot.h>
24 #define GIO_BANK_SIZE 0x20
25 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
26 #define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
27 #define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
28 #define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
29 #define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
30 #define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
31 #define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
32 #define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
34 struct brcmstb_gpio_bank {
35 struct list_head node;
38 struct brcmstb_gpio_priv *parent_priv;
40 struct irq_chip irq_chip;
43 struct brcmstb_gpio_priv {
44 struct list_head bank_list;
45 void __iomem *reg_base;
46 struct platform_device *pdev;
51 struct notifier_block reboot_notifier;
54 #define MAX_GPIO_PER_BANK 32
55 #define GPIO_BANK(gpio) ((gpio) >> 5)
56 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
57 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
59 static inline struct brcmstb_gpio_priv *
60 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
62 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
63 return bank->parent_priv;
67 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
69 void __iomem *reg_base = bank->parent_priv->reg_base;
73 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
74 status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
75 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
76 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
81 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
82 unsigned int offset, bool enable)
84 struct gpio_chip *gc = &bank->gc;
85 struct brcmstb_gpio_priv *priv = bank->parent_priv;
86 u32 mask = gc->pin2mask(gc, offset);
90 spin_lock_irqsave(&gc->bgpio_lock, flags);
91 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
96 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
97 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
100 /* -------------------- IRQ chip functions -------------------- */
102 static void brcmstb_gpio_irq_mask(struct irq_data *d)
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
107 brcmstb_gpio_set_imask(bank, d->hwirq, false);
110 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
112 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
113 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
115 brcmstb_gpio_set_imask(bank, d->hwirq, true);
118 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
121 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
122 struct brcmstb_gpio_priv *priv = bank->parent_priv;
123 u32 mask = BIT(d->hwirq);
124 u32 edge_insensitive, iedge_insensitive;
125 u32 edge_config, iedge_config;
130 case IRQ_TYPE_LEVEL_LOW:
133 edge_insensitive = 0;
135 case IRQ_TYPE_LEVEL_HIGH:
138 edge_insensitive = 0;
140 case IRQ_TYPE_EDGE_FALLING:
143 edge_insensitive = 0;
145 case IRQ_TYPE_EDGE_RISING:
148 edge_insensitive = 0;
150 case IRQ_TYPE_EDGE_BOTH:
152 edge_config = 0; /* don't care, but want known value */
153 edge_insensitive = mask;
159 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
161 iedge_config = bank->gc.read_reg(priv->reg_base +
162 GIO_EC(bank->id)) & ~mask;
163 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
164 GIO_EI(bank->id)) & ~mask;
165 ilevel = bank->gc.read_reg(priv->reg_base +
166 GIO_LEVEL(bank->id)) & ~mask;
168 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
169 iedge_config | edge_config);
170 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
171 iedge_insensitive | edge_insensitive);
172 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
175 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
179 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
185 * Only enable wake IRQ once for however many hwirqs can wake
186 * since they all use the same wake IRQ. Mask will be set
187 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
190 ret = enable_irq_wake(priv->parent_wake_irq);
192 ret = disable_irq_wake(priv->parent_wake_irq);
194 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
195 enable ? "enable" : "disable");
199 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
204 return brcmstb_gpio_priv_set_wake(priv, enable);
207 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
209 struct brcmstb_gpio_priv *priv = data;
211 if (!priv || irq != priv->parent_wake_irq)
213 pm_wakeup_event(&priv->pdev->dev, 0);
217 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
219 struct brcmstb_gpio_priv *priv = bank->parent_priv;
220 struct irq_domain *irq_domain = bank->gc.irqdomain;
221 void __iomem *reg_base = priv->reg_base;
222 unsigned long status;
224 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
227 for_each_set_bit(bit, &status, 32) {
228 u32 stat = bank->gc.read_reg(reg_base +
230 if (bit >= bank->width)
231 dev_warn(&priv->pdev->dev,
232 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
234 bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
236 generic_handle_irq(irq_find_mapping(irq_domain, bit));
241 /* Each UPG GIO block has one IRQ for all banks */
242 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
244 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
245 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
246 struct irq_chip *chip = irq_desc_get_chip(desc);
247 struct brcmstb_gpio_bank *bank;
249 /* Interrupts weren't properly cleared during probe */
250 BUG_ON(!priv || !chip);
252 chained_irq_enter(chip, desc);
253 list_for_each_entry(bank, &priv->bank_list, node)
254 brcmstb_gpio_irq_bank_handler(bank);
255 chained_irq_exit(chip, desc);
258 static int brcmstb_gpio_reboot(struct notifier_block *nb,
259 unsigned long action, void *data)
261 struct brcmstb_gpio_priv *priv =
262 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
264 /* Enable GPIO for S5 cold boot */
265 if (action == SYS_POWER_OFF)
266 brcmstb_gpio_priv_set_wake(priv, 1);
271 /* Make sure that the number of banks matches up between properties */
272 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
273 struct device_node *np, struct resource *res)
275 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
277 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
279 if (res_num_banks != num_banks) {
280 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
281 res_num_banks, num_banks);
288 static int brcmstb_gpio_remove(struct platform_device *pdev)
290 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
291 struct brcmstb_gpio_bank *bank;
295 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
300 * You can lose return values below, but we report all errors, and it's
301 * more important to actually perform all of the steps.
303 list_for_each_entry(bank, &priv->bank_list, node)
304 gpiochip_remove(&bank->gc);
306 if (priv->reboot_notifier.notifier_call) {
307 ret = unregister_reboot_notifier(&priv->reboot_notifier);
310 "failed to unregister reboot notifier\n");
315 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
316 const struct of_phandle_args *gpiospec, u32 *flags)
318 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
319 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
322 if (gc->of_gpio_n_cells != 2) {
327 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
330 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
331 if (offset >= gc->ngpio || offset < 0)
334 if (unlikely(offset >= bank->width)) {
335 dev_warn_ratelimited(&priv->pdev->dev,
336 "Received request for invalid GPIO offset %d\n",
341 *flags = gpiospec->args[1];
346 /* Before calling, must have bank->parent_irq set and gpiochip registered */
347 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
348 struct brcmstb_gpio_bank *bank)
350 struct brcmstb_gpio_priv *priv = bank->parent_priv;
351 struct device *dev = &pdev->dev;
352 struct device_node *np = dev->of_node;
355 bank->irq_chip.name = dev_name(dev);
356 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
357 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
358 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
360 /* Ensures that all non-wakeup IRQs are disabled at suspend */
361 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
363 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
364 of_property_read_bool(np, "wakeup-source")) {
365 priv->parent_wake_irq = platform_get_irq(pdev, 1);
366 if (priv->parent_wake_irq < 0) {
368 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
371 * Set wakeup capability before requesting wakeup
372 * interrupt, so we can process boot-time "wakeups"
373 * (e.g., from S5 cold boot)
375 device_set_wakeup_capable(dev, true);
376 device_wakeup_enable(dev);
377 err = devm_request_irq(dev, priv->parent_wake_irq,
378 brcmstb_gpio_wake_irq_handler, 0,
379 "brcmstb-gpio-wake", priv);
382 dev_err(dev, "Couldn't request wake IRQ");
386 priv->reboot_notifier.notifier_call =
388 register_reboot_notifier(&priv->reboot_notifier);
389 priv->can_wake = true;
394 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
396 err = gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
397 handle_simple_irq, IRQ_TYPE_NONE);
400 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
401 priv->parent_irq, brcmstb_gpio_irq_handler);
406 static int brcmstb_gpio_probe(struct platform_device *pdev)
408 struct device *dev = &pdev->dev;
409 struct device_node *np = dev->of_node;
410 void __iomem *reg_base;
411 struct brcmstb_gpio_priv *priv;
412 struct resource *res;
413 struct property *prop;
418 static int gpio_base;
419 unsigned long flags = 0;
421 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
424 platform_set_drvdata(pdev, priv);
425 INIT_LIST_HEAD(&priv->bank_list);
427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 reg_base = devm_ioremap_resource(dev, res);
429 if (IS_ERR(reg_base))
430 return PTR_ERR(reg_base);
432 priv->gpio_base = gpio_base;
433 priv->reg_base = reg_base;
436 if (of_property_read_bool(np, "interrupt-controller")) {
437 priv->parent_irq = platform_get_irq(pdev, 0);
438 if (priv->parent_irq <= 0) {
439 dev_err(dev, "Couldn't get IRQ");
443 priv->parent_irq = -ENOENT;
446 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
450 * MIPS endianness is configured by boot strap, which also reverses all
451 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
454 * Other architectures (e.g., ARM) either do not support big endian, or
455 * else leave I/O in little endian mode.
457 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
458 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
461 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
463 struct brcmstb_gpio_bank *bank;
464 struct gpio_chip *gc;
466 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
472 bank->parent_priv = priv;
473 bank->id = num_banks;
474 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
475 dev_err(dev, "Invalid bank width %d\n", bank_width);
479 bank->width = bank_width;
483 * Regs are 4 bytes wide, have data reg, no set/clear regs,
484 * and direction bits have 0 = output and 1 = input
487 err = bgpio_init(gc, dev, 4,
488 reg_base + GIO_DATA(bank->id),
490 reg_base + GIO_IODIR(bank->id), flags);
492 dev_err(dev, "bgpio_init() failed\n");
497 gc->owner = THIS_MODULE;
498 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
499 gc->base = gpio_base;
500 gc->of_gpio_n_cells = 2;
501 gc->of_xlate = brcmstb_gpio_of_xlate;
502 /* not all ngpio lines are valid, will use bank width later */
503 gc->ngpio = MAX_GPIO_PER_BANK;
506 * Mask all interrupts by default, since wakeup interrupts may
507 * be retained from S5 cold boot
509 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
511 err = gpiochip_add_data(gc, bank);
513 dev_err(dev, "Could not add gpiochip for bank %d\n",
517 gpio_base += gc->ngpio;
519 if (priv->parent_irq > 0) {
520 err = brcmstb_gpio_irq_setup(pdev, bank);
525 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
526 gc->base, gc->ngpio, bank->width);
528 /* Everything looks good, so add bank to list */
529 list_add(&bank->node, &priv->bank_list);
534 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
535 num_banks, priv->gpio_base, gpio_base - 1);
540 (void) brcmstb_gpio_remove(pdev);
544 static const struct of_device_id brcmstb_gpio_of_match[] = {
545 { .compatible = "brcm,brcmstb-gpio" },
549 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
551 static struct platform_driver brcmstb_gpio_driver = {
553 .name = "brcmstb-gpio",
554 .of_match_table = brcmstb_gpio_of_match,
556 .probe = brcmstb_gpio_probe,
557 .remove = brcmstb_gpio_remove,
559 module_platform_driver(brcmstb_gpio_driver);
561 MODULE_AUTHOR("Gregory Fong");
562 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
563 MODULE_LICENSE("GPL v2");