2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
23 #define ALTERA_GPIO_MAX_NGPIO 32
24 #define ALTERA_GPIO_DATA 0x0
25 #define ALTERA_GPIO_DIR 0x4
26 #define ALTERA_GPIO_IRQ_MASK 0x8
27 #define ALTERA_GPIO_EDGE_CAP 0xc
30 * struct altera_gpio_chip
31 * @mmchip : memory mapped chip structure.
32 * @gpio_lock : synchronization lock so that new irq/set/get requests
33 will be blocked until the current one completes.
34 * @interrupt_trigger : specifies the hardware configured IRQ trigger type
35 (rising, falling, both, high)
36 * @mapped_irq : kernel mapped irq number.
38 struct altera_gpio_chip {
39 struct of_mm_gpio_chip mmchip;
41 int interrupt_trigger;
45 static struct altera_gpio_chip *to_altera(struct gpio_chip *gc)
47 return container_of(gc, struct altera_gpio_chip, mmchip.gc);
50 static void altera_gpio_irq_unmask(struct irq_data *d)
52 struct altera_gpio_chip *altera_gc;
53 struct of_mm_gpio_chip *mm_gc;
57 altera_gc = to_altera(irq_data_get_irq_chip_data(d));
58 mm_gc = &altera_gc->mmchip;
60 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
61 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
62 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
63 intmask |= BIT(irqd_to_hwirq(d));
64 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
65 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
68 static void altera_gpio_irq_mask(struct irq_data *d)
70 struct altera_gpio_chip *altera_gc;
71 struct of_mm_gpio_chip *mm_gc;
75 altera_gc = to_altera(irq_data_get_irq_chip_data(d));
76 mm_gc = &altera_gc->mmchip;
78 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
79 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
80 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
81 intmask &= ~BIT(irqd_to_hwirq(d));
82 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
83 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
87 * This controller's IRQ type is synthesized in hardware, so this function
88 * just checks if the requested set_type matches the synthesized IRQ type
90 static int altera_gpio_irq_set_type(struct irq_data *d,
93 struct altera_gpio_chip *altera_gc;
95 altera_gc = to_altera(irq_data_get_irq_chip_data(d));
97 if (type == IRQ_TYPE_NONE) {
98 irq_set_handler_locked(d, handle_bad_irq);
101 if (type == altera_gc->interrupt_trigger) {
102 if (type == IRQ_TYPE_LEVEL_HIGH)
103 irq_set_handler_locked(d, handle_level_irq);
105 irq_set_handler_locked(d, handle_simple_irq);
108 irq_set_handler_locked(d, handle_bad_irq);
112 static unsigned int altera_gpio_irq_startup(struct irq_data *d)
114 altera_gpio_irq_unmask(d);
119 static struct irq_chip altera_irq_chip = {
120 .name = "altera-gpio",
121 .irq_mask = altera_gpio_irq_mask,
122 .irq_unmask = altera_gpio_irq_unmask,
123 .irq_set_type = altera_gpio_irq_set_type,
124 .irq_startup = altera_gpio_irq_startup,
125 .irq_shutdown = altera_gpio_irq_mask,
128 static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
130 struct of_mm_gpio_chip *mm_gc;
132 mm_gc = to_of_mm_gpio_chip(gc);
134 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
137 static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
139 struct of_mm_gpio_chip *mm_gc;
140 struct altera_gpio_chip *chip;
142 unsigned int data_reg;
144 mm_gc = to_of_mm_gpio_chip(gc);
145 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
147 spin_lock_irqsave(&chip->gpio_lock, flags);
148 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
150 data_reg |= BIT(offset);
152 data_reg &= ~BIT(offset);
153 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
154 spin_unlock_irqrestore(&chip->gpio_lock, flags);
157 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
159 struct of_mm_gpio_chip *mm_gc;
160 struct altera_gpio_chip *chip;
162 unsigned int gpio_ddr;
164 mm_gc = to_of_mm_gpio_chip(gc);
165 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
167 spin_lock_irqsave(&chip->gpio_lock, flags);
168 /* Set pin as input, assumes software controlled IP */
169 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
170 gpio_ddr &= ~BIT(offset);
171 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
172 spin_unlock_irqrestore(&chip->gpio_lock, flags);
177 static int altera_gpio_direction_output(struct gpio_chip *gc,
178 unsigned offset, int value)
180 struct of_mm_gpio_chip *mm_gc;
181 struct altera_gpio_chip *chip;
183 unsigned int data_reg, gpio_ddr;
185 mm_gc = to_of_mm_gpio_chip(gc);
186 chip = container_of(mm_gc, struct altera_gpio_chip, mmchip);
188 spin_lock_irqsave(&chip->gpio_lock, flags);
189 /* Sets the GPIO value */
190 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
192 data_reg |= BIT(offset);
194 data_reg &= ~BIT(offset);
195 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
197 /* Set pin as output, assumes software controlled IP */
198 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
199 gpio_ddr |= BIT(offset);
200 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
201 spin_unlock_irqrestore(&chip->gpio_lock, flags);
206 static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
208 struct altera_gpio_chip *altera_gc;
209 struct irq_chip *chip;
210 struct of_mm_gpio_chip *mm_gc;
211 struct irq_domain *irqdomain;
212 unsigned long status;
215 altera_gc = to_altera(irq_desc_get_handler_data(desc));
216 chip = irq_desc_get_chip(desc);
217 mm_gc = &altera_gc->mmchip;
218 irqdomain = altera_gc->mmchip.gc.irqdomain;
220 chained_irq_enter(chip, desc);
223 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
224 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
225 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
226 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
227 generic_handle_irq(irq_find_mapping(irqdomain, i));
231 chained_irq_exit(chip, desc);
234 static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
236 struct altera_gpio_chip *altera_gc;
237 struct irq_chip *chip;
238 struct of_mm_gpio_chip *mm_gc;
239 struct irq_domain *irqdomain;
240 unsigned long status;
243 altera_gc = to_altera(irq_desc_get_handler_data(desc));
244 chip = irq_desc_get_chip(desc);
245 mm_gc = &altera_gc->mmchip;
246 irqdomain = altera_gc->mmchip.gc.irqdomain;
248 chained_irq_enter(chip, desc);
250 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
251 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
253 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
254 generic_handle_irq(irq_find_mapping(irqdomain, i));
256 chained_irq_exit(chip, desc);
259 static int altera_gpio_probe(struct platform_device *pdev)
261 struct device_node *node = pdev->dev.of_node;
263 struct altera_gpio_chip *altera_gc;
265 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
269 spin_lock_init(&altera_gc->gpio_lock);
271 if (of_property_read_u32(node, "altr,ngpio", ®))
272 /* By default assume maximum ngpio */
273 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
275 altera_gc->mmchip.gc.ngpio = reg;
277 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
279 "ngpio is greater than %d, defaulting to %d\n",
280 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
281 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
284 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
285 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
286 altera_gc->mmchip.gc.get = altera_gpio_get;
287 altera_gc->mmchip.gc.set = altera_gpio_set;
288 altera_gc->mmchip.gc.owner = THIS_MODULE;
289 altera_gc->mmchip.gc.dev = &pdev->dev;
291 ret = of_mm_gpiochip_add(node, &altera_gc->mmchip);
293 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
297 platform_set_drvdata(pdev, altera_gc);
299 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
301 if (altera_gc->mapped_irq < 0)
304 if (of_property_read_u32(node, "altr,interrupt-type", ®)) {
307 "altr,interrupt-type value not set in device tree\n");
310 altera_gc->interrupt_trigger = reg;
312 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
313 handle_bad_irq, IRQ_TYPE_NONE);
316 dev_info(&pdev->dev, "could not add irqchip\n");
320 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
322 altera_gc->mapped_irq,
323 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
324 altera_gpio_irq_leveL_high_handler :
325 altera_gpio_irq_edge_handler);
330 pr_err("%s: registration failed with status %d\n",
331 node->full_name, ret);
336 static int altera_gpio_remove(struct platform_device *pdev)
338 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
340 of_mm_gpiochip_remove(&altera_gc->mmchip);
345 static const struct of_device_id altera_gpio_of_match[] = {
346 { .compatible = "altr,pio-1.0", },
349 MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
351 static struct platform_driver altera_gpio_driver = {
353 .name = "altera_gpio",
354 .of_match_table = of_match_ptr(altera_gpio_of_match),
356 .probe = altera_gpio_probe,
357 .remove = altera_gpio_remove,
360 static int __init altera_gpio_init(void)
362 return platform_driver_register(&altera_gpio_driver);
364 subsys_initcall(altera_gpio_init);
366 static void __exit altera_gpio_exit(void)
368 platform_driver_unregister(&altera_gpio_driver);
370 module_exit(altera_gpio_exit);
372 MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
373 MODULE_DESCRIPTION("Altera GPIO driver");
374 MODULE_LICENSE("GPL");