2 * Copyright (C) 2011-2012 Avionic Design GmbH
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/gpio/driver.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
24 struct i2c_client *client;
25 struct gpio_chip gpio;
26 unsigned int reg_shift;
28 struct mutex i2c_lock;
29 struct mutex irq_lock;
39 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
43 err = i2c_smbus_read_byte_data(adnp->client, offset);
45 dev_err(adnp->gpio.parent, "%s failed: %d\n",
46 "i2c_smbus_read_byte_data()", err);
54 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
58 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
60 dev_err(adnp->gpio.parent, "%s failed: %d\n",
61 "i2c_smbus_write_byte_data()", err);
68 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
70 struct adnp *adnp = gpiochip_get_data(chip);
71 unsigned int reg = offset >> adnp->reg_shift;
72 unsigned int pos = offset & 7;
76 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
80 return (value & BIT(pos)) ? 1 : 0;
83 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
85 unsigned int reg = offset >> adnp->reg_shift;
86 unsigned int pos = offset & 7;
90 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
99 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
102 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
104 struct adnp *adnp = gpiochip_get_data(chip);
106 mutex_lock(&adnp->i2c_lock);
107 __adnp_gpio_set(adnp, offset, value);
108 mutex_unlock(&adnp->i2c_lock);
111 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
113 struct adnp *adnp = gpiochip_get_data(chip);
114 unsigned int reg = offset >> adnp->reg_shift;
115 unsigned int pos = offset & 7;
119 mutex_lock(&adnp->i2c_lock);
121 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
127 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
131 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
135 if (value & BIT(pos)) {
143 mutex_unlock(&adnp->i2c_lock);
147 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
150 struct adnp *adnp = gpiochip_get_data(chip);
151 unsigned int reg = offset >> adnp->reg_shift;
152 unsigned int pos = offset & 7;
156 mutex_lock(&adnp->i2c_lock);
158 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
164 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
168 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
172 if (!(val & BIT(pos))) {
177 __adnp_gpio_set(adnp, offset, value);
181 mutex_unlock(&adnp->i2c_lock);
185 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
187 struct adnp *adnp = gpiochip_get_data(chip);
188 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
191 for (i = 0; i < num_regs; i++) {
192 u8 ddr, plr, ier, isr;
194 mutex_lock(&adnp->i2c_lock);
196 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
198 mutex_unlock(&adnp->i2c_lock);
202 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
204 mutex_unlock(&adnp->i2c_lock);
208 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
210 mutex_unlock(&adnp->i2c_lock);
214 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
216 mutex_unlock(&adnp->i2c_lock);
220 mutex_unlock(&adnp->i2c_lock);
222 for (j = 0; j < 8; j++) {
223 unsigned int bit = (i << adnp->reg_shift) + j;
224 const char *direction = "input ";
225 const char *level = "low ";
226 const char *interrupt = "disabled";
227 const char *pending = "";
230 direction = "output";
236 interrupt = "enabled ";
241 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
242 direction, level, interrupt, pending);
247 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
249 struct gpio_chip *chip = &adnp->gpio;
252 adnp->reg_shift = get_count_order(num_gpios) - 3;
254 chip->direction_input = adnp_gpio_direction_input;
255 chip->direction_output = adnp_gpio_direction_output;
256 chip->get = adnp_gpio_get;
257 chip->set = adnp_gpio_set;
258 chip->can_sleep = true;
260 if (IS_ENABLED(CONFIG_DEBUG_FS))
261 chip->dbg_show = adnp_gpio_dbg_show;
264 chip->ngpio = num_gpios;
265 chip->label = adnp->client->name;
266 chip->parent = &adnp->client->dev;
267 chip->of_node = chip->parent->of_node;
268 chip->owner = THIS_MODULE;
270 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
277 static irqreturn_t adnp_irq(int irq, void *data)
279 struct adnp *adnp = data;
280 unsigned int num_regs, i;
282 num_regs = 1 << adnp->reg_shift;
284 for (i = 0; i < num_regs; i++) {
285 unsigned int base = i << adnp->reg_shift, bit;
286 u8 changed, level, isr, ier;
287 unsigned long pending;
290 mutex_lock(&adnp->i2c_lock);
292 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
294 mutex_unlock(&adnp->i2c_lock);
298 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
300 mutex_unlock(&adnp->i2c_lock);
304 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
306 mutex_unlock(&adnp->i2c_lock);
310 mutex_unlock(&adnp->i2c_lock);
312 /* determine pins that changed levels */
313 changed = level ^ adnp->irq_level[i];
315 /* compute edge-triggered interrupts */
316 pending = changed & ((adnp->irq_fall[i] & ~level) |
317 (adnp->irq_rise[i] & level));
319 /* add in level-triggered interrupts */
320 pending |= (adnp->irq_high[i] & level) |
321 (adnp->irq_low[i] & ~level);
323 /* mask out non-pending and disabled interrupts */
324 pending &= isr & ier;
326 for_each_set_bit(bit, &pending, 8) {
327 unsigned int child_irq;
328 child_irq = irq_find_mapping(adnp->gpio.irqdomain,
330 handle_nested_irq(child_irq);
337 static void adnp_irq_mask(struct irq_data *d)
339 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
340 struct adnp *adnp = gpiochip_get_data(gc);
341 unsigned int reg = d->hwirq >> adnp->reg_shift;
342 unsigned int pos = d->hwirq & 7;
344 adnp->irq_enable[reg] &= ~BIT(pos);
347 static void adnp_irq_unmask(struct irq_data *d)
349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 struct adnp *adnp = gpiochip_get_data(gc);
351 unsigned int reg = d->hwirq >> adnp->reg_shift;
352 unsigned int pos = d->hwirq & 7;
354 adnp->irq_enable[reg] |= BIT(pos);
357 static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
359 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
360 struct adnp *adnp = gpiochip_get_data(gc);
361 unsigned int reg = d->hwirq >> adnp->reg_shift;
362 unsigned int pos = d->hwirq & 7;
364 if (type & IRQ_TYPE_EDGE_RISING)
365 adnp->irq_rise[reg] |= BIT(pos);
367 adnp->irq_rise[reg] &= ~BIT(pos);
369 if (type & IRQ_TYPE_EDGE_FALLING)
370 adnp->irq_fall[reg] |= BIT(pos);
372 adnp->irq_fall[reg] &= ~BIT(pos);
374 if (type & IRQ_TYPE_LEVEL_HIGH)
375 adnp->irq_high[reg] |= BIT(pos);
377 adnp->irq_high[reg] &= ~BIT(pos);
379 if (type & IRQ_TYPE_LEVEL_LOW)
380 adnp->irq_low[reg] |= BIT(pos);
382 adnp->irq_low[reg] &= ~BIT(pos);
387 static void adnp_irq_bus_lock(struct irq_data *d)
389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
390 struct adnp *adnp = gpiochip_get_data(gc);
392 mutex_lock(&adnp->irq_lock);
395 static void adnp_irq_bus_unlock(struct irq_data *d)
397 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
398 struct adnp *adnp = gpiochip_get_data(gc);
399 unsigned int num_regs = 1 << adnp->reg_shift, i;
401 mutex_lock(&adnp->i2c_lock);
403 for (i = 0; i < num_regs; i++)
404 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
406 mutex_unlock(&adnp->i2c_lock);
407 mutex_unlock(&adnp->irq_lock);
410 static struct irq_chip adnp_irq_chip = {
412 .irq_mask = adnp_irq_mask,
413 .irq_unmask = adnp_irq_unmask,
414 .irq_set_type = adnp_irq_set_type,
415 .irq_bus_lock = adnp_irq_bus_lock,
416 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
419 static int adnp_irq_setup(struct adnp *adnp)
421 unsigned int num_regs = 1 << adnp->reg_shift, i;
422 struct gpio_chip *chip = &adnp->gpio;
425 mutex_init(&adnp->irq_lock);
428 * Allocate memory to keep track of the current level and trigger
429 * modes of the interrupts. To avoid multiple allocations, a single
430 * large buffer is allocated and pointers are setup to point at the
431 * corresponding offsets. For consistency, the layout of the buffer
432 * is chosen to match the register layout of the hardware in that
433 * each segment contains the corresponding bits for all interrupts.
435 adnp->irq_enable = devm_kzalloc(chip->parent, num_regs * 6,
437 if (!adnp->irq_enable)
440 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
441 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
442 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
443 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
444 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
446 for (i = 0; i < num_regs; i++) {
448 * Read the initial level of all pins to allow the emulation
449 * of edge triggered interrupts.
451 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
455 /* disable all interrupts */
456 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
460 adnp->irq_enable[i] = 0x00;
463 err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
465 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
466 dev_name(chip->parent), adnp);
468 dev_err(chip->parent, "can't request IRQ#%d: %d\n",
469 adnp->client->irq, err);
473 err = gpiochip_irqchip_add(chip,
479 dev_err(chip->parent,
480 "could not connect irqchip to gpiochip\n");
487 static int adnp_i2c_probe(struct i2c_client *client,
488 const struct i2c_device_id *id)
490 struct device_node *np = client->dev.of_node;
495 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
499 client->irq = irq_of_parse_and_map(np, 0);
501 return -EPROBE_DEFER;
503 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
507 mutex_init(&adnp->i2c_lock);
508 adnp->client = client;
510 err = adnp_gpio_setup(adnp, num_gpios);
514 if (of_find_property(np, "interrupt-controller", NULL)) {
515 err = adnp_irq_setup(adnp);
520 i2c_set_clientdata(client, adnp);
525 static const struct i2c_device_id adnp_i2c_id[] = {
529 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
531 static const struct of_device_id adnp_of_match[] = {
532 { .compatible = "ad,gpio-adnp", },
535 MODULE_DEVICE_TABLE(of, adnp_of_match);
537 static struct i2c_driver adnp_i2c_driver = {
540 .of_match_table = adnp_of_match,
542 .probe = adnp_i2c_probe,
543 .id_table = adnp_i2c_id,
545 module_i2c_driver(adnp_i2c_driver);
547 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
548 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
549 MODULE_LICENSE("GPL");