1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2012 Avionic Design GmbH
6 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/seq_file.h>
12 #include <linux/slab.h>
14 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
15 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
16 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
17 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
18 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
21 struct i2c_client *client;
22 struct gpio_chip gpio;
23 unsigned int reg_shift;
25 struct mutex i2c_lock;
26 struct mutex irq_lock;
36 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
40 err = i2c_smbus_read_byte_data(adnp->client, offset);
42 dev_err(adnp->gpio.parent, "%s failed: %d\n",
43 "i2c_smbus_read_byte_data()", err);
51 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
55 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
57 dev_err(adnp->gpio.parent, "%s failed: %d\n",
58 "i2c_smbus_write_byte_data()", err);
65 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
67 struct adnp *adnp = gpiochip_get_data(chip);
68 unsigned int reg = offset >> adnp->reg_shift;
69 unsigned int pos = offset & 7;
73 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
77 return (value & BIT(pos)) ? 1 : 0;
80 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
82 unsigned int reg = offset >> adnp->reg_shift;
83 unsigned int pos = offset & 7;
87 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
96 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
99 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
101 struct adnp *adnp = gpiochip_get_data(chip);
103 mutex_lock(&adnp->i2c_lock);
104 __adnp_gpio_set(adnp, offset, value);
105 mutex_unlock(&adnp->i2c_lock);
108 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
110 struct adnp *adnp = gpiochip_get_data(chip);
111 unsigned int reg = offset >> adnp->reg_shift;
112 unsigned int pos = offset & 7;
116 mutex_lock(&adnp->i2c_lock);
118 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
124 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
128 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
132 if (value & BIT(pos)) {
140 mutex_unlock(&adnp->i2c_lock);
144 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
147 struct adnp *adnp = gpiochip_get_data(chip);
148 unsigned int reg = offset >> adnp->reg_shift;
149 unsigned int pos = offset & 7;
153 mutex_lock(&adnp->i2c_lock);
155 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
161 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
165 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
169 if (!(val & BIT(pos))) {
174 __adnp_gpio_set(adnp, offset, value);
178 mutex_unlock(&adnp->i2c_lock);
182 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
184 struct adnp *adnp = gpiochip_get_data(chip);
185 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
188 for (i = 0; i < num_regs; i++) {
189 u8 ddr, plr, ier, isr;
191 mutex_lock(&adnp->i2c_lock);
193 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
197 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
201 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
205 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
209 mutex_unlock(&adnp->i2c_lock);
211 for (j = 0; j < 8; j++) {
212 unsigned int bit = (i << adnp->reg_shift) + j;
213 const char *direction = "input ";
214 const char *level = "low ";
215 const char *interrupt = "disabled";
216 const char *pending = "";
219 direction = "output";
225 interrupt = "enabled ";
230 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
231 direction, level, interrupt, pending);
238 mutex_unlock(&adnp->i2c_lock);
241 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
243 struct gpio_chip *chip = &adnp->gpio;
246 adnp->reg_shift = get_count_order(num_gpios) - 3;
248 chip->direction_input = adnp_gpio_direction_input;
249 chip->direction_output = adnp_gpio_direction_output;
250 chip->get = adnp_gpio_get;
251 chip->set = adnp_gpio_set;
252 chip->can_sleep = true;
254 if (IS_ENABLED(CONFIG_DEBUG_FS))
255 chip->dbg_show = adnp_gpio_dbg_show;
258 chip->ngpio = num_gpios;
259 chip->label = adnp->client->name;
260 chip->parent = &adnp->client->dev;
261 chip->of_node = chip->parent->of_node;
262 chip->owner = THIS_MODULE;
264 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
271 static irqreturn_t adnp_irq(int irq, void *data)
273 struct adnp *adnp = data;
274 unsigned int num_regs, i;
276 num_regs = 1 << adnp->reg_shift;
278 for (i = 0; i < num_regs; i++) {
279 unsigned int base = i << adnp->reg_shift, bit;
280 u8 changed, level, isr, ier;
281 unsigned long pending;
284 mutex_lock(&adnp->i2c_lock);
286 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
288 mutex_unlock(&adnp->i2c_lock);
292 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
294 mutex_unlock(&adnp->i2c_lock);
298 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
300 mutex_unlock(&adnp->i2c_lock);
304 mutex_unlock(&adnp->i2c_lock);
306 /* determine pins that changed levels */
307 changed = level ^ adnp->irq_level[i];
309 /* compute edge-triggered interrupts */
310 pending = changed & ((adnp->irq_fall[i] & ~level) |
311 (adnp->irq_rise[i] & level));
313 /* add in level-triggered interrupts */
314 pending |= (adnp->irq_high[i] & level) |
315 (adnp->irq_low[i] & ~level);
317 /* mask out non-pending and disabled interrupts */
318 pending &= isr & ier;
320 for_each_set_bit(bit, &pending, 8) {
321 unsigned int child_irq;
322 child_irq = irq_find_mapping(adnp->gpio.irq.domain,
324 handle_nested_irq(child_irq);
331 static void adnp_irq_mask(struct irq_data *d)
333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
334 struct adnp *adnp = gpiochip_get_data(gc);
335 unsigned int reg = d->hwirq >> adnp->reg_shift;
336 unsigned int pos = d->hwirq & 7;
338 adnp->irq_enable[reg] &= ~BIT(pos);
341 static void adnp_irq_unmask(struct irq_data *d)
343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
344 struct adnp *adnp = gpiochip_get_data(gc);
345 unsigned int reg = d->hwirq >> adnp->reg_shift;
346 unsigned int pos = d->hwirq & 7;
348 adnp->irq_enable[reg] |= BIT(pos);
351 static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
353 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
354 struct adnp *adnp = gpiochip_get_data(gc);
355 unsigned int reg = d->hwirq >> adnp->reg_shift;
356 unsigned int pos = d->hwirq & 7;
358 if (type & IRQ_TYPE_EDGE_RISING)
359 adnp->irq_rise[reg] |= BIT(pos);
361 adnp->irq_rise[reg] &= ~BIT(pos);
363 if (type & IRQ_TYPE_EDGE_FALLING)
364 adnp->irq_fall[reg] |= BIT(pos);
366 adnp->irq_fall[reg] &= ~BIT(pos);
368 if (type & IRQ_TYPE_LEVEL_HIGH)
369 adnp->irq_high[reg] |= BIT(pos);
371 adnp->irq_high[reg] &= ~BIT(pos);
373 if (type & IRQ_TYPE_LEVEL_LOW)
374 adnp->irq_low[reg] |= BIT(pos);
376 adnp->irq_low[reg] &= ~BIT(pos);
381 static void adnp_irq_bus_lock(struct irq_data *d)
383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
384 struct adnp *adnp = gpiochip_get_data(gc);
386 mutex_lock(&adnp->irq_lock);
389 static void adnp_irq_bus_unlock(struct irq_data *d)
391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
392 struct adnp *adnp = gpiochip_get_data(gc);
393 unsigned int num_regs = 1 << adnp->reg_shift, i;
395 mutex_lock(&adnp->i2c_lock);
397 for (i = 0; i < num_regs; i++)
398 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
400 mutex_unlock(&adnp->i2c_lock);
401 mutex_unlock(&adnp->irq_lock);
404 static struct irq_chip adnp_irq_chip = {
406 .irq_mask = adnp_irq_mask,
407 .irq_unmask = adnp_irq_unmask,
408 .irq_set_type = adnp_irq_set_type,
409 .irq_bus_lock = adnp_irq_bus_lock,
410 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
413 static int adnp_irq_setup(struct adnp *adnp)
415 unsigned int num_regs = 1 << adnp->reg_shift, i;
416 struct gpio_chip *chip = &adnp->gpio;
419 mutex_init(&adnp->irq_lock);
422 * Allocate memory to keep track of the current level and trigger
423 * modes of the interrupts. To avoid multiple allocations, a single
424 * large buffer is allocated and pointers are setup to point at the
425 * corresponding offsets. For consistency, the layout of the buffer
426 * is chosen to match the register layout of the hardware in that
427 * each segment contains the corresponding bits for all interrupts.
429 adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
431 if (!adnp->irq_enable)
434 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
435 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
436 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
437 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
438 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
440 for (i = 0; i < num_regs; i++) {
442 * Read the initial level of all pins to allow the emulation
443 * of edge triggered interrupts.
445 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
449 /* disable all interrupts */
450 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
454 adnp->irq_enable[i] = 0x00;
457 err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
459 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
460 dev_name(chip->parent), adnp);
462 dev_err(chip->parent, "can't request IRQ#%d: %d\n",
463 adnp->client->irq, err);
467 err = gpiochip_irqchip_add_nested(chip,
473 dev_err(chip->parent,
474 "could not connect irqchip to gpiochip\n");
478 gpiochip_set_nested_irqchip(chip, &adnp_irq_chip, adnp->client->irq);
483 static int adnp_i2c_probe(struct i2c_client *client,
484 const struct i2c_device_id *id)
486 struct device_node *np = client->dev.of_node;
491 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
495 client->irq = irq_of_parse_and_map(np, 0);
497 return -EPROBE_DEFER;
499 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
503 mutex_init(&adnp->i2c_lock);
504 adnp->client = client;
506 err = adnp_gpio_setup(adnp, num_gpios);
510 if (of_find_property(np, "interrupt-controller", NULL)) {
511 err = adnp_irq_setup(adnp);
516 i2c_set_clientdata(client, adnp);
521 static const struct i2c_device_id adnp_i2c_id[] = {
525 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
527 static const struct of_device_id adnp_of_match[] = {
528 { .compatible = "ad,gpio-adnp", },
531 MODULE_DEVICE_TABLE(of, adnp_of_match);
533 static struct i2c_driver adnp_i2c_driver = {
536 .of_match_table = adnp_of_match,
538 .probe = adnp_i2c_probe,
539 .id_table = adnp_i2c_id,
541 module_i2c_driver(adnp_i2c_driver);
543 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
544 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
545 MODULE_LICENSE("GPL");