1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Accelerated Function Unit (AFU)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
8 * Wu Hao <hao.wu@intel.com>
9 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
10 * Joseph Grecco <joe.grecco@intel.com>
11 * Enno Luebbers <enno.luebbers@intel.com>
12 * Tim Whisonant <tim.whisonant@intel.com>
13 * Ananda Ravuri <ananda.ravuri@intel.com>
14 * Henry Mitchel <henry.mitchel@intel.com>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/uaccess.h>
20 #include <linux/fpga-dfl.h>
25 * port_enable - enable a port
26 * @pdev: port platform device.
28 * Enable Port by clear the port soft reset bit, which is set by default.
29 * The AFU is unable to respond to any MMIO access while in reset.
30 * port_enable function should only be used after port_disable function.
32 static void port_enable(struct platform_device *pdev)
34 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
38 WARN_ON(!pdata->disable_count);
40 if (--pdata->disable_count != 0)
43 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
45 /* Clear port soft reset */
46 v = readq(base + PORT_HDR_CTRL);
47 v &= ~PORT_CTRL_SFTRST;
48 writeq(v, base + PORT_HDR_CTRL);
51 #define RST_POLL_INVL 10 /* us */
52 #define RST_POLL_TIMEOUT 1000 /* us */
55 * port_disable - disable a port
56 * @pdev: port platform device.
58 * Disable Port by setting the port soft reset bit, it puts the port into
61 static int port_disable(struct platform_device *pdev)
63 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
67 if (pdata->disable_count++ != 0)
70 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
72 /* Set port soft reset */
73 v = readq(base + PORT_HDR_CTRL);
74 v |= PORT_CTRL_SFTRST;
75 writeq(v, base + PORT_HDR_CTRL);
78 * HW sets ack bit to 1 when all outstanding requests have been drained
79 * on this port and minimum soft reset pulse width has elapsed.
80 * Driver polls port_soft_reset_ack to determine if reset done by HW.
82 if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
83 v & PORT_CTRL_SFTRST_ACK,
84 RST_POLL_INVL, RST_POLL_TIMEOUT)) {
85 dev_err(&pdev->dev, "timeout, fail to reset device\n");
93 * This function resets the FPGA Port and its accelerator (AFU) by function
94 * __port_disable and __port_enable (set port soft reset bit and then clear
95 * it). Userspace can do Port reset at any time, e.g. during DMA or Partial
96 * Reconfiguration. But it should never cause any system level issue, only
97 * functional failure (e.g. DMA or PR operation failure) and be recoverable
100 * Note: the accelerator (AFU) is not accessible when its port is in reset
101 * (disabled). Any attempts on MMIO access to AFU while in reset, will
102 * result errors reported via port error reporting sub feature (if present).
104 static int __port_reset(struct platform_device *pdev)
108 ret = port_disable(pdev);
115 static int port_reset(struct platform_device *pdev)
117 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
120 mutex_lock(&pdata->lock);
121 ret = __port_reset(pdev);
122 mutex_unlock(&pdata->lock);
127 static int port_get_id(struct platform_device *pdev)
131 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
133 return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP));
137 id_show(struct device *dev, struct device_attribute *attr, char *buf)
139 int id = port_get_id(to_platform_device(dev));
141 return scnprintf(buf, PAGE_SIZE, "%d\n", id);
143 static DEVICE_ATTR_RO(id);
145 static const struct attribute *port_hdr_attrs[] = {
150 static int port_hdr_init(struct platform_device *pdev,
151 struct dfl_feature *feature)
153 dev_dbg(&pdev->dev, "PORT HDR Init.\n");
157 return sysfs_create_files(&pdev->dev.kobj, port_hdr_attrs);
160 static void port_hdr_uinit(struct platform_device *pdev,
161 struct dfl_feature *feature)
163 dev_dbg(&pdev->dev, "PORT HDR UInit.\n");
165 sysfs_remove_files(&pdev->dev.kobj, port_hdr_attrs);
169 port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
170 unsigned int cmd, unsigned long arg)
175 case DFL_FPGA_PORT_RESET:
177 ret = port_reset(pdev);
182 dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
189 static const struct dfl_feature_ops port_hdr_ops = {
190 .init = port_hdr_init,
191 .uinit = port_hdr_uinit,
192 .ioctl = port_hdr_ioctl,
196 afu_id_show(struct device *dev, struct device_attribute *attr, char *buf)
198 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
202 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU);
204 mutex_lock(&pdata->lock);
205 if (pdata->disable_count) {
206 mutex_unlock(&pdata->lock);
210 guidl = readq(base + GUID_L);
211 guidh = readq(base + GUID_H);
212 mutex_unlock(&pdata->lock);
214 return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl);
216 static DEVICE_ATTR_RO(afu_id);
218 static const struct attribute *port_afu_attrs[] = {
219 &dev_attr_afu_id.attr,
223 static int port_afu_init(struct platform_device *pdev,
224 struct dfl_feature *feature)
226 struct resource *res = &pdev->resource[feature->resource_index];
229 dev_dbg(&pdev->dev, "PORT AFU Init.\n");
231 ret = afu_mmio_region_add(dev_get_platdata(&pdev->dev),
232 DFL_PORT_REGION_INDEX_AFU, resource_size(res),
233 res->start, DFL_PORT_REGION_READ |
234 DFL_PORT_REGION_WRITE | DFL_PORT_REGION_MMAP);
238 return sysfs_create_files(&pdev->dev.kobj, port_afu_attrs);
241 static void port_afu_uinit(struct platform_device *pdev,
242 struct dfl_feature *feature)
244 dev_dbg(&pdev->dev, "PORT AFU UInit.\n");
246 sysfs_remove_files(&pdev->dev.kobj, port_afu_attrs);
249 static const struct dfl_feature_ops port_afu_ops = {
250 .init = port_afu_init,
251 .uinit = port_afu_uinit,
254 static struct dfl_feature_driver port_feature_drvs[] = {
256 .id = PORT_FEATURE_ID_HEADER,
257 .ops = &port_hdr_ops,
260 .id = PORT_FEATURE_ID_AFU,
261 .ops = &port_afu_ops,
268 static int afu_open(struct inode *inode, struct file *filp)
270 struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
271 struct dfl_feature_platform_data *pdata;
274 pdata = dev_get_platdata(&fdev->dev);
278 ret = dfl_feature_dev_use_begin(pdata);
282 dev_dbg(&fdev->dev, "Device File Open\n");
283 filp->private_data = fdev;
288 static int afu_release(struct inode *inode, struct file *filp)
290 struct platform_device *pdev = filp->private_data;
291 struct dfl_feature_platform_data *pdata;
293 dev_dbg(&pdev->dev, "Device File Release\n");
295 pdata = dev_get_platdata(&pdev->dev);
297 mutex_lock(&pdata->lock);
299 afu_dma_region_destroy(pdata);
300 mutex_unlock(&pdata->lock);
302 dfl_feature_dev_use_end(pdata);
307 static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
310 /* No extension support for now */
315 afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg)
317 struct dfl_fpga_port_info info;
321 minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs);
323 if (copy_from_user(&info, arg, minsz))
326 if (info.argsz < minsz)
329 mutex_lock(&pdata->lock);
330 afu = dfl_fpga_pdata_get_private(pdata);
332 info.num_regions = afu->num_regions;
333 info.num_umsgs = afu->num_umsgs;
334 mutex_unlock(&pdata->lock);
336 if (copy_to_user(arg, &info, sizeof(info)))
342 static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata,
345 struct dfl_fpga_port_region_info rinfo;
346 struct dfl_afu_mmio_region region;
350 minsz = offsetofend(struct dfl_fpga_port_region_info, offset);
352 if (copy_from_user(&rinfo, arg, minsz))
355 if (rinfo.argsz < minsz || rinfo.padding)
358 ret = afu_mmio_region_get_by_index(pdata, rinfo.index, ®ion);
362 rinfo.flags = region.flags;
363 rinfo.size = region.size;
364 rinfo.offset = region.offset;
366 if (copy_to_user(arg, &rinfo, sizeof(rinfo)))
373 afu_ioctl_dma_map(struct dfl_feature_platform_data *pdata, void __user *arg)
375 struct dfl_fpga_port_dma_map map;
379 minsz = offsetofend(struct dfl_fpga_port_dma_map, iova);
381 if (copy_from_user(&map, arg, minsz))
384 if (map.argsz < minsz || map.flags)
387 ret = afu_dma_map_region(pdata, map.user_addr, map.length, &map.iova);
391 if (copy_to_user(arg, &map, sizeof(map))) {
392 afu_dma_unmap_region(pdata, map.iova);
396 dev_dbg(&pdata->dev->dev, "dma map: ua=%llx, len=%llx, iova=%llx\n",
397 (unsigned long long)map.user_addr,
398 (unsigned long long)map.length,
399 (unsigned long long)map.iova);
405 afu_ioctl_dma_unmap(struct dfl_feature_platform_data *pdata, void __user *arg)
407 struct dfl_fpga_port_dma_unmap unmap;
410 minsz = offsetofend(struct dfl_fpga_port_dma_unmap, iova);
412 if (copy_from_user(&unmap, arg, minsz))
415 if (unmap.argsz < minsz || unmap.flags)
418 return afu_dma_unmap_region(pdata, unmap.iova);
421 static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
423 struct platform_device *pdev = filp->private_data;
424 struct dfl_feature_platform_data *pdata;
425 struct dfl_feature *f;
428 dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
430 pdata = dev_get_platdata(&pdev->dev);
433 case DFL_FPGA_GET_API_VERSION:
434 return DFL_FPGA_API_VERSION;
435 case DFL_FPGA_CHECK_EXTENSION:
436 return afu_ioctl_check_extension(pdata, arg);
437 case DFL_FPGA_PORT_GET_INFO:
438 return afu_ioctl_get_info(pdata, (void __user *)arg);
439 case DFL_FPGA_PORT_GET_REGION_INFO:
440 return afu_ioctl_get_region_info(pdata, (void __user *)arg);
441 case DFL_FPGA_PORT_DMA_MAP:
442 return afu_ioctl_dma_map(pdata, (void __user *)arg);
443 case DFL_FPGA_PORT_DMA_UNMAP:
444 return afu_ioctl_dma_unmap(pdata, (void __user *)arg);
447 * Let sub-feature's ioctl function to handle the cmd
448 * Sub-feature's ioctl returns -ENODEV when cmd is not
449 * handled in this sub feature, and returns 0 and other
450 * error code if cmd is handled.
452 dfl_fpga_dev_for_each_feature(pdata, f)
453 if (f->ops && f->ops->ioctl) {
454 ret = f->ops->ioctl(pdev, f, cmd, arg);
463 static int afu_mmap(struct file *filp, struct vm_area_struct *vma)
465 struct platform_device *pdev = filp->private_data;
466 struct dfl_feature_platform_data *pdata;
467 u64 size = vma->vm_end - vma->vm_start;
468 struct dfl_afu_mmio_region region;
472 if (!(vma->vm_flags & VM_SHARED))
475 pdata = dev_get_platdata(&pdev->dev);
477 offset = vma->vm_pgoff << PAGE_SHIFT;
478 ret = afu_mmio_region_get_by_offset(pdata, offset, size, ®ion);
482 if (!(region.flags & DFL_PORT_REGION_MMAP))
485 if ((vma->vm_flags & VM_READ) && !(region.flags & DFL_PORT_REGION_READ))
488 if ((vma->vm_flags & VM_WRITE) &&
489 !(region.flags & DFL_PORT_REGION_WRITE))
492 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
494 return remap_pfn_range(vma, vma->vm_start,
495 (region.phys + (offset - region.offset)) >> PAGE_SHIFT,
496 size, vma->vm_page_prot);
499 static const struct file_operations afu_fops = {
500 .owner = THIS_MODULE,
502 .release = afu_release,
503 .unlocked_ioctl = afu_ioctl,
507 static int afu_dev_init(struct platform_device *pdev)
509 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
512 afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL);
518 mutex_lock(&pdata->lock);
519 dfl_fpga_pdata_set_private(pdata, afu);
520 afu_mmio_region_init(pdata);
521 afu_dma_region_init(pdata);
522 mutex_unlock(&pdata->lock);
527 static int afu_dev_destroy(struct platform_device *pdev)
529 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
532 mutex_lock(&pdata->lock);
533 afu = dfl_fpga_pdata_get_private(pdata);
534 afu_mmio_region_destroy(pdata);
535 afu_dma_region_destroy(pdata);
536 dfl_fpga_pdata_set_private(pdata, NULL);
537 mutex_unlock(&pdata->lock);
542 static int port_enable_set(struct platform_device *pdev, bool enable)
544 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
547 mutex_lock(&pdata->lock);
551 ret = port_disable(pdev);
552 mutex_unlock(&pdata->lock);
557 static struct dfl_fpga_port_ops afu_port_ops = {
558 .name = DFL_FPGA_FEATURE_DEV_PORT,
559 .owner = THIS_MODULE,
560 .get_id = port_get_id,
561 .enable_set = port_enable_set,
564 static int afu_probe(struct platform_device *pdev)
568 dev_dbg(&pdev->dev, "%s\n", __func__);
570 ret = afu_dev_init(pdev);
574 ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs);
578 ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE);
580 dfl_fpga_dev_feature_uinit(pdev);
587 afu_dev_destroy(pdev);
592 static int afu_remove(struct platform_device *pdev)
594 dev_dbg(&pdev->dev, "%s\n", __func__);
596 dfl_fpga_dev_ops_unregister(pdev);
597 dfl_fpga_dev_feature_uinit(pdev);
598 afu_dev_destroy(pdev);
603 static struct platform_driver afu_driver = {
605 .name = DFL_FPGA_FEATURE_DEV_PORT,
608 .remove = afu_remove,
611 static int __init afu_init(void)
615 dfl_fpga_port_ops_add(&afu_port_ops);
617 ret = platform_driver_register(&afu_driver);
619 dfl_fpga_port_ops_del(&afu_port_ops);
624 static void __exit afu_exit(void)
626 platform_driver_unregister(&afu_driver);
628 dfl_fpga_port_ops_del(&afu_port_ops);
631 module_init(afu_init);
632 module_exit(afu_exit);
634 MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver");
635 MODULE_AUTHOR("Intel Corporation");
636 MODULE_LICENSE("GPL v2");
637 MODULE_ALIAS("platform:dfl-port");