1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
6 * Copyright (C) 2015 Linaro Ltd.
8 #include <linux/platform_device.h>
9 #include <linux/init.h>
10 #include <linux/cpumask.h>
11 #include <linux/export.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/qcom_scm.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/reset-controller.h>
24 static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
25 module_param(download_mode, bool, 0);
27 #define SCM_HAS_CORE_CLK BIT(0)
28 #define SCM_HAS_IFACE_CLK BIT(1)
29 #define SCM_HAS_BUS_CLK BIT(2)
34 struct clk *iface_clk;
36 struct reset_controller_dev reset;
41 struct qcom_scm_current_perm_info {
49 struct qcom_scm_mem_map_info {
54 static struct qcom_scm *__scm;
56 static int qcom_scm_clk_enable(void)
60 ret = clk_prepare_enable(__scm->core_clk);
64 ret = clk_prepare_enable(__scm->iface_clk);
68 ret = clk_prepare_enable(__scm->bus_clk);
75 clk_disable_unprepare(__scm->iface_clk);
77 clk_disable_unprepare(__scm->core_clk);
82 static void qcom_scm_clk_disable(void)
84 clk_disable_unprepare(__scm->core_clk);
85 clk_disable_unprepare(__scm->iface_clk);
86 clk_disable_unprepare(__scm->bus_clk);
90 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
91 * @entry: Entry point function for the cpus
92 * @cpus: The cpumask of cpus that will use the entry point
94 * Set the cold boot address of the cpus. Any cpu outside the supported
95 * range would be removed from the cpu present mask.
97 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
99 return __qcom_scm_set_cold_boot_addr(entry, cpus);
101 EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
104 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
105 * @entry: Entry point function for the cpus
106 * @cpus: The cpumask of cpus that will use the entry point
108 * Set the Linux entry point for the SCM to transfer control to when coming
109 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
111 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
113 return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
115 EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
118 * qcom_scm_cpu_power_down() - Power down the cpu
119 * @flags - Flags to flush cache
121 * This is an end point to power down cpu. If there was a pending interrupt,
122 * the control would return from this function, otherwise, the cpu jumps to the
123 * warm boot entry point set for this cpu upon reset.
125 void qcom_scm_cpu_power_down(u32 flags)
127 __qcom_scm_cpu_power_down(flags);
129 EXPORT_SYMBOL(qcom_scm_cpu_power_down);
132 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
134 * Return true if HDCP is supported, false if not.
136 bool qcom_scm_hdcp_available(void)
138 int ret = qcom_scm_clk_enable();
143 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
146 qcom_scm_clk_disable();
148 return ret > 0 ? true : false;
150 EXPORT_SYMBOL(qcom_scm_hdcp_available);
153 * qcom_scm_hdcp_req() - Send HDCP request.
154 * @req: HDCP request array
155 * @req_cnt: HDCP request array count
156 * @resp: response buffer passed to SCM
158 * Write HDCP register(s) through SCM.
160 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
162 int ret = qcom_scm_clk_enable();
167 ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
168 qcom_scm_clk_disable();
171 EXPORT_SYMBOL(qcom_scm_hdcp_req);
174 * qcom_scm_pas_supported() - Check if the peripheral authentication service is
175 * available for the given peripherial
176 * @peripheral: peripheral id
178 * Returns true if PAS is supported for this peripheral, otherwise false.
180 bool qcom_scm_pas_supported(u32 peripheral)
184 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
185 QCOM_SCM_PAS_IS_SUPPORTED_CMD);
189 return __qcom_scm_pas_supported(__scm->dev, peripheral);
191 EXPORT_SYMBOL(qcom_scm_pas_supported);
194 * qcom_scm_pas_init_image() - Initialize peripheral authentication service
195 * state machine for a given peripheral, using the
197 * @peripheral: peripheral id
198 * @metadata: pointer to memory containing ELF header, program header table
199 * and optional blob of data used for authenticating the metadata
200 * and the rest of the firmware
201 * @size: size of the metadata
203 * Returns 0 on success.
205 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
207 dma_addr_t mdata_phys;
212 * During the scm call memory protection will be enabled for the meta
213 * data blob, so make sure it's physically contiguous, 4K aligned and
214 * non-cachable to avoid XPU violations.
216 mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
219 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
222 memcpy(mdata_buf, metadata, size);
224 ret = qcom_scm_clk_enable();
228 ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys);
230 qcom_scm_clk_disable();
233 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
237 EXPORT_SYMBOL(qcom_scm_pas_init_image);
240 * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
241 * for firmware loading
242 * @peripheral: peripheral id
243 * @addr: start address of memory area to prepare
244 * @size: size of the memory area to prepare
246 * Returns 0 on success.
248 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
252 ret = qcom_scm_clk_enable();
256 ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size);
257 qcom_scm_clk_disable();
261 EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
264 * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
265 * and reset the remote processor
266 * @peripheral: peripheral id
268 * Return 0 on success.
270 int qcom_scm_pas_auth_and_reset(u32 peripheral)
274 ret = qcom_scm_clk_enable();
278 ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral);
279 qcom_scm_clk_disable();
283 EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
286 * qcom_scm_pas_shutdown() - Shut down the remote processor
287 * @peripheral: peripheral id
289 * Returns 0 on success.
291 int qcom_scm_pas_shutdown(u32 peripheral)
295 ret = qcom_scm_clk_enable();
299 ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral);
300 qcom_scm_clk_disable();
304 EXPORT_SYMBOL(qcom_scm_pas_shutdown);
306 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
312 return __qcom_scm_pas_mss_reset(__scm->dev, 1);
315 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
321 return __qcom_scm_pas_mss_reset(__scm->dev, 0);
324 static const struct reset_control_ops qcom_scm_pas_reset_ops = {
325 .assert = qcom_scm_pas_reset_assert,
326 .deassert = qcom_scm_pas_reset_deassert,
329 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
331 return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);
333 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
335 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
337 return __qcom_scm_iommu_secure_ptbl_size(__scm->dev, spare, size);
339 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
341 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
343 return __qcom_scm_iommu_secure_ptbl_init(__scm->dev, addr, size, spare);
345 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
347 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
349 return __qcom_scm_io_readl(__scm->dev, addr, val);
351 EXPORT_SYMBOL(qcom_scm_io_readl);
353 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
355 return __qcom_scm_io_writel(__scm->dev, addr, val);
357 EXPORT_SYMBOL(qcom_scm_io_writel);
359 static void qcom_scm_set_download_mode(bool enable)
364 avail = __qcom_scm_is_call_available(__scm->dev,
366 QCOM_SCM_SET_DLOAD_MODE);
368 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
369 } else if (__scm->dload_mode_addr) {
370 ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
371 enable ? QCOM_SCM_SET_DLOAD_MODE : 0);
374 "No available mechanism for setting download mode\n");
378 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
381 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
383 struct device_node *tcsr;
384 struct device_node *np = dev->of_node;
389 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
393 ret = of_address_to_resource(tcsr, 0, &res);
398 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
402 *addr = res.start + offset;
408 * qcom_scm_is_available() - Checks if SCM is available
410 bool qcom_scm_is_available(void)
414 EXPORT_SYMBOL(qcom_scm_is_available);
416 int qcom_scm_set_remote_state(u32 state, u32 id)
418 return __qcom_scm_set_remote_state(__scm->dev, state, id);
420 EXPORT_SYMBOL(qcom_scm_set_remote_state);
423 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
424 * @mem_addr: mem region whose ownership need to be reassigned
425 * @mem_sz: size of the region.
426 * @srcvm: vmid for current set of owners, each set bit in
427 * flag indicate a unique owner
428 * @newvm: array having new owners and corresponding permission
430 * @dest_cnt: number of owners in next set.
432 * Return negative errno on failure or 0 on success with @srcvm updated.
434 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
436 const struct qcom_scm_vmperm *newvm,
437 unsigned int dest_cnt)
439 struct qcom_scm_current_perm_info *destvm;
440 struct qcom_scm_mem_map_info *mem_to_map;
441 phys_addr_t mem_to_map_phys;
442 phys_addr_t dest_phys;
444 size_t mem_to_map_sz;
452 unsigned long srcvm_bits = *srcvm;
454 src_sz = hweight_long(srcvm_bits) * sizeof(*src);
455 mem_to_map_sz = sizeof(*mem_to_map);
456 dest_sz = dest_cnt * sizeof(*destvm);
457 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
458 ALIGN(dest_sz, SZ_64);
460 ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
464 /* Fill source vmid detail */
467 for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
468 src[i++] = cpu_to_le32(b);
470 /* Fill details of mem buff to map */
471 mem_to_map = ptr + ALIGN(src_sz, SZ_64);
472 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
473 mem_to_map->mem_addr = cpu_to_le64(mem_addr);
474 mem_to_map->mem_size = cpu_to_le64(mem_sz);
477 /* Fill details of next vmid detail */
478 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
479 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
480 for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
481 destvm->vmid = cpu_to_le32(newvm->vmid);
482 destvm->perm = cpu_to_le32(newvm->perm);
484 destvm->ctx_size = 0;
485 next_vm |= BIT(newvm->vmid);
488 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
489 ptr_phys, src_sz, dest_phys, dest_sz);
490 dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
493 "Assign memory protection call failed %d\n", ret);
500 EXPORT_SYMBOL(qcom_scm_assign_mem);
502 static int qcom_scm_probe(struct platform_device *pdev)
504 struct qcom_scm *scm;
508 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
512 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
516 clks = (unsigned long)of_device_get_match_data(&pdev->dev);
518 scm->core_clk = devm_clk_get(&pdev->dev, "core");
519 if (IS_ERR(scm->core_clk)) {
520 if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
521 return PTR_ERR(scm->core_clk);
523 if (clks & SCM_HAS_CORE_CLK) {
524 dev_err(&pdev->dev, "failed to acquire core clk\n");
525 return PTR_ERR(scm->core_clk);
528 scm->core_clk = NULL;
531 scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
532 if (IS_ERR(scm->iface_clk)) {
533 if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
534 return PTR_ERR(scm->iface_clk);
536 if (clks & SCM_HAS_IFACE_CLK) {
537 dev_err(&pdev->dev, "failed to acquire iface clk\n");
538 return PTR_ERR(scm->iface_clk);
541 scm->iface_clk = NULL;
544 scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
545 if (IS_ERR(scm->bus_clk)) {
546 if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
547 return PTR_ERR(scm->bus_clk);
549 if (clks & SCM_HAS_BUS_CLK) {
550 dev_err(&pdev->dev, "failed to acquire bus clk\n");
551 return PTR_ERR(scm->bus_clk);
557 scm->reset.ops = &qcom_scm_pas_reset_ops;
558 scm->reset.nr_resets = 1;
559 scm->reset.of_node = pdev->dev.of_node;
560 ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
564 /* vote for max clk rate for highest performance */
565 ret = clk_set_rate(scm->core_clk, INT_MAX);
570 __scm->dev = &pdev->dev;
575 * If requested enable "download mode", from this point on warmboot
576 * will cause the the boot stages to enter download mode, unless
577 * disabled below by a clean shutdown/reboot.
580 qcom_scm_set_download_mode(true);
585 static void qcom_scm_shutdown(struct platform_device *pdev)
587 /* Clean shutdown, disable download mode to allow normal restart */
589 qcom_scm_set_download_mode(false);
592 static const struct of_device_id qcom_scm_dt_match[] = {
593 { .compatible = "qcom,scm-apq8064",
594 /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
596 { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
600 { .compatible = "qcom,scm-ipq4019" },
601 { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
602 { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
603 { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
607 { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
611 { .compatible = "qcom,scm-msm8996" },
612 { .compatible = "qcom,scm" },
616 static struct platform_driver qcom_scm_driver = {
619 .of_match_table = qcom_scm_dt_match,
621 .probe = qcom_scm_probe,
622 .shutdown = qcom_scm_shutdown,
625 static int __init qcom_scm_init(void)
627 return platform_driver_register(&qcom_scm_driver);
629 subsys_initcall(qcom_scm_init);