1 // SPDX-License-Identifier: GPL-2.0
3 * System Control and Management Interface (SCMI) Clock Protocol
5 * Copyright (C) 2018-2022 ARM Ltd.
8 #include <linux/module.h>
9 #include <linux/limits.h>
10 #include <linux/sort.h>
12 #include "protocols.h"
15 enum scmi_clock_protocol_cmd {
16 CLOCK_ATTRIBUTES = 0x3,
17 CLOCK_DESCRIBE_RATES = 0x4,
20 CLOCK_CONFIG_SET = 0x7,
22 CLOCK_RATE_NOTIFY = 0x9,
23 CLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 0xA,
24 CLOCK_CONFIG_GET = 0xB,
25 CLOCK_POSSIBLE_PARENTS_GET = 0xC,
26 CLOCK_PARENT_SET = 0xD,
27 CLOCK_PARENT_GET = 0xE,
37 struct scmi_msg_resp_clock_protocol_attributes {
43 struct scmi_msg_resp_clock_attributes {
45 #define SUPPORTS_RATE_CHANGED_NOTIF(x) ((x) & BIT(31))
46 #define SUPPORTS_RATE_CHANGE_REQUESTED_NOTIF(x) ((x) & BIT(30))
47 #define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(29))
48 #define SUPPORTS_PARENT_CLOCK(x) ((x) & BIT(28))
49 u8 name[SCMI_SHORT_NAME_MAX_SIZE];
50 __le32 clock_enable_latency;
53 struct scmi_msg_clock_possible_parents {
58 struct scmi_msg_resp_clock_possible_parents {
59 __le32 num_parent_flags;
60 #define NUM_PARENTS_RETURNED(x) ((x) & 0xff)
61 #define NUM_PARENTS_REMAINING(x) ((x) >> 24)
62 __le32 possible_parents[];
65 struct scmi_msg_clock_set_parent {
70 struct scmi_msg_clock_config_set {
75 /* Valid only from SCMI clock v2.1 */
76 struct scmi_msg_clock_config_set_v2 {
79 #define NULL_OEM_TYPE 0
80 #define REGMASK_OEM_TYPE_SET GENMASK(23, 16)
81 #define REGMASK_CLK_STATE GENMASK(1, 0)
82 __le32 oem_config_val;
85 struct scmi_msg_clock_config_get {
88 #define REGMASK_OEM_TYPE_GET GENMASK(7, 0)
91 struct scmi_msg_resp_clock_config_get {
94 #define IS_CLK_ENABLED(x) le32_get_bits((x), BIT(0))
95 __le32 oem_config_val;
98 struct scmi_msg_clock_describe_rates {
103 struct scmi_msg_resp_clock_describe_rates {
104 __le32 num_rates_flags;
105 #define NUM_RETURNED(x) ((x) & 0xfff)
106 #define RATE_DISCRETE(x) !((x) & BIT(12))
107 #define NUM_REMAINING(x) ((x) >> 16)
112 #define RATE_TO_U64(X) \
115 le32_to_cpu((x).value_low) | (u64)le32_to_cpu((x).value_high) << 32; \
119 struct scmi_clock_set_rate {
121 #define CLOCK_SET_ASYNC BIT(0)
122 #define CLOCK_SET_IGNORE_RESP BIT(1)
123 #define CLOCK_SET_ROUND_UP BIT(2)
124 #define CLOCK_SET_ROUND_AUTO BIT(3)
130 struct scmi_msg_resp_set_rate_complete {
136 struct scmi_msg_clock_rate_notify {
138 __le32 notify_enable;
141 struct scmi_clock_rate_notify_payld {
152 atomic_t cur_async_req;
153 struct scmi_clock_info *clk;
154 int (*clock_config_set)(const struct scmi_protocol_handle *ph,
155 u32 clk_id, enum clk_state state,
156 u8 oem_type, u32 oem_val, bool atomic);
157 int (*clock_config_get)(const struct scmi_protocol_handle *ph,
158 u32 clk_id, u8 oem_type, u32 *attributes,
159 bool *enabled, u32 *oem_val, bool atomic);
162 static enum scmi_clock_protocol_cmd evt_2_cmd[] = {
164 CLOCK_RATE_CHANGE_REQUESTED_NOTIFY,
168 scmi_clock_protocol_attributes_get(const struct scmi_protocol_handle *ph,
169 struct clock_info *ci)
173 struct scmi_msg_resp_clock_protocol_attributes *attr;
175 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES,
176 0, sizeof(*attr), &t);
182 ret = ph->xops->do_xfer(ph, t);
184 ci->num_clocks = le16_to_cpu(attr->num_clocks);
185 ci->max_async_req = attr->max_async_req;
188 ph->xops->xfer_put(ph, t);
192 struct scmi_clk_ipriv {
195 struct scmi_clock_info *clk;
198 static void iter_clk_possible_parents_prepare_message(void *message, unsigned int desc_index,
201 struct scmi_msg_clock_possible_parents *msg = message;
202 const struct scmi_clk_ipriv *p = priv;
204 msg->id = cpu_to_le32(p->clk_id);
205 /* Set the number of OPPs to be skipped/already read */
206 msg->skip_parents = cpu_to_le32(desc_index);
209 static int iter_clk_possible_parents_update_state(struct scmi_iterator_state *st,
210 const void *response, void *priv)
212 const struct scmi_msg_resp_clock_possible_parents *r = response;
213 struct scmi_clk_ipriv *p = priv;
214 struct device *dev = ((struct scmi_clk_ipriv *)p)->dev;
217 flags = le32_to_cpu(r->num_parent_flags);
218 st->num_returned = NUM_PARENTS_RETURNED(flags);
219 st->num_remaining = NUM_PARENTS_REMAINING(flags);
222 * num parents is not declared previously anywhere so we
223 * assume it's returned+remaining on first call.
225 if (!st->max_resources) {
226 p->clk->num_parents = st->num_returned + st->num_remaining;
227 p->clk->parents = devm_kcalloc(dev, p->clk->num_parents,
228 sizeof(*p->clk->parents),
230 if (!p->clk->parents) {
231 p->clk->num_parents = 0;
234 st->max_resources = st->num_returned + st->num_remaining;
240 static int iter_clk_possible_parents_process_response(const struct scmi_protocol_handle *ph,
241 const void *response,
242 struct scmi_iterator_state *st,
245 const struct scmi_msg_resp_clock_possible_parents *r = response;
246 struct scmi_clk_ipriv *p = priv;
248 u32 *parent = &p->clk->parents[st->desc_index + st->loop_idx];
250 *parent = le32_to_cpu(r->possible_parents[st->loop_idx]);
255 static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph, u32 clk_id,
256 struct scmi_clock_info *clk)
258 struct scmi_iterator_ops ops = {
259 .prepare_message = iter_clk_possible_parents_prepare_message,
260 .update_state = iter_clk_possible_parents_update_state,
261 .process_response = iter_clk_possible_parents_process_response,
264 struct scmi_clk_ipriv ppriv = {
272 iter = ph->hops->iter_response_init(ph, &ops, 0,
273 CLOCK_POSSIBLE_PARENTS_GET,
274 sizeof(struct scmi_msg_clock_possible_parents),
277 return PTR_ERR(iter);
279 ret = ph->hops->iter_response_run(iter);
284 static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
285 u32 clk_id, struct scmi_clock_info *clk,
291 struct scmi_msg_resp_clock_attributes *attr;
293 ret = ph->xops->xfer_get_init(ph, CLOCK_ATTRIBUTES,
294 sizeof(clk_id), sizeof(*attr), &t);
298 put_unaligned_le32(clk_id, t->tx.buf);
301 ret = ph->xops->do_xfer(ph, t);
304 attributes = le32_to_cpu(attr->attributes);
305 strscpy(clk->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
306 /* clock_enable_latency field is present only since SCMI v3.1 */
307 if (PROTOCOL_REV_MAJOR(version) >= 0x2)
308 latency = le32_to_cpu(attr->clock_enable_latency);
309 clk->enable_latency = latency ? : U32_MAX;
312 ph->xops->xfer_put(ph, t);
315 * If supported overwrite short name with the extended one;
316 * on error just carry on and use already provided short name.
318 if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x2) {
319 if (SUPPORTS_EXTENDED_NAMES(attributes))
320 ph->hops->extended_name_get(ph, CLOCK_NAME_GET, clk_id,
324 if (SUPPORTS_RATE_CHANGED_NOTIF(attributes))
325 clk->rate_changed_notifications = true;
326 if (SUPPORTS_RATE_CHANGE_REQUESTED_NOTIF(attributes))
327 clk->rate_change_requested_notifications = true;
328 if (SUPPORTS_PARENT_CLOCK(attributes))
329 scmi_clock_possible_parents(ph, clk_id, clk);
335 static int rate_cmp_func(const void *_r1, const void *_r2)
337 const u64 *r1 = _r1, *r2 = _r2;
347 static void iter_clk_describe_prepare_message(void *message,
348 const unsigned int desc_index,
351 struct scmi_msg_clock_describe_rates *msg = message;
352 const struct scmi_clk_ipriv *p = priv;
354 msg->id = cpu_to_le32(p->clk_id);
355 /* Set the number of rates to be skipped/already read */
356 msg->rate_index = cpu_to_le32(desc_index);
360 iter_clk_describe_update_state(struct scmi_iterator_state *st,
361 const void *response, void *priv)
364 struct scmi_clk_ipriv *p = priv;
365 const struct scmi_msg_resp_clock_describe_rates *r = response;
367 flags = le32_to_cpu(r->num_rates_flags);
368 st->num_remaining = NUM_REMAINING(flags);
369 st->num_returned = NUM_RETURNED(flags);
370 p->clk->rate_discrete = RATE_DISCRETE(flags);
372 /* Warn about out of spec replies ... */
373 if (!p->clk->rate_discrete &&
374 (st->num_returned != 3 || st->num_remaining != 0)) {
376 "Out-of-spec CLOCK_DESCRIBE_RATES reply for %s - returned:%d remaining:%d rx_len:%zd\n",
377 p->clk->name, st->num_returned, st->num_remaining,
381 * A known quirk: a triplet is returned but num_returned != 3
382 * Check for a safe payload size and fix.
384 if (st->num_returned != 3 && st->num_remaining == 0 &&
385 st->rx_len == sizeof(*r) + sizeof(__le32) * 2 * 3) {
386 st->num_returned = 3;
387 st->num_remaining = 0;
390 "Cannot fix out-of-spec reply !\n");
399 iter_clk_describe_process_response(const struct scmi_protocol_handle *ph,
400 const void *response,
401 struct scmi_iterator_state *st, void *priv)
404 struct scmi_clk_ipriv *p = priv;
405 const struct scmi_msg_resp_clock_describe_rates *r = response;
407 if (!p->clk->rate_discrete) {
408 switch (st->desc_index + st->loop_idx) {
410 p->clk->range.min_rate = RATE_TO_U64(r->rate[0]);
413 p->clk->range.max_rate = RATE_TO_U64(r->rate[1]);
416 p->clk->range.step_size = RATE_TO_U64(r->rate[2]);
423 u64 *rate = &p->clk->list.rates[st->desc_index + st->loop_idx];
425 *rate = RATE_TO_U64(r->rate[st->loop_idx]);
426 p->clk->list.num_rates++;
433 scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
434 struct scmi_clock_info *clk)
438 struct scmi_iterator_ops ops = {
439 .prepare_message = iter_clk_describe_prepare_message,
440 .update_state = iter_clk_describe_update_state,
441 .process_response = iter_clk_describe_process_response,
443 struct scmi_clk_ipriv cpriv = {
449 iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,
450 CLOCK_DESCRIBE_RATES,
451 sizeof(struct scmi_msg_clock_describe_rates),
454 return PTR_ERR(iter);
456 ret = ph->hops->iter_response_run(iter);
460 if (!clk->rate_discrete) {
461 dev_dbg(ph->dev, "Min %llu Max %llu Step %llu Hz\n",
462 clk->range.min_rate, clk->range.max_rate,
463 clk->range.step_size);
464 } else if (clk->list.num_rates) {
465 sort(clk->list.rates, clk->list.num_rates,
466 sizeof(clk->list.rates[0]), rate_cmp_func, NULL);
473 scmi_clock_rate_get(const struct scmi_protocol_handle *ph,
474 u32 clk_id, u64 *value)
479 ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_GET,
480 sizeof(__le32), sizeof(u64), &t);
484 put_unaligned_le32(clk_id, t->tx.buf);
486 ret = ph->xops->do_xfer(ph, t);
488 *value = get_unaligned_le64(t->rx.buf);
490 ph->xops->xfer_put(ph, t);
494 static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph,
495 u32 clk_id, u64 rate)
500 struct scmi_clock_set_rate *cfg;
501 struct clock_info *ci = ph->get_priv(ph);
503 ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_SET, sizeof(*cfg), 0, &t);
507 if (ci->max_async_req &&
508 atomic_inc_return(&ci->cur_async_req) < ci->max_async_req)
509 flags |= CLOCK_SET_ASYNC;
512 cfg->flags = cpu_to_le32(flags);
513 cfg->id = cpu_to_le32(clk_id);
514 cfg->value_low = cpu_to_le32(rate & 0xffffffff);
515 cfg->value_high = cpu_to_le32(rate >> 32);
517 if (flags & CLOCK_SET_ASYNC) {
518 ret = ph->xops->do_xfer_with_response(ph, t);
520 struct scmi_msg_resp_set_rate_complete *resp;
523 if (le32_to_cpu(resp->id) == clk_id)
525 "Clk ID %d set async to %llu\n", clk_id,
526 get_unaligned_le64(&resp->rate_low));
531 ret = ph->xops->do_xfer(ph, t);
534 if (ci->max_async_req)
535 atomic_dec(&ci->cur_async_req);
537 ph->xops->xfer_put(ph, t);
542 scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id,
543 enum clk_state state, u8 __unused0, u32 __unused1,
548 struct scmi_msg_clock_config_set *cfg;
550 if (state >= CLK_STATE_RESERVED)
553 ret = ph->xops->xfer_get_init(ph, CLOCK_CONFIG_SET,
554 sizeof(*cfg), 0, &t);
558 t->hdr.poll_completion = atomic;
561 cfg->id = cpu_to_le32(clk_id);
562 cfg->attributes = cpu_to_le32(state);
564 ret = ph->xops->do_xfer(ph, t);
566 ph->xops->xfer_put(ph, t);
571 scmi_clock_set_parent(const struct scmi_protocol_handle *ph, u32 clk_id,
576 struct scmi_msg_clock_set_parent *cfg;
577 struct clock_info *ci = ph->get_priv(ph);
578 struct scmi_clock_info *clk;
580 if (clk_id >= ci->num_clocks)
583 clk = ci->clk + clk_id;
585 if (parent_id >= clk->num_parents)
588 ret = ph->xops->xfer_get_init(ph, CLOCK_PARENT_SET,
589 sizeof(*cfg), 0, &t);
593 t->hdr.poll_completion = false;
596 cfg->id = cpu_to_le32(clk_id);
597 cfg->parent_id = cpu_to_le32(clk->parents[parent_id]);
599 ret = ph->xops->do_xfer(ph, t);
601 ph->xops->xfer_put(ph, t);
607 scmi_clock_get_parent(const struct scmi_protocol_handle *ph, u32 clk_id,
613 ret = ph->xops->xfer_get_init(ph, CLOCK_PARENT_GET,
614 sizeof(__le32), sizeof(u32), &t);
618 put_unaligned_le32(clk_id, t->tx.buf);
620 ret = ph->xops->do_xfer(ph, t);
622 *parent_id = get_unaligned_le32(t->rx.buf);
624 ph->xops->xfer_put(ph, t);
628 /* For SCMI clock v2.1 and onwards */
630 scmi_clock_config_set_v2(const struct scmi_protocol_handle *ph, u32 clk_id,
631 enum clk_state state, u8 oem_type, u32 oem_val,
637 struct scmi_msg_clock_config_set_v2 *cfg;
639 if (state == CLK_STATE_RESERVED ||
640 (!oem_type && state == CLK_STATE_UNCHANGED))
643 ret = ph->xops->xfer_get_init(ph, CLOCK_CONFIG_SET,
644 sizeof(*cfg), 0, &t);
648 t->hdr.poll_completion = atomic;
650 attrs = FIELD_PREP(REGMASK_OEM_TYPE_SET, oem_type) |
651 FIELD_PREP(REGMASK_CLK_STATE, state);
654 cfg->id = cpu_to_le32(clk_id);
655 cfg->attributes = cpu_to_le32(attrs);
656 /* Clear in any case */
657 cfg->oem_config_val = cpu_to_le32(0);
659 cfg->oem_config_val = cpu_to_le32(oem_val);
661 ret = ph->xops->do_xfer(ph, t);
663 ph->xops->xfer_put(ph, t);
667 static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 clk_id,
670 struct clock_info *ci = ph->get_priv(ph);
672 return ci->clock_config_set(ph, clk_id, CLK_STATE_ENABLE,
673 NULL_OEM_TYPE, 0, atomic);
676 static int scmi_clock_disable(const struct scmi_protocol_handle *ph, u32 clk_id,
679 struct clock_info *ci = ph->get_priv(ph);
681 return ci->clock_config_set(ph, clk_id, CLK_STATE_DISABLE,
682 NULL_OEM_TYPE, 0, atomic);
685 /* For SCMI clock v2.1 and onwards */
687 scmi_clock_config_get_v2(const struct scmi_protocol_handle *ph, u32 clk_id,
688 u8 oem_type, u32 *attributes, bool *enabled,
689 u32 *oem_val, bool atomic)
694 struct scmi_msg_clock_config_get *cfg;
696 ret = ph->xops->xfer_get_init(ph, CLOCK_CONFIG_GET,
697 sizeof(*cfg), 0, &t);
701 t->hdr.poll_completion = atomic;
703 flags = FIELD_PREP(REGMASK_OEM_TYPE_GET, oem_type);
706 cfg->id = cpu_to_le32(clk_id);
707 cfg->flags = cpu_to_le32(flags);
709 ret = ph->xops->do_xfer(ph, t);
711 struct scmi_msg_resp_clock_config_get *resp = t->rx.buf;
714 *attributes = le32_to_cpu(resp->attributes);
717 *enabled = IS_CLK_ENABLED(resp->config);
719 if (oem_val && oem_type)
720 *oem_val = le32_to_cpu(resp->oem_config_val);
723 ph->xops->xfer_put(ph, t);
729 scmi_clock_config_get(const struct scmi_protocol_handle *ph, u32 clk_id,
730 u8 oem_type, u32 *attributes, bool *enabled,
731 u32 *oem_val, bool atomic)
735 struct scmi_msg_resp_clock_attributes *resp;
740 ret = ph->xops->xfer_get_init(ph, CLOCK_ATTRIBUTES,
741 sizeof(clk_id), sizeof(*resp), &t);
745 t->hdr.poll_completion = atomic;
746 put_unaligned_le32(clk_id, t->tx.buf);
749 ret = ph->xops->do_xfer(ph, t);
751 *enabled = IS_CLK_ENABLED(resp->attributes);
753 ph->xops->xfer_put(ph, t);
758 static int scmi_clock_state_get(const struct scmi_protocol_handle *ph,
759 u32 clk_id, bool *enabled, bool atomic)
761 struct clock_info *ci = ph->get_priv(ph);
763 return ci->clock_config_get(ph, clk_id, NULL_OEM_TYPE, NULL,
764 enabled, NULL, atomic);
767 static int scmi_clock_config_oem_set(const struct scmi_protocol_handle *ph,
768 u32 clk_id, u8 oem_type, u32 oem_val,
771 struct clock_info *ci = ph->get_priv(ph);
773 return ci->clock_config_set(ph, clk_id, CLK_STATE_UNCHANGED,
774 oem_type, oem_val, atomic);
777 static int scmi_clock_config_oem_get(const struct scmi_protocol_handle *ph,
778 u32 clk_id, u8 oem_type, u32 *oem_val,
779 u32 *attributes, bool atomic)
781 struct clock_info *ci = ph->get_priv(ph);
783 return ci->clock_config_get(ph, clk_id, oem_type, attributes,
784 NULL, oem_val, atomic);
787 static int scmi_clock_count_get(const struct scmi_protocol_handle *ph)
789 struct clock_info *ci = ph->get_priv(ph);
791 return ci->num_clocks;
794 static const struct scmi_clock_info *
795 scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id)
797 struct scmi_clock_info *clk;
798 struct clock_info *ci = ph->get_priv(ph);
800 if (clk_id >= ci->num_clocks)
803 clk = ci->clk + clk_id;
810 static const struct scmi_clk_proto_ops clk_proto_ops = {
811 .count_get = scmi_clock_count_get,
812 .info_get = scmi_clock_info_get,
813 .rate_get = scmi_clock_rate_get,
814 .rate_set = scmi_clock_rate_set,
815 .enable = scmi_clock_enable,
816 .disable = scmi_clock_disable,
817 .state_get = scmi_clock_state_get,
818 .config_oem_get = scmi_clock_config_oem_get,
819 .config_oem_set = scmi_clock_config_oem_set,
820 .parent_set = scmi_clock_set_parent,
821 .parent_get = scmi_clock_get_parent,
824 static int scmi_clk_rate_notify(const struct scmi_protocol_handle *ph,
825 u32 clk_id, int message_id, bool enable)
829 struct scmi_msg_clock_rate_notify *notify;
831 ret = ph->xops->xfer_get_init(ph, message_id, sizeof(*notify), 0, &t);
836 notify->clk_id = cpu_to_le32(clk_id);
837 notify->notify_enable = enable ? cpu_to_le32(BIT(0)) : 0;
839 ret = ph->xops->do_xfer(ph, t);
841 ph->xops->xfer_put(ph, t);
845 static int scmi_clk_set_notify_enabled(const struct scmi_protocol_handle *ph,
846 u8 evt_id, u32 src_id, bool enable)
850 if (evt_id >= ARRAY_SIZE(evt_2_cmd))
853 cmd_id = evt_2_cmd[evt_id];
854 ret = scmi_clk_rate_notify(ph, src_id, cmd_id, enable);
856 pr_debug("FAIL_ENABLED - evt[%X] dom[%d] - ret:%d\n",
857 evt_id, src_id, ret);
862 static void *scmi_clk_fill_custom_report(const struct scmi_protocol_handle *ph,
863 u8 evt_id, ktime_t timestamp,
864 const void *payld, size_t payld_sz,
865 void *report, u32 *src_id)
867 const struct scmi_clock_rate_notify_payld *p = payld;
868 struct scmi_clock_rate_notif_report *r = report;
870 if (sizeof(*p) != payld_sz ||
871 (evt_id != SCMI_EVENT_CLOCK_RATE_CHANGED &&
872 evt_id != SCMI_EVENT_CLOCK_RATE_CHANGE_REQUESTED))
875 r->timestamp = timestamp;
876 r->agent_id = le32_to_cpu(p->agent_id);
877 r->clock_id = le32_to_cpu(p->clock_id);
878 r->rate = get_unaligned_le64(&p->rate_low);
879 *src_id = r->clock_id;
884 static int scmi_clk_get_num_sources(const struct scmi_protocol_handle *ph)
886 struct clock_info *ci = ph->get_priv(ph);
891 return ci->num_clocks;
894 static const struct scmi_event clk_events[] = {
896 .id = SCMI_EVENT_CLOCK_RATE_CHANGED,
897 .max_payld_sz = sizeof(struct scmi_clock_rate_notify_payld),
898 .max_report_sz = sizeof(struct scmi_clock_rate_notif_report),
901 .id = SCMI_EVENT_CLOCK_RATE_CHANGE_REQUESTED,
902 .max_payld_sz = sizeof(struct scmi_clock_rate_notify_payld),
903 .max_report_sz = sizeof(struct scmi_clock_rate_notif_report),
907 static const struct scmi_event_ops clk_event_ops = {
908 .get_num_sources = scmi_clk_get_num_sources,
909 .set_notify_enabled = scmi_clk_set_notify_enabled,
910 .fill_custom_report = scmi_clk_fill_custom_report,
913 static const struct scmi_protocol_events clk_protocol_events = {
914 .queue_sz = SCMI_PROTO_QUEUE_SZ,
915 .ops = &clk_event_ops,
917 .num_events = ARRAY_SIZE(clk_events),
920 static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
924 struct clock_info *cinfo;
926 ret = ph->xops->version_get(ph, &version);
930 dev_dbg(ph->dev, "Clock Version %d.%d\n",
931 PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
933 cinfo = devm_kzalloc(ph->dev, sizeof(*cinfo), GFP_KERNEL);
937 ret = scmi_clock_protocol_attributes_get(ph, cinfo);
941 cinfo->clk = devm_kcalloc(ph->dev, cinfo->num_clocks,
942 sizeof(*cinfo->clk), GFP_KERNEL);
946 for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
947 struct scmi_clock_info *clk = cinfo->clk + clkid;
949 ret = scmi_clock_attributes_get(ph, clkid, clk, version);
951 scmi_clock_describe_rates_get(ph, clkid, clk);
954 if (PROTOCOL_REV_MAJOR(version) >= 0x3) {
955 cinfo->clock_config_set = scmi_clock_config_set_v2;
956 cinfo->clock_config_get = scmi_clock_config_get_v2;
958 cinfo->clock_config_set = scmi_clock_config_set;
959 cinfo->clock_config_get = scmi_clock_config_get;
962 cinfo->version = version;
963 return ph->set_priv(ph, cinfo);
966 static const struct scmi_protocol scmi_clock = {
967 .id = SCMI_PROTOCOL_CLOCK,
968 .owner = THIS_MODULE,
969 .instance_init = &scmi_clock_protocol_init,
970 .ops = &clk_proto_ops,
971 .events = &clk_protocol_events,
974 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(clock, scmi_clock)