drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define ohci_info(ohci, f, args...)     dev_info(ohci->card.device, f, ##args)
  58 #define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  59 #define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  60
  61 #define DESCRIPTOR_OUTPUT_MORE          0
  62 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  63 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  64 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  65 #define DESCRIPTOR_STATUS               (1 << 11)
  66 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  67 #define DESCRIPTOR_PING                 (1 << 7)
  68 #define DESCRIPTOR_YY                   (1 << 6)
  69 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  70 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  71 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  72 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  73 #define DESCRIPTOR_WAIT                 (3 << 0)
  74
  75 #define DESCRIPTOR_CMD                  (0xf << 12)
  76
  77 struct descriptor {
  78         __le16 req_count;
  79         __le16 control;
  80         __le32 data_address;
  81         __le32 branch_address;
  82         __le16 res_count;
  83         __le16 transfer_status;
  84 } __attribute__((aligned(16)));
  85
  86 #define CONTROL_SET(regs)       (regs)
  87 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  88 #define COMMAND_PTR(regs)       ((regs) + 12)
  89 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  90
  91 #define AR_BUFFER_SIZE  (32*1024)
  92 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  93 /* we need at least two pages for proper list management */
  94 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  95
  96 #define MAX_ASYNC_PAYLOAD       4096
  97 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  98 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  99
 100 struct ar_context {
 101         struct fw_ohci *ohci;
 102         struct page *pages[AR_BUFFERS];
 103         void *buffer;
 104         struct descriptor *descriptors;
 105         dma_addr_t descriptors_bus;
 106         void *pointer;
 107         unsigned int last_buffer_index;
 108         u32 regs;
 109         struct tasklet_struct tasklet;
 110 };
 111
 112 struct context;
 113
 114 typedef int (*descriptor_callback_t)(struct context *ctx,
 115                                      struct descriptor *d,
 116                                      struct descriptor *last);
 117
 118 /*
 119  * A buffer that contains a block of DMA-able coherent memory used for
 120  * storing a portion of a DMA descriptor program.
 121  */
 122 struct descriptor_buffer {
 123         struct list_head list;
 124         dma_addr_t buffer_bus;
 125         size_t buffer_size;
 126         size_t used;
 127         struct descriptor buffer[0];
 128 };
 129
 130 struct context {
 131         struct fw_ohci *ohci;
 132         u32 regs;
 133         int total_allocation;
 134         u32 current_bus;
 135         bool running;
 136         bool flushing;
 137
 138         /*
 139          * List of page-sized buffers for storing DMA descriptors.
 140          * Head of list contains buffers in use and tail of list contains
 141          * free buffers.
 142          */
 143         struct list_head buffer_list;
 144
 145         /*
 146          * Pointer to a buffer inside buffer_list that contains the tail
 147          * end of the current DMA program.
 148          */
 149         struct descriptor_buffer *buffer_tail;
 150
 151         /*
 152          * The descriptor containing the branch address of the first
 153          * descriptor that has not yet been filled by the device.
 154          */
 155         struct descriptor *last;
 156
 157         /*
 158          * The last descriptor block in the DMA program. It contains the branch
 159          * address that must be updated upon appending a new descriptor.
 160          */
 161         struct descriptor *prev;
 162         int prev_z;
 163
 164         descriptor_callback_t callback;
 165
 166         struct tasklet_struct tasklet;
 167 };
 168
 169 #define IT_HEADER_SY(v)          ((v) <<  0)
 170 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 171 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 172 #define IT_HEADER_TAG(v)         ((v) << 14)
 173 #define IT_HEADER_SPEED(v)       ((v) << 16)
 174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 175
 176 struct iso_context {
 177         struct fw_iso_context base;
 178         struct context context;
 179         void *header;
 180         size_t header_length;
 181         unsigned long flushing_completions;
 182         u32 mc_buffer_bus;
 183         u16 mc_completed;
 184         u16 last_timestamp;
 185         u8 sync;
 186         u8 tags;
 187 };
 188
 189 #define CONFIG_ROM_SIZE 1024
 190
 191 struct fw_ohci {
 192         struct fw_card card;
 193
 194         __iomem char *registers;
 195         int node_id;
 196         int generation;
 197         int request_generation; /* for timestamping incoming requests */
 198         unsigned quirks;
 199         unsigned int pri_req_max;
 200         u32 bus_time;
 201         bool bus_time_running;
 202         bool is_root;
 203         bool csr_state_setclear_abdicate;
 204         int n_ir;
 205         int n_it;
 206         /*
 207          * Spinlock for accessing fw_ohci data.  Never call out of
 208          * this driver with this lock held.
 209          */
 210         spinlock_t lock;
 211
 212         struct mutex phy_reg_mutex;
 213
 214         void *misc_buffer;
 215         dma_addr_t misc_buffer_bus;
 216
 217         struct ar_context ar_request_ctx;
 218         struct ar_context ar_response_ctx;
 219         struct context at_request_ctx;
 220         struct context at_response_ctx;
 221
 222         u32 it_context_support;
 223         u32 it_context_mask;     /* unoccupied IT contexts */
 224         struct iso_context *it_context_list;
 225         u64 ir_context_channels; /* unoccupied channels */
 226         u32 ir_context_support;
 227         u32 ir_context_mask;     /* unoccupied IR contexts */
 228         struct iso_context *ir_context_list;
 229         u64 mc_channels; /* channels in use by the multichannel IR context */
 230         bool mc_allocated;
 231
 232         __be32    *config_rom;
 233         dma_addr_t config_rom_bus;
 234         __be32    *next_config_rom;
 235         dma_addr_t next_config_rom_bus;
 236         __be32     next_header;
 237
 238         __le32    *self_id;
 239         dma_addr_t self_id_bus;
 240         struct work_struct bus_reset_work;
 241
 242         u32 self_id_buffer[512];
 243 };
 244
 245 static struct workqueue_struct *selfid_workqueue;
 246
 247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 248 {
 249         return container_of(card, struct fw_ohci, card);
 250 }
 251
 252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 253 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 254 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 256 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 257 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 258
 259 #define CONTEXT_RUN     0x8000
 260 #define CONTEXT_WAKE    0x1000
 261 #define CONTEXT_DEAD    0x0800
 262 #define CONTEXT_ACTIVE  0x0400
 263
 264 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 265 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 266 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 267
 268 #define OHCI1394_REGISTER_SIZE          0x800
 269 #define OHCI1394_PCI_HCI_Control        0x40
 270 #define SELF_ID_BUF_SIZE                0x800
 271 #define OHCI_TCODE_PHY_PACKET           0x0e
 272 #define OHCI_VERSION_1_1                0x010010
 273
 274 static char ohci_driver_name[] = KBUILD_MODNAME;
 275
 276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 277 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 278 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 280 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 281 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 282 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 283 #define PCI_DEVICE_ID_VIA_VT630X        0x3044
 284 #define PCI_REV_ID_VIA_VT6306           0x46
 285 #define PCI_DEVICE_ID_VIA_VT6315        0x3403
 286
 287 #define QUIRK_CYCLE_TIMER               0x1
 288 #define QUIRK_RESET_PACKET              0x2
 289 #define QUIRK_BE_HEADERS                0x4
 290 #define QUIRK_NO_1394A                  0x8
 291 #define QUIRK_NO_MSI                    0x10
 292 #define QUIRK_TI_SLLZ059                0x20
 293 #define QUIRK_IR_WAKE                   0x40
 294
 295 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia
 296 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register
 297 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not
 298 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register,
 299 // while it is probable due to detection of any type of PCIe error.
 300 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ        0x80000000
 301
 302 #if IS_ENABLED(CONFIG_X86)
 303
 304 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci)
 305 {
 306         return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ);
 307 }
 308
 309 #define PCI_DEVICE_ID_ASMEDIA_ASM108X   0x1080
 310
 311 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev)
 312 {
 313         const struct pci_dev *pcie_to_pci_bridge;
 314
 315         // Detect any type of AMD Ryzen machine.
 316         if (!static_cpu_has(X86_FEATURE_ZEN))
 317                 return false;
 318
 319         // Detect VIA VT6306/6307/6308.
 320         if (pdev->vendor != PCI_VENDOR_ID_VIA)
 321                 return false;
 322         if (pdev->device != PCI_DEVICE_ID_VIA_VT630X)
 323                 return false;
 324
 325         // Detect Asmedia ASM1083/1085.
 326         pcie_to_pci_bridge = pdev->bus->self;
 327         if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA)
 328                 return false;
 329         if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X)
 330                 return false;
 331
 332         return true;
 333 }
 334
 335 #else
 336 #define has_reboot_by_cycle_timer_read_quirk(ohci) false
 337 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev)   false
 338 #endif
 339
 340 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 341 static const struct {
 342         unsigned short vendor, device, revision, flags;
 343 } ohci_quirks[] = {
 344         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 345                 QUIRK_CYCLE_TIMER},
 346
 347         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 348                 QUIRK_BE_HEADERS},
 349
 350         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 351                 QUIRK_NO_MSI},
 352
 353         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 354                 QUIRK_RESET_PACKET},
 355
 356         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 357                 QUIRK_NO_MSI},
 358
 359         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 360                 QUIRK_CYCLE_TIMER},
 361
 362         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 363                 QUIRK_NO_MSI},
 364
 365         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 366                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 367
 368         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 369                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 370
 371         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 372                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 373
 374         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 375                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 376
 377         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 378                 QUIRK_RESET_PACKET},
 379
 380         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 381                 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 382
 383         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
 384                 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
 385
 386         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
 387                 QUIRK_NO_MSI},
 388
 389         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 390                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 391 };
 392
 393 /* This overrides anything that was found in ohci_quirks[]. */
 394 static int param_quirks;
 395 module_param_named(quirks, param_quirks, int, 0644);
 396 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 397         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 398         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 399         ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 400         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 401         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 402         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 403         ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 404         ")");
 405
 406 #define OHCI_PARAM_DEBUG_AT_AR          1
 407 #define OHCI_PARAM_DEBUG_SELFIDS        2
 408 #define OHCI_PARAM_DEBUG_IRQS           4
 409 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 410
 411 static int param_debug;
 412 module_param_named(debug, param_debug, int, 0644);
 413 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 414         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 415         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 416         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 417         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 418         ", or a combination, or all = -1)");
 419
 420 static bool param_remote_dma;
 421 module_param_named(remote_dma, param_remote_dma, bool, 0444);
 422 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
 423
 424 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 425 {
 426         if (likely(!(param_debug &
 427                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 428                 return;
 429
 430         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 431             !(evt & OHCI1394_busReset))
 432                 return;
 433
 434         ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 435             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 436             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 437             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 438             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 439             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 440             evt & OHCI1394_isochRx              ? " IR"                 : "",
 441             evt & OHCI1394_isochTx              ? " IT"                 : "",
 442             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 443             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 444             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 445             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 446             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 447             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 448             evt & OHCI1394_busReset             ? " busReset"           : "",
 449             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 450                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 451                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 452                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 453                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 454                     OHCI1394_cycleInconsistent |
 455                     OHCI1394_regAccessFail | OHCI1394_busReset)
 456                                                 ? " ?"                  : "");
 457 }
 458
 459 static const char *speed[] = {
 460         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 461 };
 462 static const char *power[] = {
 463         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 464         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 465 };
 466 static const char port[] = { '.', '-', 'p', 'c', };
 467
 468 static char _p(u32 *s, int shift)
 469 {
 470         return port[*s >> shift & 3];
 471 }
 472
 473 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 474 {
 475         u32 *s;
 476
 477         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 478                 return;
 479
 480         ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 481                     self_id_count, generation, ohci->node_id);
 482
 483         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 484                 if ((*s & 1 << 23) == 0)
 485                         ohci_notice(ohci,
 486                             "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 487                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 488                             speed[*s >> 14 & 3], *s >> 16 & 63,
 489                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 490                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 491                 else
 492                         ohci_notice(ohci,
 493                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 494                             *s, *s >> 24 & 63,
 495                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 496                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 497 }
 498
 499 static const char *evts[] = {
 500         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 501         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 502         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 503         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 504         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 505         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 506         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 507         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 508         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 509         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 510         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 511         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 512         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 513         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 514         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 515         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 516         [0x20] = "pending/cancelled",
 517 };
 518 static const char *tcodes[] = {
 519         [0x0] = "QW req",               [0x1] = "BW req",
 520         [0x2] = "W resp",               [0x3] = "-reserved-",
 521         [0x4] = "QR req",               [0x5] = "BR req",
 522         [0x6] = "QR resp",              [0x7] = "BR resp",
 523         [0x8] = "cycle start",          [0x9] = "Lk req",
 524         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 525         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 526         [0xe] = "link internal",        [0xf] = "-reserved-",
 527 };
 528
 529 static void log_ar_at_event(struct fw_ohci *ohci,
 530                             char dir, int speed, u32 *header, int evt)
 531 {
 532         int tcode = header[0] >> 4 & 0xf;
 533         char specific[12];
 534
 535         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 536                 return;
 537
 538         if (unlikely(evt >= ARRAY_SIZE(evts)))
 539                         evt = 0x1f;
 540
 541         if (evt == OHCI1394_evt_bus_reset) {
 542                 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 543                             dir, (header[2] >> 16) & 0xff);
 544                 return;
 545         }
 546
 547         switch (tcode) {
 548         case 0x0: case 0x6: case 0x8:
 549                 snprintf(specific, sizeof(specific), " = %08x",
 550                          be32_to_cpu((__force __be32)header[3]));
 551                 break;
 552         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 553                 snprintf(specific, sizeof(specific), " %x,%x",
 554                          header[3] >> 16, header[3] & 0xffff);
 555                 break;
 556         default:
 557                 specific[0] = '\0';
 558         }
 559
 560         switch (tcode) {
 561         case 0xa:
 562                 ohci_notice(ohci, "A%c %s, %s\n",
 563                             dir, evts[evt], tcodes[tcode]);
 564                 break;
 565         case 0xe:
 566                 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 567                             dir, evts[evt], header[1], header[2]);
 568                 break;
 569         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 570                 ohci_notice(ohci,
 571                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
 572                             dir, speed, header[0] >> 10 & 0x3f,
 573                             header[1] >> 16, header[0] >> 16, evts[evt],
 574                             tcodes[tcode], header[1] & 0xffff, header[2], specific);
 575                 break;
 576         default:
 577                 ohci_notice(ohci,
 578                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 579                             dir, speed, header[0] >> 10 & 0x3f,
 580                             header[1] >> 16, header[0] >> 16, evts[evt],
 581                             tcodes[tcode], specific);
 582         }
 583 }
 584
 585 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 586 {
 587         writel(data, ohci->registers + offset);
 588 }
 589
 590 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 591 {
 592         return readl(ohci->registers + offset);
 593 }
 594
 595 static inline void flush_writes(const struct fw_ohci *ohci)
 596 {
 597         /* Do a dummy read to flush writes. */
 598         reg_read(ohci, OHCI1394_Version);
 599 }
 600
 601 /*
 602  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 603  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 604  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 605  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 606  */
 607 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 608 {
 609         u32 val;
 610         int i;
 611
 612         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 613         for (i = 0; i < 3 + 100; i++) {
 614                 val = reg_read(ohci, OHCI1394_PhyControl);
 615                 if (!~val)
 616                         return -ENODEV; /* Card was ejected. */
 617
 618                 if (val & OHCI1394_PhyControl_ReadDone)
 619                         return OHCI1394_PhyControl_ReadData(val);
 620
 621                 /*
 622                  * Try a few times without waiting.  Sleeping is necessary
 623                  * only when the link/PHY interface is busy.
 624                  */
 625                 if (i >= 3)
 626                         msleep(1);
 627         }
 628         ohci_err(ohci, "failed to read phy reg %d\n", addr);
 629         dump_stack();
 630
 631         return -EBUSY;
 632 }
 633
 634 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 635 {
 636         int i;
 637
 638         reg_write(ohci, OHCI1394_PhyControl,
 639                   OHCI1394_PhyControl_Write(addr, val));
 640         for (i = 0; i < 3 + 100; i++) {
 641                 val = reg_read(ohci, OHCI1394_PhyControl);
 642                 if (!~val)
 643                         return -ENODEV; /* Card was ejected. */
 644
 645                 if (!(val & OHCI1394_PhyControl_WritePending))
 646                         return 0;
 647
 648                 if (i >= 3)
 649                         msleep(1);
 650         }
 651         ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
 652         dump_stack();
 653
 654         return -EBUSY;
 655 }
 656
 657 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 658                           int clear_bits, int set_bits)
 659 {
 660         int ret = read_phy_reg(ohci, addr);
 661         if (ret < 0)
 662                 return ret;
 663
 664         /*
 665          * The interrupt status bits are cleared by writing a one bit.
 666          * Avoid clearing them unless explicitly requested in set_bits.
 667          */
 668         if (addr == 5)
 669                 clear_bits |= PHY_INT_STATUS_BITS;
 670
 671         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 672 }
 673
 674 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 675 {
 676         int ret;
 677
 678         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 679         if (ret < 0)
 680                 return ret;
 681
 682         return read_phy_reg(ohci, addr);
 683 }
 684
 685 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 686 {
 687         struct fw_ohci *ohci = fw_ohci(card);
 688         int ret;
 689
 690         mutex_lock(&ohci->phy_reg_mutex);
 691         ret = read_phy_reg(ohci, addr);
 692         mutex_unlock(&ohci->phy_reg_mutex);
 693
 694         return ret;
 695 }
 696
 697 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 698                                int clear_bits, int set_bits)
 699 {
 700         struct fw_ohci *ohci = fw_ohci(card);
 701         int ret;
 702
 703         mutex_lock(&ohci->phy_reg_mutex);
 704         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 705         mutex_unlock(&ohci->phy_reg_mutex);
 706
 707         return ret;
 708 }
 709
 710 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 711 {
 712         return page_private(ctx->pages[i]);
 713 }
 714
 715 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 716 {
 717         struct descriptor *d;
 718
 719         d = &ctx->descriptors[index];
 720         d->branch_address  &= cpu_to_le32(~0xf);
 721         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 722         d->transfer_status =  0;
 723
 724         wmb(); /* finish init of new descriptors before branch_address update */
 725         d = &ctx->descriptors[ctx->last_buffer_index];
 726         d->branch_address  |= cpu_to_le32(1);
 727
 728         ctx->last_buffer_index = index;
 729
 730         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 731 }
 732
 733 static void ar_context_release(struct ar_context *ctx)
 734 {
 735         unsigned int i;
 736
 737         vunmap(ctx->buffer);
 738
 739         for (i = 0; i < AR_BUFFERS; i++)
 740                 if (ctx->pages[i]) {
 741                         dma_unmap_page(ctx->ohci->card.device,
 742                                        ar_buffer_bus(ctx, i),
 743                                        PAGE_SIZE, DMA_FROM_DEVICE);
 744                         __free_page(ctx->pages[i]);
 745                 }
 746 }
 747
 748 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 749 {
 750         struct fw_ohci *ohci = ctx->ohci;
 751
 752         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 753                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 754                 flush_writes(ohci);
 755
 756                 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 757         }
 758         /* FIXME: restart? */
 759 }
 760
 761 static inline unsigned int ar_next_buffer_index(unsigned int index)
 762 {
 763         return (index + 1) % AR_BUFFERS;
 764 }
 765
 766 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 767 {
 768         return ar_next_buffer_index(ctx->last_buffer_index);
 769 }
 770
 771 /*
 772  * We search for the buffer that contains the last AR packet DMA data written
 773  * by the controller.
 774  */
 775 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 776                                                  unsigned int *buffer_offset)
 777 {
 778         unsigned int i, next_i, last = ctx->last_buffer_index;
 779         __le16 res_count, next_res_count;
 780
 781         i = ar_first_buffer_index(ctx);
 782         res_count = READ_ONCE(ctx->descriptors[i].res_count);
 783
 784         /* A buffer that is not yet completely filled must be the last one. */
 785         while (i != last && res_count == 0) {
 786
 787                 /* Peek at the next descriptor. */
 788                 next_i = ar_next_buffer_index(i);
 789                 rmb(); /* read descriptors in order */
 790                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 791                 /*
 792                  * If the next descriptor is still empty, we must stop at this
 793                  * descriptor.
 794                  */
 795                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 796                         /*
 797                          * The exception is when the DMA data for one packet is
 798                          * split over three buffers; in this case, the middle
 799                          * buffer's descriptor might be never updated by the
 800                          * controller and look still empty, and we have to peek
 801                          * at the third one.
 802                          */
 803                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 804                                 next_i = ar_next_buffer_index(next_i);
 805                                 rmb();
 806                                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 807                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 808                                         goto next_buffer_is_active;
 809                         }
 810
 811                         break;
 812                 }
 813
 814 next_buffer_is_active:
 815                 i = next_i;
 816                 res_count = next_res_count;
 817         }
 818
 819         rmb(); /* read res_count before the DMA data */
 820
 821         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 822         if (*buffer_offset > PAGE_SIZE) {
 823                 *buffer_offset = 0;
 824                 ar_context_abort(ctx, "corrupted descriptor");
 825         }
 826
 827         return i;
 828 }
 829
 830 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 831                                     unsigned int end_buffer_index,
 832                                     unsigned int end_buffer_offset)
 833 {
 834         unsigned int i;
 835
 836         i = ar_first_buffer_index(ctx);
 837         while (i != end_buffer_index) {
 838                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 839                                         ar_buffer_bus(ctx, i),
 840                                         PAGE_SIZE, DMA_FROM_DEVICE);
 841                 i = ar_next_buffer_index(i);
 842         }
 843         if (end_buffer_offset > 0)
 844                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 845                                         ar_buffer_bus(ctx, i),
 846                                         end_buffer_offset, DMA_FROM_DEVICE);
 847 }
 848
 849 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 850 #define cond_le32_to_cpu(v) \
 851         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 852 #else
 853 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 854 #endif
 855
 856 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 857 {
 858         struct fw_ohci *ohci = ctx->ohci;
 859         struct fw_packet p;
 860         u32 status, length, tcode;
 861         int evt;
 862
 863         p.header[0] = cond_le32_to_cpu(buffer[0]);
 864         p.header[1] = cond_le32_to_cpu(buffer[1]);
 865         p.header[2] = cond_le32_to_cpu(buffer[2]);
 866
 867         tcode = (p.header[0] >> 4) & 0x0f;
 868         switch (tcode) {
 869         case TCODE_WRITE_QUADLET_REQUEST:
 870         case TCODE_READ_QUADLET_RESPONSE:
 871                 p.header[3] = (__force __u32) buffer[3];
 872                 p.header_length = 16;
 873                 p.payload_length = 0;
 874                 break;
 875
 876         case TCODE_READ_BLOCK_REQUEST :
 877                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 878                 p.header_length = 16;
 879                 p.payload_length = 0;
 880                 break;
 881
 882         case TCODE_WRITE_BLOCK_REQUEST:
 883         case TCODE_READ_BLOCK_RESPONSE:
 884         case TCODE_LOCK_REQUEST:
 885         case TCODE_LOCK_RESPONSE:
 886                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 887                 p.header_length = 16;
 888                 p.payload_length = p.header[3] >> 16;
 889                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 890                         ar_context_abort(ctx, "invalid packet length");
 891                         return NULL;
 892                 }
 893                 break;
 894
 895         case TCODE_WRITE_RESPONSE:
 896         case TCODE_READ_QUADLET_REQUEST:
 897         case OHCI_TCODE_PHY_PACKET:
 898                 p.header_length = 12;
 899                 p.payload_length = 0;
 900                 break;
 901
 902         default:
 903                 ar_context_abort(ctx, "invalid tcode");
 904                 return NULL;
 905         }
 906
 907         p.payload = (void *) buffer + p.header_length;
 908
 909         /* FIXME: What to do about evt_* errors? */
 910         length = (p.header_length + p.payload_length + 3) / 4;
 911         status = cond_le32_to_cpu(buffer[length]);
 912         evt    = (status >> 16) & 0x1f;
 913
 914         p.ack        = evt - 16;
 915         p.speed      = (status >> 21) & 0x7;
 916         p.timestamp  = status & 0xffff;
 917         p.generation = ohci->request_generation;
 918
 919         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 920
 921         /*
 922          * Several controllers, notably from NEC and VIA, forget to
 923          * write ack_complete status at PHY packet reception.
 924          */
 925         if (evt == OHCI1394_evt_no_status &&
 926             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 927                 p.ack = ACK_COMPLETE;
 928
 929         /*
 930          * The OHCI bus reset handler synthesizes a PHY packet with
 931          * the new generation number when a bus reset happens (see
 932          * section 8.4.2.3).  This helps us determine when a request
 933          * was received and make sure we send the response in the same
 934          * generation.  We only need this for requests; for responses
 935          * we use the unique tlabel for finding the matching
 936          * request.
 937          *
 938          * Alas some chips sometimes emit bus reset packets with a
 939          * wrong generation.  We set the correct generation for these
 940          * at a slightly incorrect time (in bus_reset_work).
 941          */
 942         if (evt == OHCI1394_evt_bus_reset) {
 943                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 944                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 945         } else if (ctx == &ohci->ar_request_ctx) {
 946                 fw_core_handle_request(&ohci->card, &p);
 947         } else {
 948                 fw_core_handle_response(&ohci->card, &p);
 949         }
 950
 951         return buffer + length + 1;
 952 }
 953
 954 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 955 {
 956         void *next;
 957
 958         while (p < end) {
 959                 next = handle_ar_packet(ctx, p);
 960                 if (!next)
 961                         return p;
 962                 p = next;
 963         }
 964
 965         return p;
 966 }
 967
 968 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 969 {
 970         unsigned int i;
 971
 972         i = ar_first_buffer_index(ctx);
 973         while (i != end_buffer) {
 974                 dma_sync_single_for_device(ctx->ohci->card.device,
 975                                            ar_buffer_bus(ctx, i),
 976                                            PAGE_SIZE, DMA_FROM_DEVICE);
 977                 ar_context_link_page(ctx, i);
 978                 i = ar_next_buffer_index(i);
 979         }
 980 }
 981
 982 static void ar_context_tasklet(unsigned long data)
 983 {
 984         struct ar_context *ctx = (struct ar_context *)data;
 985         unsigned int end_buffer_index, end_buffer_offset;
 986         void *p, *end;
 987
 988         p = ctx->pointer;
 989         if (!p)
 990                 return;
 991
 992         end_buffer_index = ar_search_last_active_buffer(ctx,
 993                                                         &end_buffer_offset);
 994         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 995         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 996
 997         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 998                 /*
 999                  * The filled part of the overall buffer wraps around; handle
1000                  * all packets up to the buffer end here.  If the last packet
1001                  * wraps around, its tail will be visible after the buffer end
1002                  * because the buffer start pages are mapped there again.
1003                  */
1004                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
1005                 p = handle_ar_packets(ctx, p, buffer_end);
1006                 if (p < buffer_end)
1007                         goto error;
1008                 /* adjust p to point back into the actual buffer */
1009                 p -= AR_BUFFERS * PAGE_SIZE;
1010         }
1011
1012         p = handle_ar_packets(ctx, p, end);
1013         if (p != end) {
1014                 if (p > end)
1015                         ar_context_abort(ctx, "inconsistent descriptor");
1016                 goto error;
1017         }
1018
1019         ctx->pointer = p;
1020         ar_recycle_buffers(ctx, end_buffer_index);
1021
1022         return;
1023
1024 error:
1025         ctx->pointer = NULL;
1026 }
1027
1028 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
1029                            unsigned int descriptors_offset, u32 regs)
1030 {
1031         unsigned int i;
1032         dma_addr_t dma_addr;
1033         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
1034         struct descriptor *d;
1035
1036         ctx->regs        = regs;
1037         ctx->ohci        = ohci;
1038         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
1039
1040         for (i = 0; i < AR_BUFFERS; i++) {
1041                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
1042                 if (!ctx->pages[i])
1043                         goto out_of_memory;
1044                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1045                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
1046                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1047                         __free_page(ctx->pages[i]);
1048                         ctx->pages[i] = NULL;
1049                         goto out_of_memory;
1050                 }
1051                 set_page_private(ctx->pages[i], dma_addr);
1052         }
1053
1054         for (i = 0; i < AR_BUFFERS; i++)
1055                 pages[i]              = ctx->pages[i];
1056         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1057                 pages[AR_BUFFERS + i] = ctx->pages[i];
1058         ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1059         if (!ctx->buffer)
1060                 goto out_of_memory;
1061
1062         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1063         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1064
1065         for (i = 0; i < AR_BUFFERS; i++) {
1066                 d = &ctx->descriptors[i];
1067                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1068                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1069                                                 DESCRIPTOR_STATUS |
1070                                                 DESCRIPTOR_BRANCH_ALWAYS);
1071                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1072                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1073                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1074         }
1075
1076         return 0;
1077
1078 out_of_memory:
1079         ar_context_release(ctx);
1080
1081         return -ENOMEM;
1082 }
1083
1084 static void ar_context_run(struct ar_context *ctx)
1085 {
1086         unsigned int i;
1087
1088         for (i = 0; i < AR_BUFFERS; i++)
1089                 ar_context_link_page(ctx, i);
1090
1091         ctx->pointer = ctx->buffer;
1092
1093         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1094         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1095 }
1096
1097 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1098 {
1099         __le16 branch;
1100
1101         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1102
1103         /* figure out which descriptor the branch address goes in */
1104         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1105                 return d;
1106         else
1107                 return d + z - 1;
1108 }
1109
1110 static void context_tasklet(unsigned long data)
1111 {
1112         struct context *ctx = (struct context *) data;
1113         struct descriptor *d, *last;
1114         u32 address;
1115         int z;
1116         struct descriptor_buffer *desc;
1117
1118         desc = list_entry(ctx->buffer_list.next,
1119                         struct descriptor_buffer, list);
1120         last = ctx->last;
1121         while (last->branch_address != 0) {
1122                 struct descriptor_buffer *old_desc = desc;
1123                 address = le32_to_cpu(last->branch_address);
1124                 z = address & 0xf;
1125                 address &= ~0xf;
1126                 ctx->current_bus = address;
1127
1128                 /* If the branch address points to a buffer outside of the
1129                  * current buffer, advance to the next buffer. */
1130                 if (address < desc->buffer_bus ||
1131                                 address >= desc->buffer_bus + desc->used)
1132                         desc = list_entry(desc->list.next,
1133                                         struct descriptor_buffer, list);
1134                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1135                 last = find_branch_descriptor(d, z);
1136
1137                 if (!ctx->callback(ctx, d, last))
1138                         break;
1139
1140                 if (old_desc != desc) {
1141                         /* If we've advanced to the next buffer, move the
1142                          * previous buffer to the free list. */
1143                         unsigned long flags;
1144                         old_desc->used = 0;
1145                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1146                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1147                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1148                 }
1149                 ctx->last = last;
1150         }
1151 }
1152
1153 /*
1154  * Allocate a new buffer and add it to the list of free buffers for this
1155  * context.  Must be called with ohci->lock held.
1156  */
1157 static int context_add_buffer(struct context *ctx)
1158 {
1159         struct descriptor_buffer *desc;
1160         dma_addr_t bus_addr;
1161         int offset;
1162
1163         /*
1164          * 16MB of descriptors should be far more than enough for any DMA
1165          * program.  This will catch run-away userspace or DoS attacks.
1166          */
1167         if (ctx->total_allocation >= 16*1024*1024)
1168                 return -ENOMEM;
1169
1170         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1171                         &bus_addr, GFP_ATOMIC);
1172         if (!desc)
1173                 return -ENOMEM;
1174
1175         offset = (void *)&desc->buffer - (void *)desc;
1176         /*
1177          * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
1178          * for descriptors, even 0x10-byte ones. This can cause page faults when
1179          * an IOMMU is in use and the oversized read crosses a page boundary.
1180          * Work around this by always leaving at least 0x10 bytes of padding.
1181          */
1182         desc->buffer_size = PAGE_SIZE - offset - 0x10;
1183         desc->buffer_bus = bus_addr + offset;
1184         desc->used = 0;
1185
1186         list_add_tail(&desc->list, &ctx->buffer_list);
1187         ctx->total_allocation += PAGE_SIZE;
1188
1189         return 0;
1190 }
1191
1192 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1193                         u32 regs, descriptor_callback_t callback)
1194 {
1195         ctx->ohci = ohci;
1196         ctx->regs = regs;
1197         ctx->total_allocation = 0;
1198
1199         INIT_LIST_HEAD(&ctx->buffer_list);
1200         if (context_add_buffer(ctx) < 0)
1201                 return -ENOMEM;
1202
1203         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1204                         struct descriptor_buffer, list);
1205
1206         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1207         ctx->callback = callback;
1208
1209         /*
1210          * We put a dummy descriptor in the buffer that has a NULL
1211          * branch address and looks like it's been sent.  That way we
1212          * have a descriptor to append DMA programs to.
1213          */
1214         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1215         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1216         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1217         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1218         ctx->last = ctx->buffer_tail->buffer;
1219         ctx->prev = ctx->buffer_tail->buffer;
1220         ctx->prev_z = 1;
1221
1222         return 0;
1223 }
1224
1225 static void context_release(struct context *ctx)
1226 {
1227         struct fw_card *card = &ctx->ohci->card;
1228         struct descriptor_buffer *desc, *tmp;
1229
1230         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1231                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1232                         desc->buffer_bus -
1233                         ((void *)&desc->buffer - (void *)desc));
1234 }
1235
1236 /* Must be called with ohci->lock held */
1237 static struct descriptor *context_get_descriptors(struct context *ctx,
1238                                                   int z, dma_addr_t *d_bus)
1239 {
1240         struct descriptor *d = NULL;
1241         struct descriptor_buffer *desc = ctx->buffer_tail;
1242
1243         if (z * sizeof(*d) > desc->buffer_size)
1244                 return NULL;
1245
1246         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1247                 /* No room for the descriptor in this buffer, so advance to the
1248                  * next one. */
1249
1250                 if (desc->list.next == &ctx->buffer_list) {
1251                         /* If there is no free buffer next in the list,
1252                          * allocate one. */
1253                         if (context_add_buffer(ctx) < 0)
1254                                 return NULL;
1255                 }
1256                 desc = list_entry(desc->list.next,
1257                                 struct descriptor_buffer, list);
1258                 ctx->buffer_tail = desc;
1259         }
1260
1261         d = desc->buffer + desc->used / sizeof(*d);
1262         memset(d, 0, z * sizeof(*d));
1263         *d_bus = desc->buffer_bus + desc->used;
1264
1265         return d;
1266 }
1267
1268 static void context_run(struct context *ctx, u32 extra)
1269 {
1270         struct fw_ohci *ohci = ctx->ohci;
1271
1272         reg_write(ohci, COMMAND_PTR(ctx->regs),
1273                   le32_to_cpu(ctx->last->branch_address));
1274         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1275         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1276         ctx->running = true;
1277         flush_writes(ohci);
1278 }
1279
1280 static void context_append(struct context *ctx,
1281                            struct descriptor *d, int z, int extra)
1282 {
1283         dma_addr_t d_bus;
1284         struct descriptor_buffer *desc = ctx->buffer_tail;
1285         struct descriptor *d_branch;
1286
1287         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1288
1289         desc->used += (z + extra) * sizeof(*d);
1290
1291         wmb(); /* finish init of new descriptors before branch_address update */
1292
1293         d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1294         d_branch->branch_address = cpu_to_le32(d_bus | z);
1295
1296         /*
1297          * VT6306 incorrectly checks only the single descriptor at the
1298          * CommandPtr when the wake bit is written, so if it's a
1299          * multi-descriptor block starting with an INPUT_MORE, put a copy of
1300          * the branch address in the first descriptor.
1301          *
1302          * Not doing this for transmit contexts since not sure how it interacts
1303          * with skip addresses.
1304          */
1305         if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1306             d_branch != ctx->prev &&
1307             (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1308              cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1309                 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1310         }
1311
1312         ctx->prev = d;
1313         ctx->prev_z = z;
1314 }
1315
1316 static void context_stop(struct context *ctx)
1317 {
1318         struct fw_ohci *ohci = ctx->ohci;
1319         u32 reg;
1320         int i;
1321
1322         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1323         ctx->running = false;
1324
1325         for (i = 0; i < 1000; i++) {
1326                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1327                 if ((reg & CONTEXT_ACTIVE) == 0)
1328                         return;
1329
1330                 if (i)
1331                         udelay(10);
1332         }
1333         ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1334 }
1335
1336 struct driver_data {
1337         u8 inline_data[8];
1338         struct fw_packet *packet;
1339 };
1340
1341 /*
1342  * This function apppends a packet to the DMA queue for transmission.
1343  * Must always be called with the ochi->lock held to ensure proper
1344  * generation handling and locking around packet queue manipulation.
1345  */
1346 static int at_context_queue_packet(struct context *ctx,
1347                                    struct fw_packet *packet)
1348 {
1349         struct fw_ohci *ohci = ctx->ohci;
1350         dma_addr_t d_bus, payload_bus;
1351         struct driver_data *driver_data;
1352         struct descriptor *d, *last;
1353         __le32 *header;
1354         int z, tcode;
1355
1356         d = context_get_descriptors(ctx, 4, &d_bus);
1357         if (d == NULL) {
1358                 packet->ack = RCODE_SEND_ERROR;
1359                 return -1;
1360         }
1361
1362         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1363         d[0].res_count = cpu_to_le16(packet->timestamp);
1364
1365         /*
1366          * The DMA format for asynchronous link packets is different
1367          * from the IEEE1394 layout, so shift the fields around
1368          * accordingly.
1369          */
1370
1371         tcode = (packet->header[0] >> 4) & 0x0f;
1372         header = (__le32 *) &d[1];
1373         switch (tcode) {
1374         case TCODE_WRITE_QUADLET_REQUEST:
1375         case TCODE_WRITE_BLOCK_REQUEST:
1376         case TCODE_WRITE_RESPONSE:
1377         case TCODE_READ_QUADLET_REQUEST:
1378         case TCODE_READ_BLOCK_REQUEST:
1379         case TCODE_READ_QUADLET_RESPONSE:
1380         case TCODE_READ_BLOCK_RESPONSE:
1381         case TCODE_LOCK_REQUEST:
1382         case TCODE_LOCK_RESPONSE:
1383                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1384                                         (packet->speed << 16));
1385                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1386                                         (packet->header[0] & 0xffff0000));
1387                 header[2] = cpu_to_le32(packet->header[2]);
1388
1389                 if (TCODE_IS_BLOCK_PACKET(tcode))
1390                         header[3] = cpu_to_le32(packet->header[3]);
1391                 else
1392                         header[3] = (__force __le32) packet->header[3];
1393
1394                 d[0].req_count = cpu_to_le16(packet->header_length);
1395                 break;
1396
1397         case TCODE_LINK_INTERNAL:
1398                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1399                                         (packet->speed << 16));
1400                 header[1] = cpu_to_le32(packet->header[1]);
1401                 header[2] = cpu_to_le32(packet->header[2]);
1402                 d[0].req_count = cpu_to_le16(12);
1403
1404                 if (is_ping_packet(&packet->header[1]))
1405                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1406                 break;
1407
1408         case TCODE_STREAM_DATA:
1409                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1410                                         (packet->speed << 16));
1411                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1412                 d[0].req_count = cpu_to_le16(8);
1413                 break;
1414
1415         default:
1416                 /* BUG(); */
1417                 packet->ack = RCODE_SEND_ERROR;
1418                 return -1;
1419         }
1420
1421         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1422         driver_data = (struct driver_data *) &d[3];
1423         driver_data->packet = packet;
1424         packet->driver_data = driver_data;
1425
1426         if (packet->payload_length > 0) {
1427                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1428                         payload_bus = dma_map_single(ohci->card.device,
1429                                                      packet->payload,
1430                                                      packet->payload_length,
1431                                                      DMA_TO_DEVICE);
1432                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1433                                 packet->ack = RCODE_SEND_ERROR;
1434                                 return -1;
1435                         }
1436                         packet->payload_bus     = payload_bus;
1437                         packet->payload_mapped  = true;
1438                 } else {
1439                         memcpy(driver_data->inline_data, packet->payload,
1440                                packet->payload_length);
1441                         payload_bus = d_bus + 3 * sizeof(*d);
1442                 }
1443
1444                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1445                 d[2].data_address = cpu_to_le32(payload_bus);
1446                 last = &d[2];
1447                 z = 3;
1448         } else {
1449                 last = &d[0];
1450                 z = 2;
1451         }
1452
1453         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1454                                      DESCRIPTOR_IRQ_ALWAYS |
1455                                      DESCRIPTOR_BRANCH_ALWAYS);
1456
1457         /* FIXME: Document how the locking works. */
1458         if (ohci->generation != packet->generation) {
1459                 if (packet->payload_mapped)
1460                         dma_unmap_single(ohci->card.device, payload_bus,
1461                                          packet->payload_length, DMA_TO_DEVICE);
1462                 packet->ack = RCODE_GENERATION;
1463                 return -1;
1464         }
1465
1466         context_append(ctx, d, z, 4 - z);
1467
1468         if (ctx->running)
1469                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1470         else
1471                 context_run(ctx, 0);
1472
1473         return 0;
1474 }
1475
1476 static void at_context_flush(struct context *ctx)
1477 {
1478         tasklet_disable(&ctx->tasklet);
1479
1480         ctx->flushing = true;
1481         context_tasklet((unsigned long)ctx);
1482         ctx->flushing = false;
1483
1484         tasklet_enable(&ctx->tasklet);
1485 }
1486
1487 static int handle_at_packet(struct context *context,
1488                             struct descriptor *d,
1489                             struct descriptor *last)
1490 {
1491         struct driver_data *driver_data;
1492         struct fw_packet *packet;
1493         struct fw_ohci *ohci = context->ohci;
1494         int evt;
1495
1496         if (last->transfer_status == 0 && !context->flushing)
1497                 /* This descriptor isn't done yet, stop iteration. */
1498                 return 0;
1499
1500         driver_data = (struct driver_data *) &d[3];
1501         packet = driver_data->packet;
1502         if (packet == NULL)
1503                 /* This packet was cancelled, just continue. */
1504                 return 1;
1505
1506         if (packet->payload_mapped)
1507                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1508                                  packet->payload_length, DMA_TO_DEVICE);
1509
1510         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1511         packet->timestamp = le16_to_cpu(last->res_count);
1512
1513         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1514
1515         switch (evt) {
1516         case OHCI1394_evt_timeout:
1517                 /* Async response transmit timed out. */
1518                 packet->ack = RCODE_CANCELLED;
1519                 break;
1520
1521         case OHCI1394_evt_flushed:
1522                 /*
1523                  * The packet was flushed should give same error as
1524                  * when we try to use a stale generation count.
1525                  */
1526                 packet->ack = RCODE_GENERATION;
1527                 break;
1528
1529         case OHCI1394_evt_missing_ack:
1530                 if (context->flushing)
1531                         packet->ack = RCODE_GENERATION;
1532                 else {
1533                         /*
1534                          * Using a valid (current) generation count, but the
1535                          * node is not on the bus or not sending acks.
1536                          */
1537                         packet->ack = RCODE_NO_ACK;
1538                 }
1539                 break;
1540
1541         case ACK_COMPLETE + 0x10:
1542         case ACK_PENDING + 0x10:
1543         case ACK_BUSY_X + 0x10:
1544         case ACK_BUSY_A + 0x10:
1545         case ACK_BUSY_B + 0x10:
1546         case ACK_DATA_ERROR + 0x10:
1547         case ACK_TYPE_ERROR + 0x10:
1548                 packet->ack = evt - 0x10;
1549                 break;
1550
1551         case OHCI1394_evt_no_status:
1552                 if (context->flushing) {
1553                         packet->ack = RCODE_GENERATION;
1554                         break;
1555                 }
1556                 /* fall through */
1557
1558         default:
1559                 packet->ack = RCODE_SEND_ERROR;
1560                 break;
1561         }
1562
1563         packet->callback(packet, &ohci->card, packet->ack);
1564
1565         return 1;
1566 }
1567
1568 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1569 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1570 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1571 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1572 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1573
1574 static void handle_local_rom(struct fw_ohci *ohci,
1575                              struct fw_packet *packet, u32 csr)
1576 {
1577         struct fw_packet response;
1578         int tcode, length, i;
1579
1580         tcode = HEADER_GET_TCODE(packet->header[0]);
1581         if (TCODE_IS_BLOCK_PACKET(tcode))
1582                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1583         else
1584                 length = 4;
1585
1586         i = csr - CSR_CONFIG_ROM;
1587         if (i + length > CONFIG_ROM_SIZE) {
1588                 fw_fill_response(&response, packet->header,
1589                                  RCODE_ADDRESS_ERROR, NULL, 0);
1590         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1591                 fw_fill_response(&response, packet->header,
1592                                  RCODE_TYPE_ERROR, NULL, 0);
1593         } else {
1594                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1595                                  (void *) ohci->config_rom + i, length);
1596         }
1597
1598         fw_core_handle_response(&ohci->card, &response);
1599 }
1600
1601 static void handle_local_lock(struct fw_ohci *ohci,
1602                               struct fw_packet *packet, u32 csr)
1603 {
1604         struct fw_packet response;
1605         int tcode, length, ext_tcode, sel, try;
1606         __be32 *payload, lock_old;
1607         u32 lock_arg, lock_data;
1608
1609         tcode = HEADER_GET_TCODE(packet->header[0]);
1610         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1611         payload = packet->payload;
1612         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1613
1614         if (tcode == TCODE_LOCK_REQUEST &&
1615             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1616                 lock_arg = be32_to_cpu(payload[0]);
1617                 lock_data = be32_to_cpu(payload[1]);
1618         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1619                 lock_arg = 0;
1620                 lock_data = 0;
1621         } else {
1622                 fw_fill_response(&response, packet->header,
1623                                  RCODE_TYPE_ERROR, NULL, 0);
1624                 goto out;
1625         }
1626
1627         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1628         reg_write(ohci, OHCI1394_CSRData, lock_data);
1629         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1630         reg_write(ohci, OHCI1394_CSRControl, sel);
1631
1632         for (try = 0; try < 20; try++)
1633                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1634                         lock_old = cpu_to_be32(reg_read(ohci,
1635                                                         OHCI1394_CSRData));
1636                         fw_fill_response(&response, packet->header,
1637                                          RCODE_COMPLETE,
1638                                          &lock_old, sizeof(lock_old));
1639                         goto out;
1640                 }
1641
1642         ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1643         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1644
1645  out:
1646         fw_core_handle_response(&ohci->card, &response);
1647 }
1648
1649 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1650 {
1651         u64 offset, csr;
1652
1653         if (ctx == &ctx->ohci->at_request_ctx) {
1654                 packet->ack = ACK_PENDING;
1655                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1656         }
1657
1658         offset =
1659                 ((unsigned long long)
1660                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1661                 packet->header[2];
1662         csr = offset - CSR_REGISTER_BASE;
1663
1664         /* Handle config rom reads. */
1665         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1666                 handle_local_rom(ctx->ohci, packet, csr);
1667         else switch (csr) {
1668         case CSR_BUS_MANAGER_ID:
1669         case CSR_BANDWIDTH_AVAILABLE:
1670         case CSR_CHANNELS_AVAILABLE_HI:
1671         case CSR_CHANNELS_AVAILABLE_LO:
1672                 handle_local_lock(ctx->ohci, packet, csr);
1673                 break;
1674         default:
1675                 if (ctx == &ctx->ohci->at_request_ctx)
1676                         fw_core_handle_request(&ctx->ohci->card, packet);
1677                 else
1678                         fw_core_handle_response(&ctx->ohci->card, packet);
1679                 break;
1680         }
1681
1682         if (ctx == &ctx->ohci->at_response_ctx) {
1683                 packet->ack = ACK_COMPLETE;
1684                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1685         }
1686 }
1687
1688 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1689 {
1690         unsigned long flags;
1691         int ret;
1692
1693         spin_lock_irqsave(&ctx->ohci->lock, flags);
1694
1695         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1696             ctx->ohci->generation == packet->generation) {
1697                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1698                 handle_local_request(ctx, packet);
1699                 return;
1700         }
1701
1702         ret = at_context_queue_packet(ctx, packet);
1703         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1704
1705         if (ret < 0)
1706                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1707
1708 }
1709
1710 static void detect_dead_context(struct fw_ohci *ohci,
1711                                 const char *name, unsigned int regs)
1712 {
1713         u32 ctl;
1714
1715         ctl = reg_read(ohci, CONTROL_SET(regs));
1716         if (ctl & CONTEXT_DEAD)
1717                 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1718                         name, evts[ctl & 0x1f]);
1719 }
1720
1721 static void handle_dead_contexts(struct fw_ohci *ohci)
1722 {
1723         unsigned int i;
1724         char name[8];
1725
1726         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1727         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1728         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1729         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1730         for (i = 0; i < 32; ++i) {
1731                 if (!(ohci->it_context_support & (1 << i)))
1732                         continue;
1733                 sprintf(name, "IT%u", i);
1734                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1735         }
1736         for (i = 0; i < 32; ++i) {
1737                 if (!(ohci->ir_context_support & (1 << i)))
1738                         continue;
1739                 sprintf(name, "IR%u", i);
1740                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1741         }
1742         /* TODO: maybe try to flush and restart the dead contexts */
1743 }
1744
1745 static u32 cycle_timer_ticks(u32 cycle_timer)
1746 {
1747         u32 ticks;
1748
1749         ticks = cycle_timer & 0xfff;
1750         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1751         ticks += (3072 * 8000) * (cycle_timer >> 25);
1752
1753         return ticks;
1754 }
1755
1756 /*
1757  * Some controllers exhibit one or more of the following bugs when updating the
1758  * iso cycle timer register:
1759  *  - When the lowest six bits are wrapping around to zero, a read that happens
1760  *    at the same time will return garbage in the lowest ten bits.
1761  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1762  *    not incremented for about 60 ns.
1763  *  - Occasionally, the entire register reads zero.
1764  *
1765  * To catch these, we read the register three times and ensure that the
1766  * difference between each two consecutive reads is approximately the same, i.e.
1767  * less than twice the other.  Furthermore, any negative difference indicates an
1768  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1769  * execute, so we have enough precision to compute the ratio of the differences.)
1770  */
1771 static u32 get_cycle_time(struct fw_ohci *ohci)
1772 {
1773         u32 c0, c1, c2;
1774         u32 t0, t1, t2;
1775         s32 diff01, diff12;
1776         int i;
1777
1778         if (has_reboot_by_cycle_timer_read_quirk(ohci))
1779                 return 0;
1780
1781         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1782
1783         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1784                 i = 0;
1785                 c1 = c2;
1786                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1787                 do {
1788                         c0 = c1;
1789                         c1 = c2;
1790                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1791                         t0 = cycle_timer_ticks(c0);
1792                         t1 = cycle_timer_ticks(c1);
1793                         t2 = cycle_timer_ticks(c2);
1794                         diff01 = t1 - t0;
1795                         diff12 = t2 - t1;
1796                 } while ((diff01 <= 0 || diff12 <= 0 ||
1797                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1798                          && i++ < 20);
1799         }
1800
1801         return c2;
1802 }
1803
1804 /*
1805  * This function has to be called at least every 64 seconds.  The bus_time
1806  * field stores not only the upper 25 bits of the BUS_TIME register but also
1807  * the most significant bit of the cycle timer in bit 6 so that we can detect
1808  * changes in this bit.
1809  */
1810 static u32 update_bus_time(struct fw_ohci *ohci)
1811 {
1812         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1813
1814         if (unlikely(!ohci->bus_time_running)) {
1815                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1816                 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1817                                  (cycle_time_seconds & 0x40);
1818                 ohci->bus_time_running = true;
1819         }
1820
1821         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1822                 ohci->bus_time += 0x40;
1823
1824         return ohci->bus_time | cycle_time_seconds;
1825 }
1826
1827 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1828 {
1829         int reg;
1830
1831         mutex_lock(&ohci->phy_reg_mutex);
1832         reg = write_phy_reg(ohci, 7, port_index);
1833         if (reg >= 0)
1834                 reg = read_phy_reg(ohci, 8);
1835         mutex_unlock(&ohci->phy_reg_mutex);
1836         if (reg < 0)
1837                 return reg;
1838
1839         switch (reg & 0x0f) {
1840         case 0x06:
1841                 return 2;       /* is child node (connected to parent node) */
1842         case 0x0e:
1843                 return 3;       /* is parent node (connected to child node) */
1844         }
1845         return 1;               /* not connected */
1846 }
1847
1848 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1849         int self_id_count)
1850 {
1851         int i;
1852         u32 entry;
1853
1854         for (i = 0; i < self_id_count; i++) {
1855                 entry = ohci->self_id_buffer[i];
1856                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1857                         return -1;
1858                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1859                         return i;
1860         }
1861         return i;
1862 }
1863
1864 static int initiated_reset(struct fw_ohci *ohci)
1865 {
1866         int reg;
1867         int ret = 0;
1868
1869         mutex_lock(&ohci->phy_reg_mutex);
1870         reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1871         if (reg >= 0) {
1872                 reg = read_phy_reg(ohci, 8);
1873                 reg |= 0x40;
1874                 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1875                 if (reg >= 0) {
1876                         reg = read_phy_reg(ohci, 12); /* read register 12 */
1877                         if (reg >= 0) {
1878                                 if ((reg & 0x08) == 0x08) {
1879                                         /* bit 3 indicates "initiated reset" */
1880                                         ret = 0x2;
1881                                 }
1882                         }
1883                 }
1884         }
1885         mutex_unlock(&ohci->phy_reg_mutex);
1886         return ret;
1887 }
1888
1889 /*
1890  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1891  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1892  * Construct the selfID from phy register contents.
1893  */
1894 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1895 {
1896         int reg, i, pos, status;
1897         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1898         u32 self_id = 0x8040c800;
1899
1900         reg = reg_read(ohci, OHCI1394_NodeID);
1901         if (!(reg & OHCI1394_NodeID_idValid)) {
1902                 ohci_notice(ohci,
1903                             "node ID not valid, new bus reset in progress\n");
1904                 return -EBUSY;
1905         }
1906         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1907
1908         reg = ohci_read_phy_reg(&ohci->card, 4);
1909         if (reg < 0)
1910                 return reg;
1911         self_id |= ((reg & 0x07) << 8); /* power class */
1912
1913         reg = ohci_read_phy_reg(&ohci->card, 1);
1914         if (reg < 0)
1915                 return reg;
1916         self_id |= ((reg & 0x3f) << 16); /* gap count */
1917
1918         for (i = 0; i < 3; i++) {
1919                 status = get_status_for_port(ohci, i);
1920                 if (status < 0)
1921                         return status;
1922                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1923         }
1924
1925         self_id |= initiated_reset(ohci);
1926
1927         pos = get_self_id_pos(ohci, self_id, self_id_count);
1928         if (pos >= 0) {
1929                 memmove(&(ohci->self_id_buffer[pos+1]),
1930                         &(ohci->self_id_buffer[pos]),
1931                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1932                 ohci->self_id_buffer[pos] = self_id;
1933                 self_id_count++;
1934         }
1935         return self_id_count;
1936 }
1937
1938 static void bus_reset_work(struct work_struct *work)
1939 {
1940         struct fw_ohci *ohci =
1941                 container_of(work, struct fw_ohci, bus_reset_work);
1942         int self_id_count, generation, new_generation, i, j;
1943         u32 reg;
1944         void *free_rom = NULL;
1945         dma_addr_t free_rom_bus = 0;
1946         bool is_new_root;
1947
1948         reg = reg_read(ohci, OHCI1394_NodeID);
1949         if (!(reg & OHCI1394_NodeID_idValid)) {
1950                 ohci_notice(ohci,
1951                             "node ID not valid, new bus reset in progress\n");
1952                 return;
1953         }
1954         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1955                 ohci_notice(ohci, "malconfigured bus\n");
1956                 return;
1957         }
1958         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1959                                OHCI1394_NodeID_nodeNumber);
1960
1961         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1962         if (!(ohci->is_root && is_new_root))
1963                 reg_write(ohci, OHCI1394_LinkControlSet,
1964                           OHCI1394_LinkControl_cycleMaster);
1965         ohci->is_root = is_new_root;
1966
1967         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1968         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1969                 ohci_notice(ohci, "self ID receive error\n");
1970                 return;
1971         }
1972         /*
1973          * The count in the SelfIDCount register is the number of
1974          * bytes in the self ID receive buffer.  Since we also receive
1975          * the inverted quadlets and a header quadlet, we shift one
1976          * bit extra to get the actual number of self IDs.
1977          */
1978         self_id_count = (reg >> 3) & 0xff;
1979
1980         if (self_id_count > 252) {
1981                 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1982                 return;
1983         }
1984
1985         generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1986         rmb();
1987
1988         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1989                 u32 id  = cond_le32_to_cpu(ohci->self_id[i]);
1990                 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1991
1992                 if (id != ~id2) {
1993                         /*
1994                          * If the invalid data looks like a cycle start packet,
1995                          * it's likely to be the result of the cycle master
1996                          * having a wrong gap count.  In this case, the self IDs
1997                          * so far are valid and should be processed so that the
1998                          * bus manager can then correct the gap count.
1999                          */
2000                         if (id == 0xffff008f) {
2001                                 ohci_notice(ohci, "ignoring spurious self IDs\n");
2002                                 self_id_count = j;
2003                                 break;
2004                         }
2005
2006                         ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
2007                                     j, self_id_count, id, id2);
2008                         return;
2009                 }
2010                 ohci->self_id_buffer[j] = id;
2011         }
2012
2013         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2014                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
2015                 if (self_id_count < 0) {
2016                         ohci_notice(ohci,
2017                                     "could not construct local self ID\n");
2018                         return;
2019                 }
2020         }
2021
2022         if (self_id_count == 0) {
2023                 ohci_notice(ohci, "no self IDs\n");
2024                 return;
2025         }
2026         rmb();
2027
2028         /*
2029          * Check the consistency of the self IDs we just read.  The
2030          * problem we face is that a new bus reset can start while we
2031          * read out the self IDs from the DMA buffer. If this happens,
2032          * the DMA buffer will be overwritten with new self IDs and we
2033          * will read out inconsistent data.  The OHCI specification
2034          * (section 11.2) recommends a technique similar to
2035          * linux/seqlock.h, where we remember the generation of the
2036          * self IDs in the buffer before reading them out and compare
2037          * it to the current generation after reading them out.  If
2038          * the two generations match we know we have a consistent set
2039          * of self IDs.
2040          */
2041
2042         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
2043         if (new_generation != generation) {
2044                 ohci_notice(ohci, "new bus reset, discarding self ids\n");
2045                 return;
2046         }
2047
2048         /* FIXME: Document how the locking works. */
2049         spin_lock_irq(&ohci->lock);
2050
2051         ohci->generation = -1; /* prevent AT packet queueing */
2052         context_stop(&ohci->at_request_ctx);
2053         context_stop(&ohci->at_response_ctx);
2054
2055         spin_unlock_irq(&ohci->lock);
2056
2057         /*
2058          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2059          * packets in the AT queues and software needs to drain them.
2060          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2061          */
2062         at_context_flush(&ohci->at_request_ctx);
2063         at_context_flush(&ohci->at_response_ctx);
2064
2065         spin_lock_irq(&ohci->lock);
2066
2067         ohci->generation = generation;
2068         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2069         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2070                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2071
2072         if (ohci->quirks & QUIRK_RESET_PACKET)
2073                 ohci->request_generation = generation;
2074
2075         /*
2076          * This next bit is unrelated to the AT context stuff but we
2077          * have to do it under the spinlock also.  If a new config rom
2078          * was set up before this reset, the old one is now no longer
2079          * in use and we can free it. Update the config rom pointers
2080          * to point to the current config rom and clear the
2081          * next_config_rom pointer so a new update can take place.
2082          */
2083
2084         if (ohci->next_config_rom != NULL) {
2085                 if (ohci->next_config_rom != ohci->config_rom) {
2086                         free_rom      = ohci->config_rom;
2087                         free_rom_bus  = ohci->config_rom_bus;
2088                 }
2089                 ohci->config_rom      = ohci->next_config_rom;
2090                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
2091                 ohci->next_config_rom = NULL;
2092
2093                 /*
2094                  * Restore config_rom image and manually update
2095                  * config_rom registers.  Writing the header quadlet
2096                  * will indicate that the config rom is ready, so we
2097                  * do that last.
2098                  */
2099                 reg_write(ohci, OHCI1394_BusOptions,
2100                           be32_to_cpu(ohci->config_rom[2]));
2101                 ohci->config_rom[0] = ohci->next_header;
2102                 reg_write(ohci, OHCI1394_ConfigROMhdr,
2103                           be32_to_cpu(ohci->next_header));
2104         }
2105
2106         if (param_remote_dma) {
2107                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2108                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2109         }
2110
2111         spin_unlock_irq(&ohci->lock);
2112
2113         if (free_rom)
2114                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2115                                   free_rom, free_rom_bus);
2116
2117         log_selfids(ohci, generation, self_id_count);
2118
2119         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2120                                  self_id_count, ohci->self_id_buffer,
2121                                  ohci->csr_state_setclear_abdicate);
2122         ohci->csr_state_setclear_abdicate = false;
2123 }
2124
2125 static irqreturn_t irq_handler(int irq, void *data)
2126 {
2127         struct fw_ohci *ohci = data;
2128         u32 event, iso_event;
2129         int i;
2130
2131         event = reg_read(ohci, OHCI1394_IntEventClear);
2132
2133         if (!event || !~event)
2134                 return IRQ_NONE;
2135
2136         /*
2137          * busReset and postedWriteErr events must not be cleared yet
2138          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2139          */
2140         reg_write(ohci, OHCI1394_IntEventClear,
2141                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2142         log_irqs(ohci, event);
2143         if (event & OHCI1394_busReset)
2144                 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2145
2146         if (event & OHCI1394_selfIDComplete)
2147                 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2148
2149         if (event & OHCI1394_RQPkt)
2150                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2151
2152         if (event & OHCI1394_RSPkt)
2153                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2154
2155         if (event & OHCI1394_reqTxComplete)
2156                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2157
2158         if (event & OHCI1394_respTxComplete)
2159                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2160
2161         if (event & OHCI1394_isochRx) {
2162                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2163                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2164
2165                 while (iso_event) {
2166                         i = ffs(iso_event) - 1;
2167                         tasklet_schedule(
2168                                 &ohci->ir_context_list[i].context.tasklet);
2169                         iso_event &= ~(1 << i);
2170                 }
2171         }
2172
2173         if (event & OHCI1394_isochTx) {
2174                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2175                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2176
2177                 while (iso_event) {
2178                         i = ffs(iso_event) - 1;
2179                         tasklet_schedule(
2180                                 &ohci->it_context_list[i].context.tasklet);
2181                         iso_event &= ~(1 << i);
2182                 }
2183         }
2184
2185         if (unlikely(event & OHCI1394_regAccessFail))
2186                 ohci_err(ohci, "register access failure\n");
2187
2188         if (unlikely(event & OHCI1394_postedWriteErr)) {
2189                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2190                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2191                 reg_write(ohci, OHCI1394_IntEventClear,
2192                           OHCI1394_postedWriteErr);
2193                 if (printk_ratelimit())
2194                         ohci_err(ohci, "PCI posted write error\n");
2195         }
2196
2197         if (unlikely(event & OHCI1394_cycleTooLong)) {
2198                 if (printk_ratelimit())
2199                         ohci_notice(ohci, "isochronous cycle too long\n");
2200                 reg_write(ohci, OHCI1394_LinkControlSet,
2201                           OHCI1394_LinkControl_cycleMaster);
2202         }
2203
2204         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2205                 /*
2206                  * We need to clear this event bit in order to make
2207                  * cycleMatch isochronous I/O work.  In theory we should
2208                  * stop active cycleMatch iso contexts now and restart
2209                  * them at least two cycles later.  (FIXME?)
2210                  */
2211                 if (printk_ratelimit())
2212                         ohci_notice(ohci, "isochronous cycle inconsistent\n");
2213         }
2214
2215         if (unlikely(event & OHCI1394_unrecoverableError))
2216                 handle_dead_contexts(ohci);
2217
2218         if (event & OHCI1394_cycle64Seconds) {
2219                 spin_lock(&ohci->lock);
2220                 update_bus_time(ohci);
2221                 spin_unlock(&ohci->lock);
2222         } else
2223                 flush_writes(ohci);
2224
2225         return IRQ_HANDLED;
2226 }
2227
2228 static int software_reset(struct fw_ohci *ohci)
2229 {
2230         u32 val;
2231         int i;
2232
2233         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2234         for (i = 0; i < 500; i++) {
2235                 val = reg_read(ohci, OHCI1394_HCControlSet);
2236                 if (!~val)
2237                         return -ENODEV; /* Card was ejected. */
2238
2239                 if (!(val & OHCI1394_HCControl_softReset))
2240                         return 0;
2241
2242                 msleep(1);
2243         }
2244
2245         return -EBUSY;
2246 }
2247
2248 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2249 {
2250         size_t size = length * 4;
2251
2252         memcpy(dest, src, size);
2253         if (size < CONFIG_ROM_SIZE)
2254                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2255 }
2256
2257 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2258 {
2259         bool enable_1394a;
2260         int ret, clear, set, offset;
2261
2262         /* Check if the driver should configure link and PHY. */
2263         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2264               OHCI1394_HCControl_programPhyEnable))
2265                 return 0;
2266
2267         /* Paranoia: check whether the PHY supports 1394a, too. */
2268         enable_1394a = false;
2269         ret = read_phy_reg(ohci, 2);
2270         if (ret < 0)
2271                 return ret;
2272         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2273                 ret = read_paged_phy_reg(ohci, 1, 8);
2274                 if (ret < 0)
2275                         return ret;
2276                 if (ret >= 1)
2277                         enable_1394a = true;
2278         }
2279
2280         if (ohci->quirks & QUIRK_NO_1394A)
2281                 enable_1394a = false;
2282
2283         /* Configure PHY and link consistently. */
2284         if (enable_1394a) {
2285                 clear = 0;
2286                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2287         } else {
2288                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2289                 set = 0;
2290         }
2291         ret = update_phy_reg(ohci, 5, clear, set);
2292         if (ret < 0)
2293                 return ret;
2294
2295         if (enable_1394a)
2296                 offset = OHCI1394_HCControlSet;
2297         else
2298                 offset = OHCI1394_HCControlClear;
2299         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2300
2301         /* Clean up: configuration has been taken care of. */
2302         reg_write(ohci, OHCI1394_HCControlClear,
2303                   OHCI1394_HCControl_programPhyEnable);
2304
2305         return 0;
2306 }
2307
2308 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2309 {
2310         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2311         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2312         int reg, i;
2313
2314         reg = read_phy_reg(ohci, 2);
2315         if (reg < 0)
2316                 return reg;
2317         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2318                 return 0;
2319
2320         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2321                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2322                 if (reg < 0)
2323                         return reg;
2324                 if (reg != id[i])
2325                         return 0;
2326         }
2327         return 1;
2328 }
2329
2330 static int ohci_enable(struct fw_card *card,
2331                        const __be32 *config_rom, size_t length)
2332 {
2333         struct fw_ohci *ohci = fw_ohci(card);
2334         u32 lps, version, irqs;
2335         int i, ret;
2336
2337         ret = software_reset(ohci);
2338         if (ret < 0) {
2339                 ohci_err(ohci, "failed to reset ohci card\n");
2340                 return ret;
2341         }
2342
2343         /*
2344          * Now enable LPS, which we need in order to start accessing
2345          * most of the registers.  In fact, on some cards (ALI M5251),
2346          * accessing registers in the SClk domain without LPS enabled
2347          * will lock up the machine.  Wait 50msec to make sure we have
2348          * full link enabled.  However, with some cards (well, at least
2349          * a JMicron PCIe card), we have to try again sometimes.
2350          *
2351          * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2352          * cannot actually use the phy at that time.  These need tens of
2353          * millisecods pause between LPS write and first phy access too.
2354          */
2355
2356         reg_write(ohci, OHCI1394_HCControlSet,
2357                   OHCI1394_HCControl_LPS |
2358                   OHCI1394_HCControl_postedWriteEnable);
2359         flush_writes(ohci);
2360
2361         for (lps = 0, i = 0; !lps && i < 3; i++) {
2362                 msleep(50);
2363                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2364                       OHCI1394_HCControl_LPS;
2365         }
2366
2367         if (!lps) {
2368                 ohci_err(ohci, "failed to set Link Power Status\n");
2369                 return -EIO;
2370         }
2371
2372         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2373                 ret = probe_tsb41ba3d(ohci);
2374                 if (ret < 0)
2375                         return ret;
2376                 if (ret)
2377                         ohci_notice(ohci, "local TSB41BA3D phy\n");
2378                 else
2379                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2380         }
2381
2382         reg_write(ohci, OHCI1394_HCControlClear,
2383                   OHCI1394_HCControl_noByteSwapData);
2384
2385         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2386         reg_write(ohci, OHCI1394_LinkControlSet,
2387                   OHCI1394_LinkControl_cycleTimerEnable |
2388                   OHCI1394_LinkControl_cycleMaster);
2389
2390         reg_write(ohci, OHCI1394_ATRetries,
2391                   OHCI1394_MAX_AT_REQ_RETRIES |
2392                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2393                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2394                   (200 << 16));
2395
2396         ohci->bus_time_running = false;
2397
2398         for (i = 0; i < 32; i++)
2399                 if (ohci->ir_context_support & (1 << i))
2400                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2401                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2402
2403         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2404         if (version >= OHCI_VERSION_1_1) {
2405                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2406                           0xfffffffe);
2407                 card->broadcast_channel_auto_allocated = true;
2408         }
2409
2410         /* Get implemented bits of the priority arbitration request counter. */
2411         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2412         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2413         reg_write(ohci, OHCI1394_FairnessControl, 0);
2414         card->priority_budget_implemented = ohci->pri_req_max != 0;
2415
2416         reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2417         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2418         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2419
2420         ret = configure_1394a_enhancements(ohci);
2421         if (ret < 0)
2422                 return ret;
2423
2424         /* Activate link_on bit and contender bit in our self ID packets.*/
2425         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2426         if (ret < 0)
2427                 return ret;
2428
2429         /*
2430          * When the link is not yet enabled, the atomic config rom
2431          * update mechanism described below in ohci_set_config_rom()
2432          * is not active.  We have to update ConfigRomHeader and
2433          * BusOptions manually, and the write to ConfigROMmap takes
2434          * effect immediately.  We tie this to the enabling of the
2435          * link, so we have a valid config rom before enabling - the
2436          * OHCI requires that ConfigROMhdr and BusOptions have valid
2437          * values before enabling.
2438          *
2439          * However, when the ConfigROMmap is written, some controllers
2440          * always read back quadlets 0 and 2 from the config rom to
2441          * the ConfigRomHeader and BusOptions registers on bus reset.
2442          * They shouldn't do that in this initial case where the link
2443          * isn't enabled.  This means we have to use the same
2444          * workaround here, setting the bus header to 0 and then write
2445          * the right values in the bus reset tasklet.
2446          */
2447
2448         if (config_rom) {
2449                 ohci->next_config_rom =
2450                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2451                                            &ohci->next_config_rom_bus,
2452                                            GFP_KERNEL);
2453                 if (ohci->next_config_rom == NULL)
2454                         return -ENOMEM;
2455
2456                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2457         } else {
2458                 /*
2459                  * In the suspend case, config_rom is NULL, which
2460                  * means that we just reuse the old config rom.
2461                  */
2462                 ohci->next_config_rom = ohci->config_rom;
2463                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2464         }
2465
2466         ohci->next_header = ohci->next_config_rom[0];
2467         ohci->next_config_rom[0] = 0;
2468         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2469         reg_write(ohci, OHCI1394_BusOptions,
2470                   be32_to_cpu(ohci->next_config_rom[2]));
2471         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2472
2473         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2474
2475         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2476                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2477                 OHCI1394_isochTx | OHCI1394_isochRx |
2478                 OHCI1394_postedWriteErr |
2479                 OHCI1394_selfIDComplete |
2480                 OHCI1394_regAccessFail |
2481                 OHCI1394_cycleInconsistent |
2482                 OHCI1394_unrecoverableError |
2483                 OHCI1394_cycleTooLong |
2484                 OHCI1394_masterIntEnable;
2485         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2486                 irqs |= OHCI1394_busReset;
2487         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2488
2489         reg_write(ohci, OHCI1394_HCControlSet,
2490                   OHCI1394_HCControl_linkEnable |
2491                   OHCI1394_HCControl_BIBimageValid);
2492
2493         reg_write(ohci, OHCI1394_LinkControlSet,
2494                   OHCI1394_LinkControl_rcvSelfID |
2495                   OHCI1394_LinkControl_rcvPhyPkt);
2496
2497         ar_context_run(&ohci->ar_request_ctx);
2498         ar_context_run(&ohci->ar_response_ctx);
2499
2500         flush_writes(ohci);
2501
2502         /* We are ready to go, reset bus to finish initialization. */
2503         fw_schedule_bus_reset(&ohci->card, false, true);
2504
2505         return 0;
2506 }
2507
2508 static int ohci_set_config_rom(struct fw_card *card,
2509                                const __be32 *config_rom, size_t length)
2510 {
2511         struct fw_ohci *ohci;
2512         __be32 *next_config_rom;
2513         dma_addr_t next_config_rom_bus;
2514
2515         ohci = fw_ohci(card);
2516
2517         /*
2518          * When the OHCI controller is enabled, the config rom update
2519          * mechanism is a bit tricky, but easy enough to use.  See
2520          * section 5.5.6 in the OHCI specification.
2521          *
2522          * The OHCI controller caches the new config rom address in a
2523          * shadow register (ConfigROMmapNext) and needs a bus reset
2524          * for the changes to take place.  When the bus reset is
2525          * detected, the controller loads the new values for the
2526          * ConfigRomHeader and BusOptions registers from the specified
2527          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2528          * shadow register. All automatically and atomically.
2529          *
2530          * Now, there's a twist to this story.  The automatic load of
2531          * ConfigRomHeader and BusOptions doesn't honor the
2532          * noByteSwapData bit, so with a be32 config rom, the
2533          * controller will load be32 values in to these registers
2534          * during the atomic update, even on litte endian
2535          * architectures.  The workaround we use is to put a 0 in the
2536          * header quadlet; 0 is endian agnostic and means that the
2537          * config rom isn't ready yet.  In the bus reset tasklet we
2538          * then set up the real values for the two registers.
2539          *
2540          * We use ohci->lock to avoid racing with the code that sets
2541          * ohci->next_config_rom to NULL (see bus_reset_work).
2542          */
2543
2544         next_config_rom =
2545                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2546                                    &next_config_rom_bus, GFP_KERNEL);
2547         if (next_config_rom == NULL)
2548                 return -ENOMEM;
2549
2550         spin_lock_irq(&ohci->lock);
2551
2552         /*
2553          * If there is not an already pending config_rom update,
2554          * push our new allocation into the ohci->next_config_rom
2555          * and then mark the local variable as null so that we
2556          * won't deallocate the new buffer.
2557          *
2558          * OTOH, if there is a pending config_rom update, just
2559          * use that buffer with the new config_rom data, and
2560          * let this routine free the unused DMA allocation.
2561          */
2562
2563         if (ohci->next_config_rom == NULL) {
2564                 ohci->next_config_rom = next_config_rom;
2565                 ohci->next_config_rom_bus = next_config_rom_bus;
2566                 next_config_rom = NULL;
2567         }
2568
2569         copy_config_rom(ohci->next_config_rom, config_rom, length);
2570
2571         ohci->next_header = config_rom[0];
2572         ohci->next_config_rom[0] = 0;
2573
2574         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2575
2576         spin_unlock_irq(&ohci->lock);
2577
2578         /* If we didn't use the DMA allocation, delete it. */
2579         if (next_config_rom != NULL)
2580                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2581                                   next_config_rom, next_config_rom_bus);
2582
2583         /*
2584          * Now initiate a bus reset to have the changes take
2585          * effect. We clean up the old config rom memory and DMA
2586          * mappings in the bus reset tasklet, since the OHCI
2587          * controller could need to access it before the bus reset
2588          * takes effect.
2589          */
2590
2591         fw_schedule_bus_reset(&ohci->card, true, true);
2592
2593         return 0;
2594 }
2595
2596 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2597 {
2598         struct fw_ohci *ohci = fw_ohci(card);
2599
2600         at_context_transmit(&ohci->at_request_ctx, packet);
2601 }
2602
2603 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2604 {
2605         struct fw_ohci *ohci = fw_ohci(card);
2606
2607         at_context_transmit(&ohci->at_response_ctx, packet);
2608 }
2609
2610 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2611 {
2612         struct fw_ohci *ohci = fw_ohci(card);
2613         struct context *ctx = &ohci->at_request_ctx;
2614         struct driver_data *driver_data = packet->driver_data;
2615         int ret = -ENOENT;
2616
2617         tasklet_disable(&ctx->tasklet);
2618
2619         if (packet->ack != 0)
2620                 goto out;
2621
2622         if (packet->payload_mapped)
2623                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2624                                  packet->payload_length, DMA_TO_DEVICE);
2625
2626         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2627         driver_data->packet = NULL;
2628         packet->ack = RCODE_CANCELLED;
2629         packet->callback(packet, &ohci->card, packet->ack);
2630         ret = 0;
2631  out:
2632         tasklet_enable(&ctx->tasklet);
2633
2634         return ret;
2635 }
2636
2637 static int ohci_enable_phys_dma(struct fw_card *card,
2638                                 int node_id, int generation)
2639 {
2640         struct fw_ohci *ohci = fw_ohci(card);
2641         unsigned long flags;
2642         int n, ret = 0;
2643
2644         if (param_remote_dma)
2645                 return 0;
2646
2647         /*
2648          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2649          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2650          */
2651
2652         spin_lock_irqsave(&ohci->lock, flags);
2653
2654         if (ohci->generation != generation) {
2655                 ret = -ESTALE;
2656                 goto out;
2657         }
2658
2659         /*
2660          * Note, if the node ID contains a non-local bus ID, physical DMA is
2661          * enabled for _all_ nodes on remote buses.
2662          */
2663
2664         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2665         if (n < 32)
2666                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2667         else
2668                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2669
2670         flush_writes(ohci);
2671  out:
2672         spin_unlock_irqrestore(&ohci->lock, flags);
2673
2674         return ret;
2675 }
2676
2677 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2678 {
2679         struct fw_ohci *ohci = fw_ohci(card);
2680         unsigned long flags;
2681         u32 value;
2682
2683         switch (csr_offset) {
2684         case CSR_STATE_CLEAR:
2685         case CSR_STATE_SET:
2686                 if (ohci->is_root &&
2687                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2688                      OHCI1394_LinkControl_cycleMaster))
2689                         value = CSR_STATE_BIT_CMSTR;
2690                 else
2691                         value = 0;
2692                 if (ohci->csr_state_setclear_abdicate)
2693                         value |= CSR_STATE_BIT_ABDICATE;
2694
2695                 return value;
2696
2697         case CSR_NODE_IDS:
2698                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2699
2700         case CSR_CYCLE_TIME:
2701                 return get_cycle_time(ohci);
2702
2703         case CSR_BUS_TIME:
2704                 /*
2705                  * We might be called just after the cycle timer has wrapped
2706                  * around but just before the cycle64Seconds handler, so we
2707                  * better check here, too, if the bus time needs to be updated.
2708                  */
2709                 spin_lock_irqsave(&ohci->lock, flags);
2710                 value = update_bus_time(ohci);
2711                 spin_unlock_irqrestore(&ohci->lock, flags);
2712                 return value;
2713
2714         case CSR_BUSY_TIMEOUT:
2715                 value = reg_read(ohci, OHCI1394_ATRetries);
2716                 return (value >> 4) & 0x0ffff00f;
2717
2718         case CSR_PRIORITY_BUDGET:
2719                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2720                         (ohci->pri_req_max << 8);
2721
2722         default:
2723                 WARN_ON(1);
2724                 return 0;
2725         }
2726 }
2727
2728 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2729 {
2730         struct fw_ohci *ohci = fw_ohci(card);
2731         unsigned long flags;
2732
2733         switch (csr_offset) {
2734         case CSR_STATE_CLEAR:
2735                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2736                         reg_write(ohci, OHCI1394_LinkControlClear,
2737                                   OHCI1394_LinkControl_cycleMaster);
2738                         flush_writes(ohci);
2739                 }
2740                 if (value & CSR_STATE_BIT_ABDICATE)
2741                         ohci->csr_state_setclear_abdicate = false;
2742                 break;
2743
2744         case CSR_STATE_SET:
2745                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2746                         reg_write(ohci, OHCI1394_LinkControlSet,
2747                                   OHCI1394_LinkControl_cycleMaster);
2748                         flush_writes(ohci);
2749                 }
2750                 if (value & CSR_STATE_BIT_ABDICATE)
2751                         ohci->csr_state_setclear_abdicate = true;
2752                 break;
2753
2754         case CSR_NODE_IDS:
2755                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2756                 flush_writes(ohci);
2757                 break;
2758
2759         case CSR_CYCLE_TIME:
2760                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2761                 reg_write(ohci, OHCI1394_IntEventSet,
2762                           OHCI1394_cycleInconsistent);
2763                 flush_writes(ohci);
2764                 break;
2765
2766         case CSR_BUS_TIME:
2767                 spin_lock_irqsave(&ohci->lock, flags);
2768                 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2769                                  (value & ~0x7f);
2770                 spin_unlock_irqrestore(&ohci->lock, flags);
2771                 break;
2772
2773         case CSR_BUSY_TIMEOUT:
2774                 value = (value & 0xf) | ((value & 0xf) << 4) |
2775                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2776                 reg_write(ohci, OHCI1394_ATRetries, value);
2777                 flush_writes(ohci);
2778                 break;
2779
2780         case CSR_PRIORITY_BUDGET:
2781                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2782                 flush_writes(ohci);
2783                 break;
2784
2785         default:
2786                 WARN_ON(1);
2787                 break;
2788         }
2789 }
2790
2791 static void flush_iso_completions(struct iso_context *ctx)
2792 {
2793         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2794                               ctx->header_length, ctx->header,
2795                               ctx->base.callback_data);
2796         ctx->header_length = 0;
2797 }
2798
2799 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2800 {
2801         u32 *ctx_hdr;
2802
2803         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2804                 if (ctx->base.drop_overflow_headers)
2805                         return;
2806                 flush_iso_completions(ctx);
2807         }
2808
2809         ctx_hdr = ctx->header + ctx->header_length;
2810         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2811
2812         /*
2813          * The two iso header quadlets are byteswapped to little
2814          * endian by the controller, but we want to present them
2815          * as big endian for consistency with the bus endianness.
2816          */
2817         if (ctx->base.header_size > 0)
2818                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2819         if (ctx->base.header_size > 4)
2820                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2821         if (ctx->base.header_size > 8)
2822                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2823         ctx->header_length += ctx->base.header_size;
2824 }
2825
2826 static int handle_ir_packet_per_buffer(struct context *context,
2827                                        struct descriptor *d,
2828                                        struct descriptor *last)
2829 {
2830         struct iso_context *ctx =
2831                 container_of(context, struct iso_context, context);
2832         struct descriptor *pd;
2833         u32 buffer_dma;
2834
2835         for (pd = d; pd <= last; pd++)
2836                 if (pd->transfer_status)
2837                         break;
2838         if (pd > last)
2839                 /* Descriptor(s) not done yet, stop iteration */
2840                 return 0;
2841
2842         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2843                 d++;
2844                 buffer_dma = le32_to_cpu(d->data_address);
2845                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2846                                               buffer_dma & PAGE_MASK,
2847                                               buffer_dma & ~PAGE_MASK,
2848                                               le16_to_cpu(d->req_count),
2849                                               DMA_FROM_DEVICE);
2850         }
2851
2852         copy_iso_headers(ctx, (u32 *) (last + 1));
2853
2854         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2855                 flush_iso_completions(ctx);
2856
2857         return 1;
2858 }
2859
2860 /* d == last because each descriptor block is only a single descriptor. */
2861 static int handle_ir_buffer_fill(struct context *context,
2862                                  struct descriptor *d,
2863                                  struct descriptor *last)
2864 {
2865         struct iso_context *ctx =
2866                 container_of(context, struct iso_context, context);
2867         unsigned int req_count, res_count, completed;
2868         u32 buffer_dma;
2869
2870         req_count = le16_to_cpu(last->req_count);
2871         res_count = le16_to_cpu(READ_ONCE(last->res_count));
2872         completed = req_count - res_count;
2873         buffer_dma = le32_to_cpu(last->data_address);
2874
2875         if (completed > 0) {
2876                 ctx->mc_buffer_bus = buffer_dma;
2877                 ctx->mc_completed = completed;
2878         }
2879
2880         if (res_count != 0)
2881                 /* Descriptor(s) not done yet, stop iteration */
2882                 return 0;
2883
2884         dma_sync_single_range_for_cpu(context->ohci->card.device,
2885                                       buffer_dma & PAGE_MASK,
2886                                       buffer_dma & ~PAGE_MASK,
2887                                       completed, DMA_FROM_DEVICE);
2888
2889         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2890                 ctx->base.callback.mc(&ctx->base,
2891                                       buffer_dma + completed,
2892                                       ctx->base.callback_data);
2893                 ctx->mc_completed = 0;
2894         }
2895
2896         return 1;
2897 }
2898
2899 static void flush_ir_buffer_fill(struct iso_context *ctx)
2900 {
2901         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2902                                       ctx->mc_buffer_bus & PAGE_MASK,
2903                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2904                                       ctx->mc_completed, DMA_FROM_DEVICE);
2905
2906         ctx->base.callback.mc(&ctx->base,
2907                               ctx->mc_buffer_bus + ctx->mc_completed,
2908                               ctx->base.callback_data);
2909         ctx->mc_completed = 0;
2910 }
2911
2912 static inline void sync_it_packet_for_cpu(struct context *context,
2913                                           struct descriptor *pd)
2914 {
2915         __le16 control;
2916         u32 buffer_dma;
2917
2918         /* only packets beginning with OUTPUT_MORE* have data buffers */
2919         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2920                 return;
2921
2922         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2923         pd += 2;
2924
2925         /*
2926          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2927          * data buffer is in the context program's coherent page and must not
2928          * be synced.
2929          */
2930         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2931             (context->current_bus          & PAGE_MASK)) {
2932                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2933                         return;
2934                 pd++;
2935         }
2936
2937         do {
2938                 buffer_dma = le32_to_cpu(pd->data_address);
2939                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2940                                               buffer_dma & PAGE_MASK,
2941                                               buffer_dma & ~PAGE_MASK,
2942                                               le16_to_cpu(pd->req_count),
2943                                               DMA_TO_DEVICE);
2944                 control = pd->control;
2945                 pd++;
2946         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2947 }
2948
2949 static int handle_it_packet(struct context *context,
2950                             struct descriptor *d,
2951                             struct descriptor *last)
2952 {
2953         struct iso_context *ctx =
2954                 container_of(context, struct iso_context, context);
2955         struct descriptor *pd;
2956         __be32 *ctx_hdr;
2957
2958         for (pd = d; pd <= last; pd++)
2959                 if (pd->transfer_status)
2960                         break;
2961         if (pd > last)
2962                 /* Descriptor(s) not done yet, stop iteration */
2963                 return 0;
2964
2965         sync_it_packet_for_cpu(context, d);
2966
2967         if (ctx->header_length + 4 > PAGE_SIZE) {
2968                 if (ctx->base.drop_overflow_headers)
2969                         return 1;
2970                 flush_iso_completions(ctx);
2971         }
2972
2973         ctx_hdr = ctx->header + ctx->header_length;
2974         ctx->last_timestamp = le16_to_cpu(last->res_count);
2975         /* Present this value as big-endian to match the receive code */
2976         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2977                                le16_to_cpu(pd->res_count));
2978         ctx->header_length += 4;
2979
2980         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2981                 flush_iso_completions(ctx);
2982
2983         return 1;
2984 }
2985
2986 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2987 {
2988         u32 hi = channels >> 32, lo = channels;
2989
2990         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2991         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2992         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2993         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2994         mmiowb();
2995         ohci->mc_channels = channels;
2996 }
2997
2998 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2999                                 int type, int channel, size_t header_size)
3000 {
3001         struct fw_ohci *ohci = fw_ohci(card);
3002         struct iso_context *ctx;
3003         descriptor_callback_t callback;
3004         u64 *channels;
3005         u32 *mask, regs;
3006         int index, ret = -EBUSY;
3007
3008         spin_lock_irq(&ohci->lock);
3009
3010         switch (type) {
3011         case FW_ISO_CONTEXT_TRANSMIT:
3012                 mask     = &ohci->it_context_mask;
3013                 callback = handle_it_packet;
3014                 index    = ffs(*mask) - 1;
3015                 if (index >= 0) {
3016                         *mask &= ~(1 << index);
3017                         regs = OHCI1394_IsoXmitContextBase(index);
3018                         ctx  = &ohci->it_context_list[index];
3019                 }
3020                 break;
3021
3022         case FW_ISO_CONTEXT_RECEIVE:
3023                 channels = &ohci->ir_context_channels;
3024                 mask     = &ohci->ir_context_mask;
3025                 callback = handle_ir_packet_per_buffer;
3026                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
3027                 if (index >= 0) {
3028                         *channels &= ~(1ULL << channel);
3029                         *mask     &= ~(1 << index);
3030                         regs = OHCI1394_IsoRcvContextBase(index);
3031                         ctx  = &ohci->ir_context_list[index];
3032                 }
3033                 break;
3034
3035         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3036                 mask     = &ohci->ir_context_mask;
3037                 callback = handle_ir_buffer_fill;
3038                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
3039                 if (index >= 0) {
3040                         ohci->mc_allocated = true;
3041                         *mask &= ~(1 << index);
3042                         regs = OHCI1394_IsoRcvContextBase(index);
3043                         ctx  = &ohci->ir_context_list[index];
3044                 }
3045                 break;
3046
3047         default:
3048                 index = -1;
3049                 ret = -ENOSYS;
3050         }
3051
3052         spin_unlock_irq(&ohci->lock);
3053
3054         if (index < 0)
3055                 return ERR_PTR(ret);
3056
3057         memset(ctx, 0, sizeof(*ctx));
3058         ctx->header_length = 0;
3059         ctx->header = (void *) __get_free_page(GFP_KERNEL);
3060         if (ctx->header == NULL) {
3061                 ret = -ENOMEM;
3062                 goto out;
3063         }
3064         ret = context_init(&ctx->context, ohci, regs, callback);
3065         if (ret < 0)
3066                 goto out_with_header;
3067
3068         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3069                 set_multichannel_mask(ohci, 0);
3070                 ctx->mc_completed = 0;
3071         }
3072
3073         return &ctx->base;
3074
3075  out_with_header:
3076         free_page((unsigned long)ctx->header);
3077  out:
3078         spin_lock_irq(&ohci->lock);
3079
3080         switch (type) {
3081         case FW_ISO_CONTEXT_RECEIVE:
3082                 *channels |= 1ULL << channel;
3083                 break;
3084
3085         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3086                 ohci->mc_allocated = false;
3087                 break;
3088         }
3089         *mask |= 1 << index;
3090
3091         spin_unlock_irq(&ohci->lock);
3092
3093         return ERR_PTR(ret);
3094 }
3095
3096 static int ohci_start_iso(struct fw_iso_context *base,
3097                           s32 cycle, u32 sync, u32 tags)
3098 {
3099         struct iso_context *ctx = container_of(base, struct iso_context, base);
3100         struct fw_ohci *ohci = ctx->context.ohci;
3101         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3102         int index;
3103
3104         /* the controller cannot start without any queued packets */
3105         if (ctx->context.last->branch_address == 0)
3106                 return -ENODATA;
3107
3108         switch (ctx->base.type) {
3109         case FW_ISO_CONTEXT_TRANSMIT:
3110                 index = ctx - ohci->it_context_list;
3111                 match = 0;
3112                 if (cycle >= 0)
3113                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3114                                 (cycle & 0x7fff) << 16;
3115
3116                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3117                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3118                 context_run(&ctx->context, match);
3119                 break;
3120
3121         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3122                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3123                 /* fall through */
3124         case FW_ISO_CONTEXT_RECEIVE:
3125                 index = ctx - ohci->ir_context_list;
3126                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3127                 if (cycle >= 0) {
3128                         match |= (cycle & 0x07fff) << 12;
3129                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3130                 }
3131
3132                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3133                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3134                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3135                 context_run(&ctx->context, control);
3136
3137                 ctx->sync = sync;
3138                 ctx->tags = tags;
3139
3140                 break;
3141         }
3142
3143         return 0;
3144 }
3145
3146 static int ohci_stop_iso(struct fw_iso_context *base)
3147 {
3148         struct fw_ohci *ohci = fw_ohci(base->card);
3149         struct iso_context *ctx = container_of(base, struct iso_context, base);
3150         int index;
3151
3152         switch (ctx->base.type) {
3153         case FW_ISO_CONTEXT_TRANSMIT:
3154                 index = ctx - ohci->it_context_list;
3155                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3156                 break;
3157
3158         case FW_ISO_CONTEXT_RECEIVE:
3159         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3160                 index = ctx - ohci->ir_context_list;
3161                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3162                 break;
3163         }
3164         flush_writes(ohci);
3165         context_stop(&ctx->context);
3166         tasklet_kill(&ctx->context.tasklet);
3167
3168         return 0;
3169 }
3170
3171 static void ohci_free_iso_context(struct fw_iso_context *base)
3172 {
3173         struct fw_ohci *ohci = fw_ohci(base->card);
3174         struct iso_context *ctx = container_of(base, struct iso_context, base);
3175         unsigned long flags;
3176         int index;
3177
3178         ohci_stop_iso(base);
3179         context_release(&ctx->context);
3180         free_page((unsigned long)ctx->header);
3181
3182         spin_lock_irqsave(&ohci->lock, flags);
3183
3184         switch (base->type) {
3185         case FW_ISO_CONTEXT_TRANSMIT:
3186                 index = ctx - ohci->it_context_list;
3187                 ohci->it_context_mask |= 1 << index;
3188                 break;
3189
3190         case FW_ISO_CONTEXT_RECEIVE:
3191                 index = ctx - ohci->ir_context_list;
3192                 ohci->ir_context_mask |= 1 << index;
3193                 ohci->ir_context_channels |= 1ULL << base->channel;
3194                 break;
3195
3196         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3197                 index = ctx - ohci->ir_context_list;
3198                 ohci->ir_context_mask |= 1 << index;
3199                 ohci->ir_context_channels |= ohci->mc_channels;
3200                 ohci->mc_channels = 0;
3201                 ohci->mc_allocated = false;
3202                 break;
3203         }
3204
3205         spin_unlock_irqrestore(&ohci->lock, flags);
3206 }
3207
3208 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3209 {
3210         struct fw_ohci *ohci = fw_ohci(base->card);
3211         unsigned long flags;
3212         int ret;
3213
3214         switch (base->type) {
3215         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3216
3217                 spin_lock_irqsave(&ohci->lock, flags);
3218
3219                 /* Don't allow multichannel to grab other contexts' channels. */
3220                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3221                         *channels = ohci->ir_context_channels;
3222                         ret = -EBUSY;
3223                 } else {
3224                         set_multichannel_mask(ohci, *channels);
3225                         ret = 0;
3226                 }
3227
3228                 spin_unlock_irqrestore(&ohci->lock, flags);
3229
3230                 break;
3231         default:
3232                 ret = -EINVAL;
3233         }
3234
3235         return ret;
3236 }
3237
3238 #ifdef CONFIG_PM
3239 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3240 {
3241         int i;
3242         struct iso_context *ctx;
3243
3244         for (i = 0 ; i < ohci->n_ir ; i++) {
3245                 ctx = &ohci->ir_context_list[i];
3246                 if (ctx->context.running)
3247                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3248         }
3249
3250         for (i = 0 ; i < ohci->n_it ; i++) {
3251                 ctx = &ohci->it_context_list[i];
3252                 if (ctx->context.running)
3253                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3254         }
3255 }
3256 #endif
3257
3258 static int queue_iso_transmit(struct iso_context *ctx,
3259                               struct fw_iso_packet *packet,
3260                               struct fw_iso_buffer *buffer,
3261                               unsigned long payload)
3262 {
3263         struct descriptor *d, *last, *pd;
3264         struct fw_iso_packet *p;
3265         __le32 *header;
3266         dma_addr_t d_bus, page_bus;
3267         u32 z, header_z, payload_z, irq;
3268         u32 payload_index, payload_end_index, next_page_index;
3269         int page, end_page, i, length, offset;
3270
3271         p = packet;
3272         payload_index = payload;
3273
3274         if (p->skip)
3275                 z = 1;
3276         else
3277                 z = 2;
3278         if (p->header_length > 0)
3279                 z++;
3280
3281         /* Determine the first page the payload isn't contained in. */
3282         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3283         if (p->payload_length > 0)
3284                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3285         else
3286                 payload_z = 0;
3287
3288         z += payload_z;
3289
3290         /* Get header size in number of descriptors. */
3291         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3292
3293         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3294         if (d == NULL)
3295                 return -ENOMEM;
3296
3297         if (!p->skip) {
3298                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3299                 d[0].req_count = cpu_to_le16(8);
3300                 /*
3301                  * Link the skip address to this descriptor itself.  This causes
3302                  * a context to skip a cycle whenever lost cycles or FIFO
3303                  * overruns occur, without dropping the data.  The application
3304                  * should then decide whether this is an error condition or not.
3305                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3306                  */
3307                 d[0].branch_address = cpu_to_le32(d_bus | z);
3308
3309                 header = (__le32 *) &d[1];
3310                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3311                                         IT_HEADER_TAG(p->tag) |
3312                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3313                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3314                                         IT_HEADER_SPEED(ctx->base.speed));
3315                 header[1] =
3316                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3317                                                           p->payload_length));
3318         }
3319
3320         if (p->header_length > 0) {
3321                 d[2].req_count    = cpu_to_le16(p->header_length);
3322                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3323                 memcpy(&d[z], p->header, p->header_length);
3324         }
3325
3326         pd = d + z - payload_z;
3327         payload_end_index = payload_index + p->payload_length;
3328         for (i = 0; i < payload_z; i++) {
3329                 page               = payload_index >> PAGE_SHIFT;
3330                 offset             = payload_index & ~PAGE_MASK;
3331                 next_page_index    = (page + 1) << PAGE_SHIFT;
3332                 length             =
3333                         min(next_page_index, payload_end_index) - payload_index;
3334                 pd[i].req_count    = cpu_to_le16(length);
3335
3336                 page_bus = page_private(buffer->pages[page]);
3337                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3338
3339                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3340                                                  page_bus, offset, length,
3341                                                  DMA_TO_DEVICE);
3342
3343                 payload_index += length;
3344         }
3345
3346         if (p->interrupt)
3347                 irq = DESCRIPTOR_IRQ_ALWAYS;
3348         else
3349                 irq = DESCRIPTOR_NO_IRQ;
3350
3351         last = z == 2 ? d : d + z - 1;
3352         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3353                                      DESCRIPTOR_STATUS |
3354                                      DESCRIPTOR_BRANCH_ALWAYS |
3355                                      irq);
3356
3357         context_append(&ctx->context, d, z, header_z);
3358
3359         return 0;
3360 }
3361
3362 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3363                                        struct fw_iso_packet *packet,
3364                                        struct fw_iso_buffer *buffer,
3365                                        unsigned long payload)
3366 {
3367         struct device *device = ctx->context.ohci->card.device;
3368         struct descriptor *d, *pd;
3369         dma_addr_t d_bus, page_bus;
3370         u32 z, header_z, rest;
3371         int i, j, length;
3372         int page, offset, packet_count, header_size, payload_per_buffer;
3373
3374         /*
3375          * The OHCI controller puts the isochronous header and trailer in the
3376          * buffer, so we need at least 8 bytes.
3377          */
3378         packet_count = packet->header_length / ctx->base.header_size;
3379         header_size  = max(ctx->base.header_size, (size_t)8);
3380
3381         /* Get header size in number of descriptors. */
3382         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3383         page     = payload >> PAGE_SHIFT;
3384         offset   = payload & ~PAGE_MASK;
3385         payload_per_buffer = packet->payload_length / packet_count;
3386
3387         for (i = 0; i < packet_count; i++) {
3388                 /* d points to the header descriptor */
3389                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3390                 d = context_get_descriptors(&ctx->context,
3391                                 z + header_z, &d_bus);
3392                 if (d == NULL)
3393                         return -ENOMEM;
3394
3395                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3396                                               DESCRIPTOR_INPUT_MORE);
3397                 if (packet->skip && i == 0)
3398                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3399                 d->req_count    = cpu_to_le16(header_size);
3400                 d->res_count    = d->req_count;
3401                 d->transfer_status = 0;
3402                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3403
3404                 rest = payload_per_buffer;
3405                 pd = d;
3406                 for (j = 1; j < z; j++) {
3407                         pd++;
3408                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3409                                                   DESCRIPTOR_INPUT_MORE);
3410
3411                         if (offset + rest < PAGE_SIZE)
3412                                 length = rest;
3413                         else
3414                                 length = PAGE_SIZE - offset;
3415                         pd->req_count = cpu_to_le16(length);
3416                         pd->res_count = pd->req_count;
3417                         pd->transfer_status = 0;
3418
3419                         page_bus = page_private(buffer->pages[page]);
3420                         pd->data_address = cpu_to_le32(page_bus + offset);
3421
3422                         dma_sync_single_range_for_device(device, page_bus,
3423                                                          offset, length,
3424                                                          DMA_FROM_DEVICE);
3425
3426                         offset = (offset + length) & ~PAGE_MASK;
3427                         rest -= length;
3428                         if (offset == 0)
3429                                 page++;
3430                 }
3431                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3432                                           DESCRIPTOR_INPUT_LAST |
3433                                           DESCRIPTOR_BRANCH_ALWAYS);
3434                 if (packet->interrupt && i == packet_count - 1)
3435                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3436
3437                 context_append(&ctx->context, d, z, header_z);
3438         }
3439
3440         return 0;
3441 }
3442
3443 static int queue_iso_buffer_fill(struct iso_context *ctx,
3444                                  struct fw_iso_packet *packet,
3445                                  struct fw_iso_buffer *buffer,
3446                                  unsigned long payload)
3447 {
3448         struct descriptor *d;
3449         dma_addr_t d_bus, page_bus;
3450         int page, offset, rest, z, i, length;
3451
3452         page   = payload >> PAGE_SHIFT;
3453         offset = payload & ~PAGE_MASK;
3454         rest   = packet->payload_length;
3455
3456         /* We need one descriptor for each page in the buffer. */
3457         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3458
3459         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3460                 return -EFAULT;
3461
3462         for (i = 0; i < z; i++) {
3463                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3464                 if (d == NULL)
3465                         return -ENOMEM;
3466
3467                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3468                                          DESCRIPTOR_BRANCH_ALWAYS);
3469                 if (packet->skip && i == 0)
3470                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3471                 if (packet->interrupt && i == z - 1)
3472                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3473
3474                 if (offset + rest < PAGE_SIZE)
3475                         length = rest;
3476                 else
3477                         length = PAGE_SIZE - offset;
3478                 d->req_count = cpu_to_le16(length);
3479                 d->res_count = d->req_count;
3480                 d->transfer_status = 0;
3481
3482                 page_bus = page_private(buffer->pages[page]);
3483                 d->data_address = cpu_to_le32(page_bus + offset);
3484
3485                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3486                                                  page_bus, offset, length,
3487                                                  DMA_FROM_DEVICE);
3488
3489                 rest -= length;
3490                 offset = 0;
3491                 page++;
3492
3493                 context_append(&ctx->context, d, 1, 0);
3494         }
3495
3496         return 0;
3497 }
3498
3499 static int ohci_queue_iso(struct fw_iso_context *base,
3500                           struct fw_iso_packet *packet,
3501                           struct fw_iso_buffer *buffer,
3502                           unsigned long payload)
3503 {
3504         struct iso_context *ctx = container_of(base, struct iso_context, base);
3505         unsigned long flags;
3506         int ret = -ENOSYS;
3507
3508         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3509         switch (base->type) {
3510         case FW_ISO_CONTEXT_TRANSMIT:
3511                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3512                 break;
3513         case FW_ISO_CONTEXT_RECEIVE:
3514                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3515                 break;
3516         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3517                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3518                 break;
3519         }
3520         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3521
3522         return ret;
3523 }
3524
3525 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3526 {
3527         struct context *ctx =
3528                         &container_of(base, struct iso_context, base)->context;
3529
3530         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3531 }
3532
3533 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3534 {
3535         struct iso_context *ctx = container_of(base, struct iso_context, base);
3536         int ret = 0;
3537
3538         tasklet_disable(&ctx->context.tasklet);
3539
3540         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3541                 context_tasklet((unsigned long)&ctx->context);
3542
3543                 switch (base->type) {
3544                 case FW_ISO_CONTEXT_TRANSMIT:
3545                 case FW_ISO_CONTEXT_RECEIVE:
3546                         if (ctx->header_length != 0)
3547                                 flush_iso_completions(ctx);
3548                         break;
3549                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3550                         if (ctx->mc_completed != 0)
3551                                 flush_ir_buffer_fill(ctx);
3552                         break;
3553                 default:
3554                         ret = -ENOSYS;
3555                 }
3556
3557                 clear_bit_unlock(0, &ctx->flushing_completions);
3558                 smp_mb__after_atomic();
3559         }
3560
3561         tasklet_enable(&ctx->context.tasklet);
3562
3563         return ret;
3564 }
3565
3566 static const struct fw_card_driver ohci_driver = {
3567         .enable                 = ohci_enable,
3568         .read_phy_reg           = ohci_read_phy_reg,
3569         .update_phy_reg         = ohci_update_phy_reg,
3570         .set_config_rom         = ohci_set_config_rom,
3571         .send_request           = ohci_send_request,
3572         .send_response          = ohci_send_response,
3573         .cancel_packet          = ohci_cancel_packet,
3574         .enable_phys_dma        = ohci_enable_phys_dma,
3575         .read_csr               = ohci_read_csr,
3576         .write_csr              = ohci_write_csr,
3577
3578         .allocate_iso_context   = ohci_allocate_iso_context,
3579         .free_iso_context       = ohci_free_iso_context,
3580         .set_iso_channels       = ohci_set_iso_channels,
3581         .queue_iso              = ohci_queue_iso,
3582         .flush_queue_iso        = ohci_flush_queue_iso,
3583         .flush_iso_completions  = ohci_flush_iso_completions,
3584         .start_iso              = ohci_start_iso,
3585         .stop_iso               = ohci_stop_iso,
3586 };
3587
3588 #ifdef CONFIG_PPC_PMAC
3589 static void pmac_ohci_on(struct pci_dev *dev)
3590 {
3591         if (machine_is(powermac)) {
3592                 struct device_node *ofn = pci_device_to_OF_node(dev);
3593
3594                 if (ofn) {
3595                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3596                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3597                 }
3598         }
3599 }
3600
3601 static void pmac_ohci_off(struct pci_dev *dev)
3602 {
3603         if (machine_is(powermac)) {
3604                 struct device_node *ofn = pci_device_to_OF_node(dev);
3605
3606                 if (ofn) {
3607                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3608                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3609                 }
3610         }
3611 }
3612 #else
3613 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3614 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3615 #endif /* CONFIG_PPC_PMAC */
3616
3617 static int pci_probe(struct pci_dev *dev,
3618                                const struct pci_device_id *ent)
3619 {
3620         struct fw_ohci *ohci;
3621         u32 bus_options, max_receive, link_speed, version;
3622         u64 guid;
3623         int i, err;
3624         size_t size;
3625
3626         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3627                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3628                 return -ENOSYS;
3629         }
3630
3631         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3632         if (ohci == NULL) {
3633                 err = -ENOMEM;
3634                 goto fail;
3635         }
3636
3637         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3638
3639         pmac_ohci_on(dev);
3640
3641         err = pci_enable_device(dev);
3642         if (err) {
3643                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3644                 goto fail_free;
3645         }
3646
3647         pci_set_master(dev);
3648         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3649         pci_set_drvdata(dev, ohci);
3650
3651         spin_lock_init(&ohci->lock);
3652         mutex_init(&ohci->phy_reg_mutex);
3653
3654         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3655
3656         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3657             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3658                 ohci_err(ohci, "invalid MMIO resource\n");
3659                 err = -ENXIO;
3660                 goto fail_disable;
3661         }
3662
3663         err = pci_request_region(dev, 0, ohci_driver_name);
3664         if (err) {
3665                 ohci_err(ohci, "MMIO resource unavailable\n");
3666                 goto fail_disable;
3667         }
3668
3669         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3670         if (ohci->registers == NULL) {
3671                 ohci_err(ohci, "failed to remap registers\n");
3672                 err = -ENXIO;
3673                 goto fail_iomem;
3674         }
3675
3676         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3677                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3678                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3679                      ohci_quirks[i].device == dev->device) &&
3680                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3681                      ohci_quirks[i].revision >= dev->revision)) {
3682                         ohci->quirks = ohci_quirks[i].flags;
3683                         break;
3684                 }
3685         if (param_quirks)
3686                 ohci->quirks = param_quirks;
3687
3688         if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev))
3689                 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ;
3690
3691         /*
3692          * Because dma_alloc_coherent() allocates at least one page,
3693          * we save space by using a common buffer for the AR request/
3694          * response descriptors and the self IDs buffer.
3695          */
3696         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3697         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3698         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3699                                                PAGE_SIZE,
3700                                                &ohci->misc_buffer_bus,
3701                                                GFP_KERNEL);
3702         if (!ohci->misc_buffer) {
3703                 err = -ENOMEM;
3704                 goto fail_iounmap;
3705         }
3706
3707         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3708                               OHCI1394_AsReqRcvContextControlSet);
3709         if (err < 0)
3710                 goto fail_misc_buf;
3711
3712         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3713                               OHCI1394_AsRspRcvContextControlSet);
3714         if (err < 0)
3715                 goto fail_arreq_ctx;
3716
3717         err = context_init(&ohci->at_request_ctx, ohci,
3718                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3719         if (err < 0)
3720                 goto fail_arrsp_ctx;
3721
3722         err = context_init(&ohci->at_response_ctx, ohci,
3723                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3724         if (err < 0)
3725                 goto fail_atreq_ctx;
3726
3727         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3728         ohci->ir_context_channels = ~0ULL;
3729         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3730         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3731         ohci->ir_context_mask = ohci->ir_context_support;
3732         ohci->n_ir = hweight32(ohci->ir_context_mask);
3733         size = sizeof(struct iso_context) * ohci->n_ir;
3734         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3735
3736         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3737         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3738         /* JMicron JMB38x often shows 0 at first read, just ignore it */
3739         if (!ohci->it_context_support) {
3740                 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3741                 ohci->it_context_support = 0xf;
3742         }
3743         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3744         ohci->it_context_mask = ohci->it_context_support;
3745         ohci->n_it = hweight32(ohci->it_context_mask);
3746         size = sizeof(struct iso_context) * ohci->n_it;
3747         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3748
3749         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3750                 err = -ENOMEM;
3751                 goto fail_contexts;
3752         }
3753
3754         ohci->self_id     = ohci->misc_buffer     + PAGE_SIZE/2;
3755         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3756
3757         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3758         max_receive = (bus_options >> 12) & 0xf;
3759         link_speed = bus_options & 0x7;
3760         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3761                 reg_read(ohci, OHCI1394_GUIDLo);
3762
3763         if (!(ohci->quirks & QUIRK_NO_MSI))
3764                 pci_enable_msi(dev);
3765         if (request_irq(dev->irq, irq_handler,
3766                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3767                         ohci_driver_name, ohci)) {
3768                 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3769                 err = -EIO;
3770                 goto fail_msi;
3771         }
3772
3773         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3774         if (err)
3775                 goto fail_irq;
3776
3777         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3778         ohci_notice(ohci,
3779                     "added OHCI v%x.%x device as card %d, "
3780                     "%d IR + %d IT contexts, quirks 0x%x%s\n",
3781                     version >> 16, version & 0xff, ohci->card.index,
3782                     ohci->n_ir, ohci->n_it, ohci->quirks,
3783                     reg_read(ohci, OHCI1394_PhyUpperBound) ?
3784                         ", physUB" : "");
3785
3786         return 0;
3787
3788  fail_irq:
3789         free_irq(dev->irq, ohci);
3790  fail_msi:
3791         pci_disable_msi(dev);
3792  fail_contexts:
3793         kfree(ohci->ir_context_list);
3794         kfree(ohci->it_context_list);
3795         context_release(&ohci->at_response_ctx);
3796  fail_atreq_ctx:
3797         context_release(&ohci->at_request_ctx);
3798  fail_arrsp_ctx:
3799         ar_context_release(&ohci->ar_response_ctx);
3800  fail_arreq_ctx:
3801         ar_context_release(&ohci->ar_request_ctx);
3802  fail_misc_buf:
3803         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3804                           ohci->misc_buffer, ohci->misc_buffer_bus);
3805  fail_iounmap:
3806         pci_iounmap(dev, ohci->registers);
3807  fail_iomem:
3808         pci_release_region(dev, 0);
3809  fail_disable:
3810         pci_disable_device(dev);
3811  fail_free:
3812         kfree(ohci);
3813         pmac_ohci_off(dev);
3814  fail:
3815         return err;
3816 }
3817
3818 static void pci_remove(struct pci_dev *dev)
3819 {
3820         struct fw_ohci *ohci = pci_get_drvdata(dev);
3821
3822         /*
3823          * If the removal is happening from the suspend state, LPS won't be
3824          * enabled and host registers (eg., IntMaskClear) won't be accessible.
3825          */
3826         if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3827                 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3828                 flush_writes(ohci);
3829         }
3830         cancel_work_sync(&ohci->bus_reset_work);
3831         fw_core_remove_card(&ohci->card);
3832
3833         /*
3834          * FIXME: Fail all pending packets here, now that the upper
3835          * layers can't queue any more.
3836          */
3837
3838         software_reset(ohci);
3839         free_irq(dev->irq, ohci);
3840
3841         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3842                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3843                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3844         if (ohci->config_rom)
3845                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3846                                   ohci->config_rom, ohci->config_rom_bus);
3847         ar_context_release(&ohci->ar_request_ctx);
3848         ar_context_release(&ohci->ar_response_ctx);
3849         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3850                           ohci->misc_buffer, ohci->misc_buffer_bus);
3851         context_release(&ohci->at_request_ctx);
3852         context_release(&ohci->at_response_ctx);
3853         kfree(ohci->it_context_list);
3854         kfree(ohci->ir_context_list);
3855         pci_disable_msi(dev);
3856         pci_iounmap(dev, ohci->registers);
3857         pci_release_region(dev, 0);
3858         pci_disable_device(dev);
3859         kfree(ohci);
3860         pmac_ohci_off(dev);
3861
3862         dev_notice(&dev->dev, "removed fw-ohci device\n");
3863 }
3864
3865 #ifdef CONFIG_PM
3866 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3867 {
3868         struct fw_ohci *ohci = pci_get_drvdata(dev);
3869         int err;
3870
3871         software_reset(ohci);
3872         err = pci_save_state(dev);
3873         if (err) {
3874                 ohci_err(ohci, "pci_save_state failed\n");
3875                 return err;
3876         }
3877         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3878         if (err)
3879                 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3880         pmac_ohci_off(dev);
3881
3882         return 0;
3883 }
3884
3885 static int pci_resume(struct pci_dev *dev)
3886 {
3887         struct fw_ohci *ohci = pci_get_drvdata(dev);
3888         int err;
3889
3890         pmac_ohci_on(dev);
3891         pci_set_power_state(dev, PCI_D0);
3892         pci_restore_state(dev);
3893         err = pci_enable_device(dev);
3894         if (err) {
3895                 ohci_err(ohci, "pci_enable_device failed\n");
3896                 return err;
3897         }
3898
3899         /* Some systems don't setup GUID register on resume from ram  */
3900         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3901                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3902                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3903                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3904         }
3905
3906         err = ohci_enable(&ohci->card, NULL, 0);
3907         if (err)
3908                 return err;
3909
3910         ohci_resume_iso_dma(ohci);
3911
3912         return 0;
3913 }
3914 #endif
3915
3916 static const struct pci_device_id pci_table[] = {
3917         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3918         { }
3919 };
3920
3921 MODULE_DEVICE_TABLE(pci, pci_table);
3922
3923 static struct pci_driver fw_ohci_pci_driver = {
3924         .name           = ohci_driver_name,
3925         .id_table       = pci_table,
3926         .probe          = pci_probe,
3927         .remove         = pci_remove,
3928 #ifdef CONFIG_PM
3929         .resume         = pci_resume,
3930         .suspend        = pci_suspend,
3931 #endif
3932 };
3933
3934 static int __init fw_ohci_init(void)
3935 {
3936         selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3937         if (!selfid_workqueue)
3938                 return -ENOMEM;
3939
3940         return pci_register_driver(&fw_ohci_pci_driver);
3941 }
3942
3943 static void __exit fw_ohci_cleanup(void)
3944 {
3945         pci_unregister_driver(&fw_ohci_pci_driver);
3946         destroy_workqueue(selfid_workqueue);
3947 }
3948
3949 module_init(fw_ohci_init);
3950 module_exit(fw_ohci_cleanup);
3951
3952 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3953 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3954 MODULE_LICENSE("GPL");
3955
3956 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3957 MODULE_ALIAS("ohci1394");