1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Versal memory controller driver
4 * Copyright (C) 2023 Advanced Micro Devices, Inc.
6 #include <linux/bitfield.h>
7 #include <linux/edac.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/sizes.h>
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
18 #include "edac_module.h"
20 /* Granularity of reported error in bytes */
21 #define XDDR_EDAC_ERR_GRAIN 1
23 #define XDDR_EDAC_MSG_SIZE 256
26 #define XDDR_PCSR_OFFSET 0xC
27 #define XDDR_ISR_OFFSET 0x14
28 #define XDDR_IRQ_EN_OFFSET 0x20
29 #define XDDR_IRQ1_EN_OFFSET 0x2C
30 #define XDDR_IRQ_DIS_OFFSET 0x24
31 #define XDDR_IRQ_CE_MASK GENMASK(18, 15)
32 #define XDDR_IRQ_UE_MASK GENMASK(14, 11)
34 #define XDDR_REG_CONFIG0_OFFSET 0x258
35 #define XDDR_REG_CONFIG0_BUS_WIDTH_MASK GENMASK(19, 18)
36 #define XDDR_REG_CONFIG0_NUM_CHANS_MASK BIT(17)
37 #define XDDR_REG_CONFIG0_NUM_RANKS_MASK GENMASK(15, 14)
38 #define XDDR_REG_CONFIG0_SIZE_MASK GENMASK(10, 8)
40 #define XDDR_REG_PINOUT_OFFSET 0x25C
41 #define XDDR_REG_PINOUT_ECC_EN_MASK GENMASK(7, 5)
43 #define ECCW0_FLIP_CTRL 0x109C
44 #define ECCW0_FLIP0_OFFSET 0x10A0
45 #define ECCW1_FLIP_CTRL 0x10AC
46 #define ECCW1_FLIP0_OFFSET 0x10B0
47 #define ECCR0_CERR_STAT_OFFSET 0x10BC
48 #define ECCR0_CE_ADDR_LO_OFFSET 0x10C0
49 #define ECCR0_CE_ADDR_HI_OFFSET 0x10C4
50 #define ECCR0_CE_DATA_LO_OFFSET 0x10C8
51 #define ECCR0_CE_DATA_HI_OFFSET 0x10CC
52 #define ECCR0_CE_DATA_PAR_OFFSET 0x10D0
54 #define ECCR0_UERR_STAT_OFFSET 0x10D4
55 #define ECCR0_UE_ADDR_LO_OFFSET 0x10D8
56 #define ECCR0_UE_ADDR_HI_OFFSET 0x10DC
57 #define ECCR0_UE_DATA_LO_OFFSET 0x10E0
58 #define ECCR0_UE_DATA_HI_OFFSET 0x10E4
59 #define ECCR0_UE_DATA_PAR_OFFSET 0x10E8
61 #define ECCR1_CERR_STAT_OFFSET 0x10F4
62 #define ECCR1_CE_ADDR_LO_OFFSET 0x10F8
63 #define ECCR1_CE_ADDR_HI_OFFSET 0x10FC
64 #define ECCR1_CE_DATA_LO_OFFSET 0x1100
65 #define ECCR1_CE_DATA_HI_OFFSET 0x110C
66 #define ECCR1_CE_DATA_PAR_OFFSET 0x1108
68 #define ECCR1_UERR_STAT_OFFSET 0x110C
69 #define ECCR1_UE_ADDR_LO_OFFSET 0x1110
70 #define ECCR1_UE_ADDR_HI_OFFSET 0x1114
71 #define ECCR1_UE_DATA_LO_OFFSET 0x1118
72 #define ECCR1_UE_DATA_HI_OFFSET 0x111C
73 #define ECCR1_UE_DATA_PAR_OFFSET 0x1120
75 #define XDDR_NOC_REG_ADEC4_OFFSET 0x44
76 #define RANK_1_MASK GENMASK(11, 6)
77 #define LRANK_0_MASK GENMASK(17, 12)
78 #define LRANK_1_MASK GENMASK(23, 18)
79 #define MASK_24 GENMASK(29, 24)
81 #define XDDR_NOC_REG_ADEC5_OFFSET 0x48
82 #define XDDR_NOC_REG_ADEC6_OFFSET 0x4C
83 #define XDDR_NOC_REG_ADEC7_OFFSET 0x50
84 #define XDDR_NOC_REG_ADEC8_OFFSET 0x54
85 #define XDDR_NOC_REG_ADEC9_OFFSET 0x58
86 #define XDDR_NOC_REG_ADEC10_OFFSET 0x5C
88 #define XDDR_NOC_REG_ADEC11_OFFSET 0x60
89 #define MASK_0 GENMASK(5, 0)
90 #define GRP_0_MASK GENMASK(11, 6)
91 #define GRP_1_MASK GENMASK(17, 12)
92 #define CH_0_MASK GENMASK(23, 18)
94 #define XDDR_NOC_REG_ADEC12_OFFSET 0x71C
95 #define XDDR_NOC_REG_ADEC13_OFFSET 0x720
97 #define XDDR_NOC_REG_ADEC14_OFFSET 0x724
98 #define XDDR_NOC_ROW_MATCH_MASK GENMASK(17, 0)
99 #define XDDR_NOC_COL_MATCH_MASK GENMASK(27, 18)
100 #define XDDR_NOC_BANK_MATCH_MASK GENMASK(29, 28)
101 #define XDDR_NOC_GRP_MATCH_MASK GENMASK(31, 30)
103 #define XDDR_NOC_REG_ADEC15_OFFSET 0x728
104 #define XDDR_NOC_RANK_MATCH_MASK GENMASK(1, 0)
105 #define XDDR_NOC_LRANK_MATCH_MASK GENMASK(4, 2)
106 #define XDDR_NOC_CH_MATCH_MASK BIT(5)
107 #define XDDR_NOC_MOD_SEL_MASK BIT(6)
108 #define XDDR_NOC_MATCH_EN_MASK BIT(8)
110 #define ECCR_UE_CE_ADDR_HI_ROW_MASK GENMASK(7, 0)
112 #define XDDR_EDAC_NR_CSROWS 1
113 #define XDDR_EDAC_NR_CHANS 1
115 #define XDDR_BUS_WIDTH_64 0
116 #define XDDR_BUS_WIDTH_32 1
117 #define XDDR_BUS_WIDTH_16 2
119 #define ECC_CEPOISON_MASK 0x1
120 #define ECC_UEPOISON_MASK 0x3
122 #define XDDR_MAX_ROW_CNT 18
123 #define XDDR_MAX_COL_CNT 10
124 #define XDDR_MAX_RANK_CNT 2
125 #define XDDR_MAX_LRANK_CNT 3
126 #define XDDR_MAX_BANK_CNT 2
127 #define XDDR_MAX_GRP_CNT 2
130 * Config and system registers are usually locked. This is the
131 * code which unlocks them in order to accept writes. See
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
135 #define PCSR_UNLOCK_VAL 0xF9E8D7C6
136 #define XDDR_ERR_TYPE_CE 0
137 #define XDDR_ERR_TYPE_UE 1
139 #define XILINX_DRAM_SIZE_4G 0
140 #define XILINX_DRAM_SIZE_6G 1
141 #define XILINX_DRAM_SIZE_8G 2
142 #define XILINX_DRAM_SIZE_12G 3
143 #define XILINX_DRAM_SIZE_16G 4
144 #define XILINX_DRAM_SIZE_32G 5
147 * struct ecc_error_info - ECC error log information.
148 * @burstpos: Burst position.
149 * @lrank: Logical Rank number.
150 * @rank: Rank number.
151 * @group: Group number.
152 * @bank: Bank number.
153 * @col: Column number.
155 * @rowhi: Row number higher bits.
156 * @i: ECC error info.
158 union ecc_error_info {
193 * struct ecc_status - ECC status information to report.
194 * @ceinfo: Correctable error log information.
195 * @ueinfo: Uncorrectable error log information.
196 * @channel: Channel number.
197 * @error_type: Error type information.
200 union ecc_error_info ceinfo[2];
201 union ecc_error_info ueinfo[2];
207 * struct edac_priv - DDR memory controller private instance data.
208 * @ddrmc_baseaddr: Base address of the DDR controller.
209 * @ddrmc_noc_baseaddr: Base address of the DDRMC NOC.
210 * @message: Buffer for framing the event specific info.
211 * @mc_id: Memory controller ID.
212 * @ce_cnt: Correctable error count.
213 * @ue_cnt: UnCorrectable error count.
214 * @stat: ECC status information.
215 * @lrank_bit: Bit shifts for lrank bit.
216 * @rank_bit: Bit shifts for rank bit.
217 * @row_bit: Bit shifts for row bit.
218 * @col_bit: Bit shifts for column bit.
219 * @bank_bit: Bit shifts for bank bit.
220 * @grp_bit: Bit shifts for group bit.
221 * @ch_bit: Bit shifts for channel bit.
222 * @err_inject_addr: Data poison address.
223 * @debugfs: Debugfs handle.
226 void __iomem *ddrmc_baseaddr;
227 void __iomem *ddrmc_noc_baseaddr;
228 char message[XDDR_EDAC_MSG_SIZE];
232 struct ecc_status stat;
240 #ifdef CONFIG_EDAC_DEBUG
242 struct dentry *debugfs;
246 static void get_ce_error_info(struct edac_priv *priv)
248 void __iomem *ddrmc_base;
249 struct ecc_status *p;
253 ddrmc_base = priv->ddrmc_baseaddr;
256 p->error_type = XDDR_ERR_TYPE_CE;
257 regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET);
258 reghi = regval & ECCR_UE_CE_ADDR_HI_ROW_MASK;
259 p->ceinfo[0].i = regval | reghi << 32;
260 regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET);
262 edac_dbg(2, "ERR DATA: 0x%08X%08X ERR DATA PARITY: 0x%08X\n",
263 readl(ddrmc_base + ECCR0_CE_DATA_LO_OFFSET),
264 readl(ddrmc_base + ECCR0_CE_DATA_HI_OFFSET),
265 readl(ddrmc_base + ECCR0_CE_DATA_PAR_OFFSET));
267 regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET);
268 reghi = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET);
269 p->ceinfo[1].i = regval | reghi << 32;
270 regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET);
272 edac_dbg(2, "ERR DATA: 0x%08X%08X ERR DATA PARITY: 0x%08X\n",
273 readl(ddrmc_base + ECCR1_CE_DATA_LO_OFFSET),
274 readl(ddrmc_base + ECCR1_CE_DATA_HI_OFFSET),
275 readl(ddrmc_base + ECCR1_CE_DATA_PAR_OFFSET));
278 static void get_ue_error_info(struct edac_priv *priv)
280 void __iomem *ddrmc_base;
281 struct ecc_status *p;
285 ddrmc_base = priv->ddrmc_baseaddr;
288 p->error_type = XDDR_ERR_TYPE_UE;
289 regval = readl(ddrmc_base + ECCR0_UE_ADDR_LO_OFFSET);
290 reghi = readl(ddrmc_base + ECCR0_UE_ADDR_HI_OFFSET);
292 p->ueinfo[0].i = regval | reghi << 32;
293 regval = readl(ddrmc_base + ECCR0_UE_ADDR_HI_OFFSET);
295 edac_dbg(2, "ERR DATA: 0x%08X%08X ERR DATA PARITY: 0x%08X\n",
296 readl(ddrmc_base + ECCR0_UE_DATA_LO_OFFSET),
297 readl(ddrmc_base + ECCR0_UE_DATA_HI_OFFSET),
298 readl(ddrmc_base + ECCR0_UE_DATA_PAR_OFFSET));
300 regval = readl(ddrmc_base + ECCR1_UE_ADDR_LO_OFFSET);
301 reghi = readl(ddrmc_base + ECCR1_UE_ADDR_HI_OFFSET);
302 p->ueinfo[1].i = regval | reghi << 32;
304 edac_dbg(2, "ERR DATA: 0x%08X%08X ERR DATA PARITY: 0x%08X\n",
305 readl(ddrmc_base + ECCR1_UE_DATA_LO_OFFSET),
306 readl(ddrmc_base + ECCR1_UE_DATA_HI_OFFSET),
307 readl(ddrmc_base + ECCR1_UE_DATA_PAR_OFFSET));
310 static bool get_error_info(struct edac_priv *priv)
312 u32 eccr0_ceval, eccr1_ceval, eccr0_ueval, eccr1_ueval;
313 void __iomem *ddrmc_base;
314 struct ecc_status *p;
316 ddrmc_base = priv->ddrmc_baseaddr;
319 eccr0_ceval = readl(ddrmc_base + ECCR0_CERR_STAT_OFFSET);
320 eccr1_ceval = readl(ddrmc_base + ECCR1_CERR_STAT_OFFSET);
321 eccr0_ueval = readl(ddrmc_base + ECCR0_UERR_STAT_OFFSET);
322 eccr1_ueval = readl(ddrmc_base + ECCR1_UERR_STAT_OFFSET);
324 if (!eccr0_ceval && !eccr1_ceval && !eccr0_ueval && !eccr1_ueval)
331 if (eccr0_ceval || eccr1_ceval)
332 get_ce_error_info(priv);
334 if (eccr0_ueval || eccr1_ueval) {
339 get_ue_error_info(priv);
342 /* Unlock the PCSR registers */
343 writel(PCSR_UNLOCK_VAL, ddrmc_base + XDDR_PCSR_OFFSET);
345 writel(0, ddrmc_base + ECCR0_CERR_STAT_OFFSET);
346 writel(0, ddrmc_base + ECCR1_CERR_STAT_OFFSET);
347 writel(0, ddrmc_base + ECCR0_UERR_STAT_OFFSET);
348 writel(0, ddrmc_base + ECCR1_UERR_STAT_OFFSET);
350 /* Lock the PCSR registers */
351 writel(1, ddrmc_base + XDDR_PCSR_OFFSET);
357 * convert_to_physical - Convert to physical address.
358 * @priv: DDR memory controller private instance data.
359 * @pinf: ECC error info structure.
361 * Return: Physical address of the DDR memory.
363 static unsigned long convert_to_physical(struct edac_priv *priv, union ecc_error_info pinf)
365 unsigned long err_addr = 0;
369 row = pinf.rowhi << 10 | pinf.row;
370 for (index = 0; index < XDDR_MAX_ROW_CNT; index++) {
371 err_addr |= (row & BIT(0)) << priv->row_bit[index];
375 for (index = 0; index < XDDR_MAX_COL_CNT; index++) {
376 err_addr |= (pinf.col & BIT(0)) << priv->col_bit[index];
380 for (index = 0; index < XDDR_MAX_BANK_CNT; index++) {
381 err_addr |= (pinf.bank & BIT(0)) << priv->bank_bit[index];
385 for (index = 0; index < XDDR_MAX_GRP_CNT; index++) {
386 err_addr |= (pinf.group & BIT(0)) << priv->grp_bit[index];
390 for (index = 0; index < XDDR_MAX_RANK_CNT; index++) {
391 err_addr |= (pinf.rank & BIT(0)) << priv->rank_bit[index];
395 for (index = 0; index < XDDR_MAX_LRANK_CNT; index++) {
396 err_addr |= (pinf.lrank & BIT(0)) << priv->lrank_bit[index];
400 err_addr |= (priv->stat.channel & BIT(0)) << priv->ch_bit;
406 * handle_error - Handle Correctable and Uncorrectable errors.
407 * @mci: EDAC memory controller instance.
408 * @stat: ECC status structure.
410 * Handles ECC correctable and uncorrectable errors.
412 static void handle_error(struct mem_ctl_info *mci, struct ecc_status *stat)
414 struct edac_priv *priv = mci->pvt_info;
415 union ecc_error_info pinf;
417 if (stat->error_type == XDDR_ERR_TYPE_CE) {
419 pinf = stat->ceinfo[stat->channel];
420 snprintf(priv->message, XDDR_EDAC_MSG_SIZE,
421 "Error type:%s MC ID: %d Addr at %lx Burst Pos: %d\n",
423 convert_to_physical(priv, pinf), pinf.burstpos);
425 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
426 priv->ce_cnt, 0, 0, 0, 0, 0, -1,
430 if (stat->error_type == XDDR_ERR_TYPE_UE) {
432 pinf = stat->ueinfo[stat->channel];
433 snprintf(priv->message, XDDR_EDAC_MSG_SIZE,
434 "Error type:%s MC ID: %d Addr at %lx Burst Pos: %d\n",
436 convert_to_physical(priv, pinf), pinf.burstpos);
438 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
439 priv->ue_cnt, 0, 0, 0, 0, 0, -1,
443 memset(stat, 0, sizeof(*stat));
447 * err_callback - Handle Correctable and Uncorrectable errors.
448 * @payload: payload data.
449 * @data: mci controller data.
451 * Handles ECC correctable and uncorrectable errors.
453 static void err_callback(const u32 *payload, void *data)
455 struct mem_ctl_info *mci = (struct mem_ctl_info *)data;
456 struct edac_priv *priv;
457 struct ecc_status *p;
460 priv = mci->pvt_info;
463 regval = readl(priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);
465 if (payload[EVENT] == XPM_EVENT_ERROR_MASK_DDRMC_CR)
466 p->error_type = XDDR_ERR_TYPE_CE;
467 if (payload[EVENT] == XPM_EVENT_ERROR_MASK_DDRMC_NCR)
468 p->error_type = XDDR_ERR_TYPE_UE;
470 if (get_error_info(priv))
473 handle_error(mci, &priv->stat);
475 /* Unlock the PCSR registers */
476 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
479 writel(regval, priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);
481 /* Lock the PCSR registers */
482 writel(1, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
483 edac_dbg(3, "Total error count CE %d UE %d\n",
484 priv->ce_cnt, priv->ue_cnt);
488 * get_dwidth - Return the controller memory width.
489 * @base: DDR memory controller base address.
491 * Get the EDAC device type width appropriate for the controller
494 * Return: a device type width enumeration.
496 static enum dev_type get_dwidth(const void __iomem *base)
502 regval = readl(base + XDDR_REG_CONFIG0_OFFSET);
503 width = FIELD_GET(XDDR_REG_CONFIG0_BUS_WIDTH_MASK, regval);
506 case XDDR_BUS_WIDTH_16:
509 case XDDR_BUS_WIDTH_32:
512 case XDDR_BUS_WIDTH_64:
523 * get_ecc_state - Return the controller ECC enable/disable status.
524 * @base: DDR memory controller base address.
526 * Get the ECC enable/disable status for the controller.
528 * Return: a ECC status boolean i.e true/false - enabled/disabled.
530 static bool get_ecc_state(void __iomem *base)
535 dt = get_dwidth(base);
536 if (dt == DEV_UNKNOWN)
539 ecctype = readl(base + XDDR_REG_PINOUT_OFFSET);
540 ecctype &= XDDR_REG_PINOUT_ECC_EN_MASK;
546 * get_memsize - Get the size of the attached memory device.
547 * @priv: DDR memory controller private instance data.
549 * Return: the memory size in bytes.
551 static u64 get_memsize(struct edac_priv *priv)
556 regval = readl(priv->ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);
557 regval = FIELD_GET(XDDR_REG_CONFIG0_SIZE_MASK, regval);
560 case XILINX_DRAM_SIZE_4G:
562 case XILINX_DRAM_SIZE_6G:
564 case XILINX_DRAM_SIZE_8G:
566 case XILINX_DRAM_SIZE_12G:
568 case XILINX_DRAM_SIZE_16G:
570 case XILINX_DRAM_SIZE_32G:
572 /* Invalid configuration */
582 * init_csrows - Initialize the csrow data.
583 * @mci: EDAC memory controller instance.
585 * Initialize the chip select rows associated with the EDAC memory
586 * controller instance.
588 static void init_csrows(struct mem_ctl_info *mci)
590 struct edac_priv *priv = mci->pvt_info;
591 struct csrow_info *csi;
592 struct dimm_info *dimm;
597 size = get_memsize(priv);
598 for (row = 0; row < mci->nr_csrows; row++) {
599 csi = mci->csrows[row];
600 for (ch = 0; ch < csi->nr_channels; ch++) {
601 dimm = csi->channels[ch]->dimm;
602 dimm->edac_mode = EDAC_SECDED;
603 dimm->mtype = MEM_DDR4;
604 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
605 dimm->grain = XDDR_EDAC_ERR_GRAIN;
606 dimm->dtype = get_dwidth(priv->ddrmc_baseaddr);
612 * mc_init - Initialize one driver instance.
613 * @mci: EDAC memory controller instance.
614 * @pdev: platform device.
616 * Perform initialization of the EDAC memory controller instance and
617 * related driver-private data associated with the memory controller the
618 * instance is bound to.
620 static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
622 mci->pdev = &pdev->dev;
623 platform_set_drvdata(pdev, mci);
625 /* Initialize controller capabilities and configuration */
626 mci->mtype_cap = MEM_FLAG_DDR4;
627 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
628 mci->scrub_cap = SCRUB_HW_SRC;
629 mci->scrub_mode = SCRUB_NONE;
631 mci->edac_cap = EDAC_FLAG_SECDED;
632 mci->ctl_name = "xlnx_ddr_controller";
633 mci->dev_name = dev_name(&pdev->dev);
634 mci->mod_name = "xlnx_edac";
636 edac_op_state = EDAC_OPSTATE_INT;
641 static void enable_intr(struct edac_priv *priv)
643 /* Unlock the PCSR registers */
644 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
646 /* Enable UE and CE Interrupts to support the interrupt case */
647 writel(XDDR_IRQ_CE_MASK | XDDR_IRQ_UE_MASK,
648 priv->ddrmc_baseaddr + XDDR_IRQ_EN_OFFSET);
650 writel(XDDR_IRQ_UE_MASK,
651 priv->ddrmc_baseaddr + XDDR_IRQ1_EN_OFFSET);
652 /* Lock the PCSR registers */
653 writel(1, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
656 static void disable_intr(struct edac_priv *priv)
658 /* Unlock the PCSR registers */
659 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
661 /* Disable UE/CE Interrupts */
662 writel(XDDR_IRQ_CE_MASK | XDDR_IRQ_UE_MASK,
663 priv->ddrmc_baseaddr + XDDR_IRQ_DIS_OFFSET);
665 /* Lock the PCSR registers */
666 writel(1, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
669 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
671 #ifdef CONFIG_EDAC_DEBUG
673 * poison_setup - Update poison registers.
674 * @priv: DDR memory controller private instance data.
676 * Update poison registers as per DDR mapping upon write of the address
677 * location the fault is injected.
680 static void poison_setup(struct edac_priv *priv)
682 u32 col = 0, row = 0, bank = 0, grp = 0, rank = 0, lrank = 0, ch = 0;
685 for (index = 0; index < XDDR_MAX_ROW_CNT; index++) {
686 row |= (((priv->err_inject_addr >> priv->row_bit[index]) &
690 for (index = 0; index < XDDR_MAX_COL_CNT; index++) {
691 col |= (((priv->err_inject_addr >> priv->col_bit[index]) &
695 for (index = 0; index < XDDR_MAX_BANK_CNT; index++) {
696 bank |= (((priv->err_inject_addr >> priv->bank_bit[index]) &
700 for (index = 0; index < XDDR_MAX_GRP_CNT; index++) {
701 grp |= (((priv->err_inject_addr >> priv->grp_bit[index]) &
705 for (index = 0; index < XDDR_MAX_RANK_CNT; index++) {
706 rank |= (((priv->err_inject_addr >> priv->rank_bit[index]) &
710 for (index = 0; index < XDDR_MAX_LRANK_CNT; index++) {
711 lrank |= (((priv->err_inject_addr >> priv->lrank_bit[index]) &
715 ch = (priv->err_inject_addr >> priv->ch_bit) & BIT(0);
717 writel(0xFF, priv->ddrmc_baseaddr + ECCW1_FLIP_CTRL);
719 writel(0xFF, priv->ddrmc_baseaddr + ECCW0_FLIP_CTRL);
721 writel(0, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC12_OFFSET);
722 writel(0, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC13_OFFSET);
724 regval = row & XDDR_NOC_ROW_MATCH_MASK;
725 regval |= FIELD_PREP(XDDR_NOC_COL_MATCH_MASK, col);
726 regval |= FIELD_PREP(XDDR_NOC_BANK_MATCH_MASK, bank);
727 regval |= FIELD_PREP(XDDR_NOC_GRP_MATCH_MASK, grp);
728 writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC14_OFFSET);
730 regval = rank & XDDR_NOC_RANK_MATCH_MASK;
731 regval |= FIELD_PREP(XDDR_NOC_LRANK_MATCH_MASK, lrank);
732 regval |= FIELD_PREP(XDDR_NOC_CH_MATCH_MASK, ch);
733 regval |= (XDDR_NOC_MOD_SEL_MASK | XDDR_NOC_MATCH_EN_MASK);
734 writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC15_OFFSET);
737 static ssize_t xddr_inject_data_poison_store(struct mem_ctl_info *mci,
738 const char __user *data)
740 struct edac_priv *priv = mci->pvt_info;
742 writel(0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);
743 writel(0, priv->ddrmc_baseaddr + ECCW1_FLIP0_OFFSET);
745 if (strncmp(data, "CE", 2) == 0) {
746 writel(ECC_CEPOISON_MASK, priv->ddrmc_baseaddr +
748 writel(ECC_CEPOISON_MASK, priv->ddrmc_baseaddr +
751 writel(ECC_UEPOISON_MASK, priv->ddrmc_baseaddr +
753 writel(ECC_UEPOISON_MASK, priv->ddrmc_baseaddr +
757 /* Lock the PCSR registers */
758 writel(1, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
763 static ssize_t inject_data_poison_store(struct file *file, const char __user *data,
764 size_t count, loff_t *ppos)
766 struct device *dev = file->private_data;
767 struct mem_ctl_info *mci = to_mci(dev);
768 struct edac_priv *priv = mci->pvt_info;
770 /* Unlock the PCSR registers */
771 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
772 writel(PCSR_UNLOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
776 /* Lock the PCSR registers */
777 writel(1, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
779 xddr_inject_data_poison_store(mci, data);
784 static const struct file_operations xddr_inject_enable_fops = {
786 .write = inject_data_poison_store,
787 .llseek = generic_file_llseek,
790 static void create_debugfs_attributes(struct mem_ctl_info *mci)
792 struct edac_priv *priv = mci->pvt_info;
794 priv->debugfs = edac_debugfs_create_dir(mci->dev_name);
798 edac_debugfs_create_file("inject_error", 0200, priv->debugfs,
799 &mci->dev, &xddr_inject_enable_fops);
800 debugfs_create_x64("address", 0600, priv->debugfs,
801 &priv->err_inject_addr);
802 mci->debugfs = priv->debugfs;
805 static inline void process_bit(struct edac_priv *priv, unsigned int start, u32 regval)
807 union edac_info rows;
810 priv->row_bit[start] = rows.row0;
811 priv->row_bit[start + 1] = rows.row1;
812 priv->row_bit[start + 2] = rows.row2;
813 priv->row_bit[start + 3] = rows.row3;
814 priv->row_bit[start + 4] = rows.row4;
817 static void setup_row_address_map(struct edac_priv *priv)
820 union edac_info rows;
822 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC5_OFFSET);
823 process_bit(priv, 0, regval);
825 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC6_OFFSET);
826 process_bit(priv, 5, regval);
828 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC7_OFFSET);
829 process_bit(priv, 10, regval);
831 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET);
834 priv->row_bit[15] = rows.row0;
835 priv->row_bit[16] = rows.row1;
836 priv->row_bit[17] = rows.row2;
839 static void setup_column_address_map(struct edac_priv *priv)
842 union edac_info cols;
844 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET);
845 priv->col_bit[0] = FIELD_GET(MASK_24, regval);
847 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC9_OFFSET);
849 priv->col_bit[1] = cols.col1;
850 priv->col_bit[2] = cols.col2;
851 priv->col_bit[3] = cols.col3;
852 priv->col_bit[4] = cols.col4;
853 priv->col_bit[5] = cols.col5;
855 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET);
857 priv->col_bit[6] = cols.col1;
858 priv->col_bit[7] = cols.col2;
859 priv->col_bit[8] = cols.col3;
860 priv->col_bit[9] = cols.col4;
863 static void setup_bank_grp_ch_address_map(struct edac_priv *priv)
867 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET);
868 priv->bank_bit[0] = FIELD_GET(MASK_24, regval);
870 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC11_OFFSET);
871 priv->bank_bit[1] = (regval & MASK_0);
872 priv->grp_bit[0] = FIELD_GET(GRP_0_MASK, regval);
873 priv->grp_bit[1] = FIELD_GET(GRP_1_MASK, regval);
874 priv->ch_bit = FIELD_GET(CH_0_MASK, regval);
877 static void setup_rank_lrank_address_map(struct edac_priv *priv)
881 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC4_OFFSET);
882 priv->rank_bit[0] = (regval & MASK_0);
883 priv->rank_bit[1] = FIELD_GET(RANK_1_MASK, regval);
884 priv->lrank_bit[0] = FIELD_GET(LRANK_0_MASK, regval);
885 priv->lrank_bit[1] = FIELD_GET(LRANK_1_MASK, regval);
886 priv->lrank_bit[2] = FIELD_GET(MASK_24, regval);
890 * setup_address_map - Set Address Map by querying ADDRMAP registers.
891 * @priv: DDR memory controller private instance data.
893 * Set Address Map by querying ADDRMAP registers.
897 static void setup_address_map(struct edac_priv *priv)
899 setup_row_address_map(priv);
901 setup_column_address_map(priv);
903 setup_bank_grp_ch_address_map(priv);
905 setup_rank_lrank_address_map(priv);
907 #endif /* CONFIG_EDAC_DEBUG */
909 static const struct of_device_id xlnx_edac_match[] = {
910 { .compatible = "xlnx,versal-ddrmc", },
916 MODULE_DEVICE_TABLE(of, xlnx_edac_match);
917 static u32 emif_get_id(struct device_node *node)
919 u32 addr, my_addr, my_id = 0;
920 struct device_node *np;
923 addrp = of_get_address(node, 0, NULL, NULL);
924 my_addr = (u32)of_translate_address(node, addrp);
926 for_each_matching_node(np, xlnx_edac_match) {
930 addrp = of_get_address(np, 0, NULL, NULL);
931 addr = (u32)of_translate_address(np, addrp);
933 edac_printk(KERN_INFO, EDAC_MC,
934 "addr=%x, my_addr=%x\n",
944 static int mc_probe(struct platform_device *pdev)
946 void __iomem *ddrmc_baseaddr, *ddrmc_noc_baseaddr;
947 struct edac_mc_layer layers[2];
948 struct mem_ctl_info *mci;
949 u8 num_chans, num_csrows;
950 struct edac_priv *priv;
951 u32 edac_mc_id, regval;
954 ddrmc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "base");
955 if (IS_ERR(ddrmc_baseaddr))
956 return PTR_ERR(ddrmc_baseaddr);
958 ddrmc_noc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "noc");
959 if (IS_ERR(ddrmc_noc_baseaddr))
960 return PTR_ERR(ddrmc_noc_baseaddr);
962 if (!get_ecc_state(ddrmc_baseaddr))
965 /* Allocate ID number for the EMIF controller */
966 edac_mc_id = emif_get_id(pdev->dev.of_node);
968 regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);
969 num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);
972 num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);
977 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
978 layers[0].size = num_csrows;
979 layers[0].is_virt_csrow = true;
980 layers[1].type = EDAC_MC_LAYER_CHANNEL;
981 layers[1].size = num_chans;
982 layers[1].is_virt_csrow = false;
984 mci = edac_mc_alloc(edac_mc_id, ARRAY_SIZE(layers), layers,
985 sizeof(struct edac_priv));
987 edac_printk(KERN_ERR, EDAC_MC,
988 "Failed memory allocation for mc instance\n");
992 priv = mci->pvt_info;
993 priv->ddrmc_baseaddr = ddrmc_baseaddr;
994 priv->ddrmc_noc_baseaddr = ddrmc_noc_baseaddr;
997 priv->mc_id = edac_mc_id;
1001 rc = edac_mc_add_mc(mci);
1003 edac_printk(KERN_ERR, EDAC_MC,
1004 "Failed to register with EDAC core\n");
1008 rc = xlnx_register_event(PM_NOTIFY_CB, EVENT_ERROR_PMC_ERR1,
1009 XPM_EVENT_ERROR_MASK_DDRMC_CR | XPM_EVENT_ERROR_MASK_DDRMC_NCR |
1010 XPM_EVENT_ERROR_MASK_NOC_CR | XPM_EVENT_ERROR_MASK_NOC_NCR,
1011 false, err_callback, mci);
1019 #ifdef CONFIG_EDAC_DEBUG
1020 create_debugfs_attributes(mci);
1021 setup_address_map(priv);
1027 edac_mc_del_mc(&pdev->dev);
1034 static int mc_remove(struct platform_device *pdev)
1036 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1037 struct edac_priv *priv = mci->pvt_info;
1041 #ifdef CONFIG_EDAC_DEBUG
1042 debugfs_remove_recursive(priv->debugfs);
1045 xlnx_unregister_event(PM_NOTIFY_CB, EVENT_ERROR_PMC_ERR1,
1046 XPM_EVENT_ERROR_MASK_DDRMC_CR |
1047 XPM_EVENT_ERROR_MASK_NOC_CR |
1048 XPM_EVENT_ERROR_MASK_NOC_NCR |
1049 XPM_EVENT_ERROR_MASK_DDRMC_NCR, err_callback, mci);
1050 edac_mc_del_mc(&pdev->dev);
1056 static struct platform_driver xilinx_ddr_edac_mc_driver = {
1058 .name = "xilinx-ddrmc-edac",
1059 .of_match_table = xlnx_edac_match,
1062 .remove = mc_remove,
1065 module_platform_driver(xilinx_ddr_edac_mc_driver);
1067 MODULE_AUTHOR("AMD Inc");
1068 MODULE_DESCRIPTION("Xilinx DDRMC ECC driver");
1069 MODULE_LICENSE("GPL");