drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <asm/processor.h>
  25 #include <asm/mce.h>
  26
  27 #include "edac_core.h"
  28
  29 /* Static vars */
  30 static LIST_HEAD(sbridge_edac_list);
  31 static DEFINE_MUTEX(sbridge_edac_lock);
  32 static int probed;
  33
  34 /*
  35  * Alter this version for the module when modifications are made
  36  */
  37 #define SBRIDGE_REVISION    " Ver: 1.1.1 "
  38 #define EDAC_MOD_STR      "sbridge_edac"
  39
  40 /*
  41  * Debug macros
  42  */
  43 #define sbridge_printk(level, fmt, arg...)                      \
  44         edac_printk(level, "sbridge", fmt, ##arg)
  45
  46 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  47         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  48
  49 /*
  50  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  51  */
  52 #define GET_BITFIELD(v, lo, hi) \
  53         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  54
  55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  56 static const u32 sbridge_dram_rule[] = {
  57         0x80, 0x88, 0x90, 0x98, 0xa0,
  58         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  59 };
  60
  61 static const u32 ibridge_dram_rule[] = {
  62         0x60, 0x68, 0x70, 0x78, 0x80,
  63         0x88, 0x90, 0x98, 0xa0, 0xa8,
  64         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  65         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  66 };
  67
  68 #define SAD_LIMIT(reg)          ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
  69 #define DRAM_ATTR(reg)          GET_BITFIELD(reg, 2,  3)
  70 #define INTERLEAVE_MODE(reg)    GET_BITFIELD(reg, 1,  1)
  71 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  72 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  73
  74 static char *get_dram_attr(u32 reg)
  75 {
  76         switch(DRAM_ATTR(reg)) {
  77                 case 0:
  78                         return "DRAM";
  79                 case 1:
  80                         return "MMCFG";
  81                 case 2:
  82                         return "NXM";
  83                 default:
  84                         return "unknown";
  85         }
  86 }
  87
  88 static const u32 sbridge_interleave_list[] = {
  89         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  90         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  91 };
  92
  93 static const u32 ibridge_interleave_list[] = {
  94         0x64, 0x6c, 0x74, 0x7c, 0x84,
  95         0x8c, 0x94, 0x9c, 0xa4, 0xac,
  96         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
  97         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
  98 };
  99
 100 struct interleave_pkg {
 101         unsigned char start;
 102         unsigned char end;
 103 };
 104
 105 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 106         { 0, 2 },
 107         { 3, 5 },
 108         { 8, 10 },
 109         { 11, 13 },
 110         { 16, 18 },
 111         { 19, 21 },
 112         { 24, 26 },
 113         { 27, 29 },
 114 };
 115
 116 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 117         { 0, 3 },
 118         { 4, 7 },
 119         { 8, 11 },
 120         { 12, 15 },
 121         { 16, 19 },
 122         { 20, 23 },
 123         { 24, 27 },
 124         { 28, 31 },
 125 };
 126
 127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 128                           int interleave)
 129 {
 130         return GET_BITFIELD(reg, table[interleave].start,
 131                             table[interleave].end);
 132 }
 133
 134 /* Devices 12 Function 7 */
 135
 136 #define TOLM            0x80
 137 #define TOHM            0x84
 138 #define HASWELL_TOLM    0xd0
 139 #define HASWELL_TOHM_0  0xd4
 140 #define HASWELL_TOHM_1  0xd8
 141
 142 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 143 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 144
 145 /* Device 13 Function 6 */
 146
 147 #define SAD_TARGET      0xf0
 148
 149 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 150
 151 #define SAD_CONTROL     0xf4
 152
 153 /* Device 14 function 0 */
 154
 155 static const u32 tad_dram_rule[] = {
 156         0x40, 0x44, 0x48, 0x4c,
 157         0x50, 0x54, 0x58, 0x5c,
 158         0x60, 0x64, 0x68, 0x6c,
 159 };
 160 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 161
 162 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 163 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 164 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 165 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 166 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 167 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 168 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 169
 170 /* Device 15, function 0 */
 171
 172 #define MCMTR                   0x7c
 173
 174 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 175 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 176 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 177
 178 /* Device 15, function 1 */
 179
 180 #define RASENABLES              0xac
 181 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 182
 183 /* Device 15, functions 2-5 */
 184
 185 static const int mtr_regs[] = {
 186         0x80, 0x84, 0x88,
 187 };
 188
 189 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 190 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 191 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 192 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 193 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 194
 195 static const u32 tad_ch_nilv_offset[] = {
 196         0x90, 0x94, 0x98, 0x9c,
 197         0xa0, 0xa4, 0xa8, 0xac,
 198         0xb0, 0xb4, 0xb8, 0xbc,
 199 };
 200 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 201 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 202
 203 static const u32 rir_way_limit[] = {
 204         0x108, 0x10c, 0x110, 0x114, 0x118,
 205 };
 206 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 207
 208 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 209 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 210
 211 #define MAX_RIR_WAY     8
 212
 213 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 214         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 215         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 216         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 217         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 218         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 219 };
 220
 221 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
 222         GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
 223
 224 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
 225         GET_BITFIELD(reg,  2, 15) : GET_BITFIELD(reg,  2, 14))
 226
 227 /* Device 16, functions 2-7 */
 228
 229 /*
 230  * FIXME: Implement the error count reads directly
 231  */
 232
 233 static const u32 correrrcnt[] = {
 234         0x104, 0x108, 0x10c, 0x110,
 235 };
 236
 237 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 238 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 239 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 240 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 241
 242 static const u32 correrrthrsld[] = {
 243         0x11c, 0x120, 0x124, 0x128,
 244 };
 245
 246 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 247 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 248
 249
 250 /* Device 17, function 0 */
 251
 252 #define SB_RANK_CFG_A           0x0328
 253
 254 #define IB_RANK_CFG_A           0x0320
 255
 256 /*
 257  * sbridge structs
 258  */
 259
 260 #define NUM_CHANNELS            8       /* 2MC per socket, four chan per MC */
 261 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 262 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 263
 264 enum type {
 265         SANDY_BRIDGE,
 266         IVY_BRIDGE,
 267         HASWELL,
 268         BROADWELL,
 269 };
 270
 271 struct sbridge_pvt;
 272 struct sbridge_info {
 273         enum type       type;
 274         u32             mcmtr;
 275         u32             rankcfgr;
 276         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 277         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 278         u64             (*rir_limit)(u32 reg);
 279         const u32       *dram_rule;
 280         const u32       *interleave_list;
 281         const struct interleave_pkg *interleave_pkg;
 282         u8              max_sad;
 283         u8              max_interleave;
 284         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 285         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 286         enum dev_type   (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
 287         struct pci_dev  *pci_vtd;
 288 };
 289
 290 struct sbridge_channel {
 291         u32             ranks;
 292         u32             dimms;
 293 };
 294
 295 struct pci_id_descr {
 296         int                     dev_id;
 297         int                     optional;
 298 };
 299
 300 struct pci_id_table {
 301         const struct pci_id_descr       *descr;
 302         int                             n_devs;
 303 };
 304
 305 struct sbridge_dev {
 306         struct list_head        list;
 307         u8                      bus, mc;
 308         u8                      node_id, source_id;
 309         struct pci_dev          **pdev;
 310         int                     n_devs;
 311         struct mem_ctl_info     *mci;
 312 };
 313
 314 struct sbridge_pvt {
 315         struct pci_dev          *pci_ta, *pci_ddrio, *pci_ras;
 316         struct pci_dev          *pci_sad0, *pci_sad1;
 317         struct pci_dev          *pci_ha0, *pci_ha1;
 318         struct pci_dev          *pci_br0, *pci_br1;
 319         struct pci_dev          *pci_ha1_ta;
 320         struct pci_dev          *pci_tad[NUM_CHANNELS];
 321
 322         struct sbridge_dev      *sbridge_dev;
 323
 324         struct sbridge_info     info;
 325         struct sbridge_channel  channel[NUM_CHANNELS];
 326
 327         /* Memory type detection */
 328         bool                    is_mirrored, is_lockstep, is_close_pg;
 329
 330         /* Fifo double buffers */
 331         struct mce              mce_entry[MCE_LOG_LEN];
 332         struct mce              mce_outentry[MCE_LOG_LEN];
 333
 334         /* Fifo in/out counters */
 335         unsigned                mce_in, mce_out;
 336
 337         /* Count indicator to show errors not got */
 338         unsigned                mce_overrun;
 339
 340         /* Memory description */
 341         u64                     tolm, tohm;
 342 };
 343
 344 #define PCI_DESCR(device_id, opt)       \
 345         .dev_id = (device_id),          \
 346         .optional = opt
 347
 348 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 349                 /* Processor Home Agent */
 350         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)     },
 351
 352                 /* Memory controller */
 353         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)      },
 354         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)     },
 355         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)    },
 356         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)    },
 357         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)    },
 358         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)    },
 359         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)   },
 360
 361                 /* System Address Decoder */
 362         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)        },
 363         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)        },
 364
 365                 /* Broadcast Registers */
 366         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)          },
 367 };
 368
 369 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
 370 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 371         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
 372         {0,}                    /* 0 terminated list. */
 373 };
 374
 375 /* This changes depending if 1HA or 2HA:
 376  * 1HA:
 377  *      0x0eb8 (17.0) is DDRIO0
 378  * 2HA:
 379  *      0x0ebc (17.4) is DDRIO0
 380  */
 381 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 382 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 383
 384 /* pci ids */
 385 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 386 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 387 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 388 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 389 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 390 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 391 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 392 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 393 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 394 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 395 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 396 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 397 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 398 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 399 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 400 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 401 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 402
 403 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 404                 /* Processor Home Agent */
 405         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)             },
 406
 407                 /* Memory controller */
 408         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)          },
 409         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)         },
 410         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)        },
 411         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)        },
 412         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)        },
 413         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)        },
 414
 415                 /* System Address Decoder */
 416         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)                 },
 417
 418                 /* Broadcast Registers */
 419         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)                 },
 420         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)                 },
 421
 422                 /* Optional, mode 2HA */
 423         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)             },
 424 #if 0
 425         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)  },
 426         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
 427 #endif
 428         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)        },
 429         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)        },
 430         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1)        },
 431         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1)        },
 432
 433         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)      },
 434         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)      },
 435 };
 436
 437 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 438         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
 439         {0,}                    /* 0 terminated list. */
 440 };
 441
 442 /* Haswell support */
 443 /* EN processor:
 444  *      - 1 IMC
 445  *      - 3 DDR3 channels, 2 DPC per channel
 446  * EP processor:
 447  *      - 1 or 2 IMC
 448  *      - 4 DDR4 channels, 3 DPC per channel
 449  * EP 4S processor:
 450  *      - 2 IMC
 451  *      - 4 DDR4 channels, 3 DPC per channel
 452  * EX processor:
 453  *      - 2 IMC
 454  *      - each IMC interfaces with a SMI 2 channel
 455  *      - each SMI channel interfaces with a scalable memory buffer
 456  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 457  */
 458 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 459 #define HASWELL_HASYSDEFEATURE2 0x84
 460 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 461 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 462 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 463 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 464 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
 465 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 466 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
 467 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 468 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 469 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 470 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 471 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 472 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 473 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 474 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 475 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 476 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 477 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 478 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 479 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 480 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 481 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 482         /* first item must be the HA */
 483         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)             },
 484
 485         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)        },
 486         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)        },
 487
 488         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)             },
 489
 490         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)          },
 491         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)     },
 492         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)        },
 493         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)        },
 494         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)        },
 495         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)        },
 496
 497         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)          },
 498         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1)          },
 499         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1)          },
 500         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1)          },
 501
 502         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)          },
 503         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)     },
 504         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)        },
 505         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)        },
 506         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)        },
 507         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)        },
 508 };
 509
 510 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 511         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
 512         {0,}                    /* 0 terminated list. */
 513 };
 514
 515 /*
 516  * Broadwell support
 517  *
 518  * DE processor:
 519  *      - 1 IMC
 520  *      - 2 DDR3 channels, 2 DPC per channel
 521  * EP processor:
 522  *      - 1 or 2 IMC
 523  *      - 4 DDR4 channels, 3 DPC per channel
 524  * EP 4S processor:
 525  *      - 2 IMC
 526  *      - 4 DDR4 channels, 3 DPC per channel
 527  * EX processor:
 528  *      - 2 IMC
 529  *      - each IMC interfaces with a SMI 2 channel
 530  *      - each SMI channel interfaces with a scalable memory buffer
 531  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 532  */
 533 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 534 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 535 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 536 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 537 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
 538 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 539 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
 540 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 541 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 542 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 543 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 544 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 545 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 546 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 547 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 548 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 549 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 550 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 551
 552 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 553         /* first item must be the HA */
 554         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0)           },
 555
 556         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0)      },
 557         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0)      },
 558
 559         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1)           },
 560
 561         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0)        },
 562         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0)   },
 563         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0)      },
 564         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0)      },
 565         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1)      },
 566         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1)      },
 567
 568         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1)        },
 569
 570         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1)        },
 571         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1)   },
 572         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1)      },
 573         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1)      },
 574         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1)      },
 575         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1)      },
 576 };
 577
 578 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 579         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
 580         {0,}                    /* 0 terminated list. */
 581 };
 582
 583 /*
 584  *      pci_device_id   table for which devices we are looking for
 585  */
 586 static const struct pci_device_id sbridge_pci_tbl[] = {
 587         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
 588         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
 589         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
 590         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
 591         {0,}                    /* 0 terminated list. */
 592 };
 593
 594
 595 /****************************************************************************
 596                         Ancillary status routines
 597  ****************************************************************************/
 598
 599 static inline int numrank(enum type type, u32 mtr)
 600 {
 601         int ranks = (1 << RANK_CNT_BITS(mtr));
 602         int max = 4;
 603
 604         if (type == HASWELL || type == BROADWELL)
 605                 max = 8;
 606
 607         if (ranks > max) {
 608                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 609                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 610                 return -EINVAL;
 611         }
 612
 613         return ranks;
 614 }
 615
 616 static inline int numrow(u32 mtr)
 617 {
 618         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 619
 620         if (rows < 13 || rows > 18) {
 621                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 622                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 623                 return -EINVAL;
 624         }
 625
 626         return 1 << rows;
 627 }
 628
 629 static inline int numcol(u32 mtr)
 630 {
 631         int cols = (COL_WIDTH_BITS(mtr) + 10);
 632
 633         if (cols > 12) {
 634                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 635                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 636                 return -EINVAL;
 637         }
 638
 639         return 1 << cols;
 640 }
 641
 642 static struct sbridge_dev *get_sbridge_dev(u8 bus)
 643 {
 644         struct sbridge_dev *sbridge_dev;
 645
 646         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
 647                 if (sbridge_dev->bus == bus)
 648                         return sbridge_dev;
 649         }
 650
 651         return NULL;
 652 }
 653
 654 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
 655                                            const struct pci_id_table *table)
 656 {
 657         struct sbridge_dev *sbridge_dev;
 658
 659         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 660         if (!sbridge_dev)
 661                 return NULL;
 662
 663         sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
 664                                    GFP_KERNEL);
 665         if (!sbridge_dev->pdev) {
 666                 kfree(sbridge_dev);
 667                 return NULL;
 668         }
 669
 670         sbridge_dev->bus = bus;
 671         sbridge_dev->n_devs = table->n_devs;
 672         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 673
 674         return sbridge_dev;
 675 }
 676
 677 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 678 {
 679         list_del(&sbridge_dev->list);
 680         kfree(sbridge_dev->pdev);
 681         kfree(sbridge_dev);
 682 }
 683
 684 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 685 {
 686         u32 reg;
 687
 688         /* Address range is 32:28 */
 689         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 690         return GET_TOLM(reg);
 691 }
 692
 693 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 694 {
 695         u32 reg;
 696
 697         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 698         return GET_TOHM(reg);
 699 }
 700
 701 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 702 {
 703         u32 reg;
 704
 705         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 706
 707         return GET_TOLM(reg);
 708 }
 709
 710 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 711 {
 712         u32 reg;
 713
 714         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 715
 716         return GET_TOHM(reg);
 717 }
 718
 719 static u64 rir_limit(u32 reg)
 720 {
 721         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 722 }
 723
 724 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 725 {
 726         u32 reg;
 727         enum mem_type mtype;
 728
 729         if (pvt->pci_ddrio) {
 730                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 731                                       &reg);
 732                 if (GET_BITFIELD(reg, 11, 11))
 733                         /* FIXME: Can also be LRDIMM */
 734                         mtype = MEM_RDDR3;
 735                 else
 736                         mtype = MEM_DDR3;
 737         } else
 738                 mtype = MEM_UNKNOWN;
 739
 740         return mtype;
 741 }
 742
 743 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 744 {
 745         u32 reg;
 746         bool registered = false;
 747         enum mem_type mtype = MEM_UNKNOWN;
 748
 749         if (!pvt->pci_ddrio)
 750                 goto out;
 751
 752         pci_read_config_dword(pvt->pci_ddrio,
 753                               HASWELL_DDRCRCLKCONTROLS, &reg);
 754         /* Is_Rdimm */
 755         if (GET_BITFIELD(reg, 16, 16))
 756                 registered = true;
 757
 758         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 759         if (GET_BITFIELD(reg, 14, 14)) {
 760                 if (registered)
 761                         mtype = MEM_RDDR4;
 762                 else
 763                         mtype = MEM_DDR4;
 764         } else {
 765                 if (registered)
 766                         mtype = MEM_RDDR3;
 767                 else
 768                         mtype = MEM_DDR3;
 769         }
 770
 771 out:
 772         return mtype;
 773 }
 774
 775 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 776 {
 777         /* there's no way to figure out */
 778         return DEV_UNKNOWN;
 779 }
 780
 781 static enum dev_type __ibridge_get_width(u32 mtr)
 782 {
 783         enum dev_type type;
 784
 785         switch (mtr) {
 786         case 3:
 787                 type = DEV_UNKNOWN;
 788                 break;
 789         case 2:
 790                 type = DEV_X16;
 791                 break;
 792         case 1:
 793                 type = DEV_X8;
 794                 break;
 795         case 0:
 796                 type = DEV_X4;
 797                 break;
 798         }
 799
 800         return type;
 801 }
 802
 803 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 804 {
 805         /*
 806          * ddr3_width on the documentation but also valid for DDR4 on
 807          * Haswell
 808          */
 809         return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
 810 }
 811
 812 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
 813 {
 814         /* ddr3_width on the documentation but also valid for DDR4 */
 815         return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
 816 }
 817
 818 static u8 get_node_id(struct sbridge_pvt *pvt)
 819 {
 820         u32 reg;
 821         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 822         return GET_BITFIELD(reg, 0, 2);
 823 }
 824
 825 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 826 {
 827         u32 reg;
 828
 829         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 830         return GET_BITFIELD(reg, 0, 3);
 831 }
 832
 833 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
 834 {
 835         u32 reg;
 836
 837         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
 838         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
 839 }
 840
 841 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
 842 {
 843         u64 rc;
 844         u32 reg;
 845
 846         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
 847         rc = GET_BITFIELD(reg, 26, 31);
 848         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
 849         rc = ((reg << 6) | rc) << 26;
 850
 851         return rc | 0x1ffffff;
 852 }
 853
 854 static u64 haswell_rir_limit(u32 reg)
 855 {
 856         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
 857 }
 858
 859 static inline u8 sad_pkg_socket(u8 pkg)
 860 {
 861         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
 862         return ((pkg >> 3) << 2) | (pkg & 0x3);
 863 }
 864
 865 static inline u8 sad_pkg_ha(u8 pkg)
 866 {
 867         return (pkg >> 2) & 0x1;
 868 }
 869
 870 /****************************************************************************
 871                         Memory check routines
 872  ****************************************************************************/
 873 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
 874 {
 875         struct pci_dev *pdev = NULL;
 876
 877         do {
 878                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
 879                 if (pdev && pdev->bus->number == bus)
 880                         break;
 881         } while (pdev);
 882
 883         return pdev;
 884 }
 885
 886 /**
 887  * check_if_ecc_is_active() - Checks if ECC is active
 888  * @bus:        Device bus
 889  * @type:       Memory controller type
 890  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
 891  *          disabled
 892  */
 893 static int check_if_ecc_is_active(const u8 bus, enum type type)
 894 {
 895         struct pci_dev *pdev = NULL;
 896         u32 mcmtr, id;
 897
 898         switch (type) {
 899         case IVY_BRIDGE:
 900                 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
 901                 break;
 902         case HASWELL:
 903                 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
 904                 break;
 905         case SANDY_BRIDGE:
 906                 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
 907                 break;
 908         case BROADWELL:
 909                 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
 910                 break;
 911         default:
 912                 return -ENODEV;
 913         }
 914
 915         pdev = get_pdev_same_bus(bus, id);
 916         if (!pdev) {
 917                 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
 918                                         "%04x:%04x! on bus %02d\n",
 919                                         PCI_VENDOR_ID_INTEL, id, bus);
 920                 return -ENODEV;
 921         }
 922
 923         pci_read_config_dword(pdev, MCMTR, &mcmtr);
 924         if (!IS_ECC_ENABLED(mcmtr)) {
 925                 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
 926                 return -ENODEV;
 927         }
 928         return 0;
 929 }
 930
 931 static int get_dimm_config(struct mem_ctl_info *mci)
 932 {
 933         struct sbridge_pvt *pvt = mci->pvt_info;
 934         struct dimm_info *dimm;
 935         unsigned i, j, banks, ranks, rows, cols, npages;
 936         u64 size;
 937         u32 reg;
 938         enum edac_type mode;
 939         enum mem_type mtype;
 940
 941         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
 942                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
 943         else
 944                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
 945
 946         pvt->sbridge_dev->source_id = SOURCE_ID(reg);
 947
 948         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
 949         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
 950                  pvt->sbridge_dev->mc,
 951                  pvt->sbridge_dev->node_id,
 952                  pvt->sbridge_dev->source_id);
 953
 954         pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
 955         if (IS_MIRROR_ENABLED(reg)) {
 956                 edac_dbg(0, "Memory mirror is enabled\n");
 957                 pvt->is_mirrored = true;
 958         } else {
 959                 edac_dbg(0, "Memory mirror is disabled\n");
 960                 pvt->is_mirrored = false;
 961         }
 962
 963         pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
 964         if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
 965                 edac_dbg(0, "Lockstep is enabled\n");
 966                 mode = EDAC_S8ECD8ED;
 967                 pvt->is_lockstep = true;
 968         } else {
 969                 edac_dbg(0, "Lockstep is disabled\n");
 970                 mode = EDAC_S4ECD4ED;
 971                 pvt->is_lockstep = false;
 972         }
 973         if (IS_CLOSE_PG(pvt->info.mcmtr)) {
 974                 edac_dbg(0, "address map is on closed page mode\n");
 975                 pvt->is_close_pg = true;
 976         } else {
 977                 edac_dbg(0, "address map is on open page mode\n");
 978                 pvt->is_close_pg = false;
 979         }
 980
 981         mtype = pvt->info.get_memory_type(pvt);
 982         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
 983                 edac_dbg(0, "Memory is registered\n");
 984         else if (mtype == MEM_UNKNOWN)
 985                 edac_dbg(0, "Cannot determine memory type\n");
 986         else
 987                 edac_dbg(0, "Memory is unregistered\n");
 988
 989         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
 990                 banks = 16;
 991         else
 992                 banks = 8;
 993
 994         for (i = 0; i < NUM_CHANNELS; i++) {
 995                 u32 mtr;
 996
 997                 if (!pvt->pci_tad[i])
 998                         continue;
 999                 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
1000                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1001                                        i, j, 0);
1002                         pci_read_config_dword(pvt->pci_tad[i],
1003                                               mtr_regs[j], &mtr);
1004                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1005                         if (IS_DIMM_PRESENT(mtr)) {
1006                                 pvt->channel[i].dimms++;
1007
1008                                 ranks = numrank(pvt->info.type, mtr);
1009                                 rows = numrow(mtr);
1010                                 cols = numcol(mtr);
1011
1012                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1013                                 npages = MiB_TO_PAGES(size);
1014
1015                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1016                                          pvt->sbridge_dev->mc, i/4, i%4, j,
1017                                          size, npages,
1018                                          banks, ranks, rows, cols);
1019
1020                                 dimm->nr_pages = npages;
1021                                 dimm->grain = 32;
1022                                 dimm->dtype = pvt->info.get_width(pvt, mtr);
1023                                 dimm->mtype = mtype;
1024                                 dimm->edac_mode = mode;
1025                                 snprintf(dimm->label, sizeof(dimm->label),
1026                                          "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1027                                          pvt->sbridge_dev->source_id, i/4, i%4, j);
1028                         }
1029                 }
1030         }
1031
1032         return 0;
1033 }
1034
1035 static void get_memory_layout(const struct mem_ctl_info *mci)
1036 {
1037         struct sbridge_pvt *pvt = mci->pvt_info;
1038         int i, j, k, n_sads, n_tads, sad_interl;
1039         u32 reg;
1040         u64 limit, prv = 0;
1041         u64 tmp_mb;
1042         u32 gb, mb;
1043         u32 rir_way;
1044
1045         /*
1046          * Step 1) Get TOLM/TOHM ranges
1047          */
1048
1049         pvt->tolm = pvt->info.get_tolm(pvt);
1050         tmp_mb = (1 + pvt->tolm) >> 20;
1051
1052         gb = div_u64_rem(tmp_mb, 1024, &mb);
1053         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1054                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1055
1056         /* Address range is already 45:25 */
1057         pvt->tohm = pvt->info.get_tohm(pvt);
1058         tmp_mb = (1 + pvt->tohm) >> 20;
1059
1060         gb = div_u64_rem(tmp_mb, 1024, &mb);
1061         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1062                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1063
1064         /*
1065          * Step 2) Get SAD range and SAD Interleave list
1066          * TAD registers contain the interleave wayness. However, it
1067          * seems simpler to just discover it indirectly, with the
1068          * algorithm bellow.
1069          */
1070         prv = 0;
1071         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1072                 /* SAD_LIMIT Address range is 45:26 */
1073                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1074                                       &reg);
1075                 limit = SAD_LIMIT(reg);
1076
1077                 if (!DRAM_RULE_ENABLE(reg))
1078                         continue;
1079
1080                 if (limit <= prv)
1081                         break;
1082
1083                 tmp_mb = (limit + 1) >> 20;
1084                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1085                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1086                          n_sads,
1087                          get_dram_attr(reg),
1088                          gb, (mb*1000)/1024,
1089                          ((u64)tmp_mb) << 20L,
1090                          INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
1091                          reg);
1092                 prv = limit;
1093
1094                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1095                                       &reg);
1096                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1097                 for (j = 0; j < 8; j++) {
1098                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1099                         if (j > 0 && sad_interl == pkg)
1100                                 break;
1101
1102                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1103                                  n_sads, j, pkg);
1104                 }
1105         }
1106
1107         /*
1108          * Step 3) Get TAD range
1109          */
1110         prv = 0;
1111         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1112                 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1113                                       &reg);
1114                 limit = TAD_LIMIT(reg);
1115                 if (limit <= prv)
1116                         break;
1117                 tmp_mb = (limit + 1) >> 20;
1118
1119                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1120                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1121                          n_tads, gb, (mb*1000)/1024,
1122                          ((u64)tmp_mb) << 20L,
1123                          (u32)(1 << TAD_SOCK(reg)),
1124                          (u32)TAD_CH(reg) + 1,
1125                          (u32)TAD_TGT0(reg),
1126                          (u32)TAD_TGT1(reg),
1127                          (u32)TAD_TGT2(reg),
1128                          (u32)TAD_TGT3(reg),
1129                          reg);
1130                 prv = limit;
1131         }
1132
1133         /*
1134          * Step 4) Get TAD offsets, per each channel
1135          */
1136         for (i = 0; i < NUM_CHANNELS; i++) {
1137                 if (!pvt->channel[i].dimms)
1138                         continue;
1139                 for (j = 0; j < n_tads; j++) {
1140                         pci_read_config_dword(pvt->pci_tad[i],
1141                                               tad_ch_nilv_offset[j],
1142                                               &reg);
1143                         tmp_mb = TAD_OFFSET(reg) >> 20;
1144                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1145                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1146                                  i, j,
1147                                  gb, (mb*1000)/1024,
1148                                  ((u64)tmp_mb) << 20L,
1149                                  reg);
1150                 }
1151         }
1152
1153         /*
1154          * Step 6) Get RIR Wayness/Limit, per each channel
1155          */
1156         for (i = 0; i < NUM_CHANNELS; i++) {
1157                 if (!pvt->channel[i].dimms)
1158                         continue;
1159                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1160                         pci_read_config_dword(pvt->pci_tad[i],
1161                                               rir_way_limit[j],
1162                                               &reg);
1163
1164                         if (!IS_RIR_VALID(reg))
1165                                 continue;
1166
1167                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1168                         rir_way = 1 << RIR_WAY(reg);
1169                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1170                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1171                                  i, j,
1172                                  gb, (mb*1000)/1024,
1173                                  ((u64)tmp_mb) << 20L,
1174                                  rir_way,
1175                                  reg);
1176
1177                         for (k = 0; k < rir_way; k++) {
1178                                 pci_read_config_dword(pvt->pci_tad[i],
1179                                                       rir_offset[j][k],
1180                                                       &reg);
1181                                 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1182
1183                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1184                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1185                                          i, j, k,
1186                                          gb, (mb*1000)/1024,
1187                                          ((u64)tmp_mb) << 20L,
1188                                          (u32)RIR_RNK_TGT(pvt->info.type, reg),
1189                                          reg);
1190                         }
1191                 }
1192         }
1193 }
1194
1195 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1196 {
1197         struct sbridge_dev *sbridge_dev;
1198
1199         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1200                 if (sbridge_dev->node_id == node_id)
1201                         return sbridge_dev->mci;
1202         }
1203         return NULL;
1204 }
1205
1206 static int get_memory_error_data(struct mem_ctl_info *mci,
1207                                  u64 addr,
1208                                  u8 *socket, u8 *ha,
1209                                  long *channel_mask,
1210                                  u8 *rank,
1211                                  char **area_type, char *msg)
1212 {
1213         struct mem_ctl_info     *new_mci;
1214         struct sbridge_pvt *pvt = mci->pvt_info;
1215         struct pci_dev          *pci_ha;
1216         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1217         int                     sad_interl, idx, base_ch;
1218         int                     interleave_mode, shiftup = 0;
1219         unsigned                sad_interleave[pvt->info.max_interleave];
1220         u32                     reg, dram_rule;
1221         u8                      ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1222         u32                     tad_offset;
1223         u32                     rir_way;
1224         u32                     mb, gb;
1225         u64                     ch_addr, offset, limit = 0, prv = 0;
1226
1227
1228         /*
1229          * Step 0) Check if the address is at special memory ranges
1230          * The check bellow is probably enough to fill all cases where
1231          * the error is not inside a memory, except for the legacy
1232          * range (e. g. VGA addresses). It is unlikely, however, that the
1233          * memory controller would generate an error on that range.
1234          */
1235         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1236                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1237                 return -EINVAL;
1238         }
1239         if (addr >= (u64)pvt->tohm) {
1240                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1241                 return -EINVAL;
1242         }
1243
1244         /*
1245          * Step 1) Get socket
1246          */
1247         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1248                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1249                                       &reg);
1250
1251                 if (!DRAM_RULE_ENABLE(reg))
1252                         continue;
1253
1254                 limit = SAD_LIMIT(reg);
1255                 if (limit <= prv) {
1256                         sprintf(msg, "Can't discover the memory socket");
1257                         return -EINVAL;
1258                 }
1259                 if  (addr <= limit)
1260                         break;
1261                 prv = limit;
1262         }
1263         if (n_sads == pvt->info.max_sad) {
1264                 sprintf(msg, "Can't discover the memory socket");
1265                 return -EINVAL;
1266         }
1267         dram_rule = reg;
1268         *area_type = get_dram_attr(dram_rule);
1269         interleave_mode = INTERLEAVE_MODE(dram_rule);
1270
1271         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1272                               &reg);
1273
1274         if (pvt->info.type == SANDY_BRIDGE) {
1275                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1276                 for (sad_way = 0; sad_way < 8; sad_way++) {
1277                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1278                         if (sad_way > 0 && sad_interl == pkg)
1279                                 break;
1280                         sad_interleave[sad_way] = pkg;
1281                         edac_dbg(0, "SAD interleave #%d: %d\n",
1282                                  sad_way, sad_interleave[sad_way]);
1283                 }
1284                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1285                          pvt->sbridge_dev->mc,
1286                          n_sads,
1287                          addr,
1288                          limit,
1289                          sad_way + 7,
1290                          !interleave_mode ? "" : "XOR[18:16]");
1291                 if (interleave_mode)
1292                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1293                 else
1294                         idx = (addr >> 6) & 7;
1295                 switch (sad_way) {
1296                 case 1:
1297                         idx = 0;
1298                         break;
1299                 case 2:
1300                         idx = idx & 1;
1301                         break;
1302                 case 4:
1303                         idx = idx & 3;
1304                         break;
1305                 case 8:
1306                         break;
1307                 default:
1308                         sprintf(msg, "Can't discover socket interleave");
1309                         return -EINVAL;
1310                 }
1311                 *socket = sad_interleave[idx];
1312                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1313                          idx, sad_way, *socket);
1314         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1315                 int bits, a7mode = A7MODE(dram_rule);
1316
1317                 if (a7mode) {
1318                         /* A7 mode swaps P9 with P6 */
1319                         bits = GET_BITFIELD(addr, 7, 8) << 1;
1320                         bits |= GET_BITFIELD(addr, 9, 9);
1321                 } else
1322                         bits = GET_BITFIELD(addr, 6, 8);
1323
1324                 if (interleave_mode == 0) {
1325                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
1326                         idx = GET_BITFIELD(addr, 16, 18);
1327                         idx ^= bits;
1328                 } else
1329                         idx = bits;
1330
1331                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1332                 *socket = sad_pkg_socket(pkg);
1333                 sad_ha = sad_pkg_ha(pkg);
1334                 if (sad_ha)
1335                         ch_add = 4;
1336
1337                 if (a7mode) {
1338                         /* MCChanShiftUpEnable */
1339                         pci_read_config_dword(pvt->pci_ha0,
1340                                               HASWELL_HASYSDEFEATURE2, &reg);
1341                         shiftup = GET_BITFIELD(reg, 22, 22);
1342                 }
1343
1344                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1345                          idx, *socket, sad_ha, shiftup);
1346         } else {
1347                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
1348                 idx = (addr >> 6) & 7;
1349                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1350                 *socket = sad_pkg_socket(pkg);
1351                 sad_ha = sad_pkg_ha(pkg);
1352                 if (sad_ha)
1353                         ch_add = 4;
1354                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1355                          idx, *socket, sad_ha);
1356         }
1357
1358         *ha = sad_ha;
1359
1360         /*
1361          * Move to the proper node structure, in order to access the
1362          * right PCI registers
1363          */
1364         new_mci = get_mci_for_node_id(*socket);
1365         if (!new_mci) {
1366                 sprintf(msg, "Struct for socket #%u wasn't initialized",
1367                         *socket);
1368                 return -EINVAL;
1369         }
1370         mci = new_mci;
1371         pvt = mci->pvt_info;
1372
1373         /*
1374          * Step 2) Get memory channel
1375          */
1376         prv = 0;
1377         if (pvt->info.type == SANDY_BRIDGE)
1378                 pci_ha = pvt->pci_ha0;
1379         else {
1380                 if (sad_ha)
1381                         pci_ha = pvt->pci_ha1;
1382                 else
1383                         pci_ha = pvt->pci_ha0;
1384         }
1385         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1386                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
1387                 limit = TAD_LIMIT(reg);
1388                 if (limit <= prv) {
1389                         sprintf(msg, "Can't discover the memory channel");
1390                         return -EINVAL;
1391                 }
1392                 if  (addr <= limit)
1393                         break;
1394                 prv = limit;
1395         }
1396         if (n_tads == MAX_TAD) {
1397                 sprintf(msg, "Can't discover the memory channel");
1398                 return -EINVAL;
1399         }
1400
1401         ch_way = TAD_CH(reg) + 1;
1402         sck_way = TAD_SOCK(reg);
1403
1404         if (ch_way == 3)
1405                 idx = addr >> 6;
1406         else
1407                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
1408         idx = idx % ch_way;
1409
1410         /*
1411          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1412          */
1413         switch (idx) {
1414         case 0:
1415                 base_ch = TAD_TGT0(reg);
1416                 break;
1417         case 1:
1418                 base_ch = TAD_TGT1(reg);
1419                 break;
1420         case 2:
1421                 base_ch = TAD_TGT2(reg);
1422                 break;
1423         case 3:
1424                 base_ch = TAD_TGT3(reg);
1425                 break;
1426         default:
1427                 sprintf(msg, "Can't discover the TAD target");
1428                 return -EINVAL;
1429         }
1430         *channel_mask = 1 << base_ch;
1431
1432         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1433                                 tad_ch_nilv_offset[n_tads],
1434                                 &tad_offset);
1435
1436         if (pvt->is_mirrored) {
1437                 *channel_mask |= 1 << ((base_ch + 2) % 4);
1438                 switch(ch_way) {
1439                 case 2:
1440                 case 4:
1441                         sck_xch = (1 << sck_way) * (ch_way >> 1);
1442                         break;
1443                 default:
1444                         sprintf(msg, "Invalid mirror set. Can't decode addr");
1445                         return -EINVAL;
1446                 }
1447         } else
1448                 sck_xch = (1 << sck_way) * ch_way;
1449
1450         if (pvt->is_lockstep)
1451                 *channel_mask |= 1 << ((base_ch + 1) % 4);
1452
1453         offset = TAD_OFFSET(tad_offset);
1454
1455         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1456                  n_tads,
1457                  addr,
1458                  limit,
1459                  sck_way,
1460                  ch_way,
1461                  offset,
1462                  idx,
1463                  base_ch,
1464                  *channel_mask);
1465
1466         /* Calculate channel address */
1467         /* Remove the TAD offset */
1468
1469         if (offset > addr) {
1470                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1471                         offset, addr);
1472                 return -EINVAL;
1473         }
1474
1475         ch_addr = addr - offset;
1476         ch_addr >>= (6 + shiftup);
1477         ch_addr /= sck_xch;
1478         ch_addr <<= (6 + shiftup);
1479         ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
1480
1481         /*
1482          * Step 3) Decode rank
1483          */
1484         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1485                 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1486                                       rir_way_limit[n_rir],
1487                                       &reg);
1488
1489                 if (!IS_RIR_VALID(reg))
1490                         continue;
1491
1492                 limit = pvt->info.rir_limit(reg);
1493                 gb = div_u64_rem(limit >> 20, 1024, &mb);
1494                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1495                          n_rir,
1496                          gb, (mb*1000)/1024,
1497                          limit,
1498                          1 << RIR_WAY(reg));
1499                 if  (ch_addr <= limit)
1500                         break;
1501         }
1502         if (n_rir == MAX_RIR_RANGES) {
1503                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1504                         ch_addr);
1505                 return -EINVAL;
1506         }
1507         rir_way = RIR_WAY(reg);
1508
1509         if (pvt->is_close_pg)
1510                 idx = (ch_addr >> 6);
1511         else
1512                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
1513         idx %= 1 << rir_way;
1514
1515         pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
1516                               rir_offset[n_rir][idx],
1517                               &reg);
1518         *rank = RIR_RNK_TGT(pvt->info.type, reg);
1519
1520         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1521                  n_rir,
1522                  ch_addr,
1523                  limit,
1524                  rir_way,
1525                  idx);
1526
1527         return 0;
1528 }
1529
1530 /****************************************************************************
1531         Device initialization routines: put/get, init/exit
1532  ****************************************************************************/
1533
1534 /*
1535  *      sbridge_put_all_devices 'put' all the devices that we have
1536  *                              reserved via 'get'
1537  */
1538 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1539 {
1540         int i;
1541
1542         edac_dbg(0, "\n");
1543         for (i = 0; i < sbridge_dev->n_devs; i++) {
1544                 struct pci_dev *pdev = sbridge_dev->pdev[i];
1545                 if (!pdev)
1546                         continue;
1547                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1548                          pdev->bus->number,
1549                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1550                 pci_dev_put(pdev);
1551         }
1552 }
1553
1554 static void sbridge_put_all_devices(void)
1555 {
1556         struct sbridge_dev *sbridge_dev, *tmp;
1557
1558         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1559                 sbridge_put_devices(sbridge_dev);
1560                 free_sbridge_dev(sbridge_dev);
1561         }
1562 }
1563
1564 static int sbridge_get_onedevice(struct pci_dev **prev,
1565                                  u8 *num_mc,
1566                                  const struct pci_id_table *table,
1567                                  const unsigned devno)
1568 {
1569         struct sbridge_dev *sbridge_dev;
1570         const struct pci_id_descr *dev_descr = &table->descr[devno];
1571         struct pci_dev *pdev = NULL;
1572         u8 bus = 0;
1573
1574         sbridge_printk(KERN_DEBUG,
1575                 "Seeking for: PCI ID %04x:%04x\n",
1576                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1577
1578         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1579                               dev_descr->dev_id, *prev);
1580
1581         if (!pdev) {
1582                 if (*prev) {
1583                         *prev = pdev;
1584                         return 0;
1585                 }
1586
1587                 if (dev_descr->optional)
1588                         return 0;
1589
1590                 /* if the HA wasn't found */
1591                 if (devno == 0)
1592                         return -ENODEV;
1593
1594                 sbridge_printk(KERN_INFO,
1595                         "Device not found: %04x:%04x\n",
1596                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1597
1598                 /* End of list, leave */
1599                 return -ENODEV;
1600         }
1601         bus = pdev->bus->number;
1602
1603         sbridge_dev = get_sbridge_dev(bus);
1604         if (!sbridge_dev) {
1605                 sbridge_dev = alloc_sbridge_dev(bus, table);
1606                 if (!sbridge_dev) {
1607                         pci_dev_put(pdev);
1608                         return -ENOMEM;
1609                 }
1610                 (*num_mc)++;
1611         }
1612
1613         if (sbridge_dev->pdev[devno]) {
1614                 sbridge_printk(KERN_ERR,
1615                         "Duplicated device for %04x:%04x\n",
1616                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1617                 pci_dev_put(pdev);
1618                 return -ENODEV;
1619         }
1620
1621         sbridge_dev->pdev[devno] = pdev;
1622
1623         /* Be sure that the device is enabled */
1624         if (unlikely(pci_enable_device(pdev) < 0)) {
1625                 sbridge_printk(KERN_ERR,
1626                         "Couldn't enable %04x:%04x\n",
1627                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1628                 return -ENODEV;
1629         }
1630
1631         edac_dbg(0, "Detected %04x:%04x\n",
1632                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1633
1634         /*
1635          * As stated on drivers/pci/search.c, the reference count for
1636          * @from is always decremented if it is not %NULL. So, as we need
1637          * to get all devices up to null, we need to do a get for the device
1638          */
1639         pci_dev_get(pdev);
1640
1641         *prev = pdev;
1642
1643         return 0;
1644 }
1645
1646 /*
1647  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
1648  *                           devices we want to reference for this driver.
1649  * @num_mc: pointer to the memory controllers count, to be incremented in case
1650  *          of success.
1651  * @table: model specific table
1652  *
1653  * returns 0 in case of success or error code
1654  */
1655 static int sbridge_get_all_devices(u8 *num_mc,
1656                                    const struct pci_id_table *table)
1657 {
1658         int i, rc;
1659         struct pci_dev *pdev = NULL;
1660
1661         while (table && table->descr) {
1662                 for (i = 0; i < table->n_devs; i++) {
1663                         pdev = NULL;
1664                         do {
1665                                 rc = sbridge_get_onedevice(&pdev, num_mc,
1666                                                            table, i);
1667                                 if (rc < 0) {
1668                                         if (i == 0) {
1669                                                 i = table->n_devs;
1670                                                 break;
1671                                         }
1672                                         sbridge_put_all_devices();
1673                                         return -ENODEV;
1674                                 }
1675                         } while (pdev);
1676                 }
1677                 table++;
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1684                                  struct sbridge_dev *sbridge_dev)
1685 {
1686         struct sbridge_pvt *pvt = mci->pvt_info;
1687         struct pci_dev *pdev;
1688         u8 saw_chan_mask = 0;
1689         int i;
1690
1691         for (i = 0; i < sbridge_dev->n_devs; i++) {
1692                 pdev = sbridge_dev->pdev[i];
1693                 if (!pdev)
1694                         continue;
1695
1696                 switch (pdev->device) {
1697                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1698                         pvt->pci_sad0 = pdev;
1699                         break;
1700                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1701                         pvt->pci_sad1 = pdev;
1702                         break;
1703                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1704                         pvt->pci_br0 = pdev;
1705                         break;
1706                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1707                         pvt->pci_ha0 = pdev;
1708                         break;
1709                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1710                         pvt->pci_ta = pdev;
1711                         break;
1712                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1713                         pvt->pci_ras = pdev;
1714                         break;
1715                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1716                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1717                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1718                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1719                 {
1720                         int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1721                         pvt->pci_tad[id] = pdev;
1722                         saw_chan_mask |= 1 << id;
1723                 }
1724                         break;
1725                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1726                         pvt->pci_ddrio = pdev;
1727                         break;
1728                 default:
1729                         goto error;
1730                 }
1731
1732                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1733                          pdev->vendor, pdev->device,
1734                          sbridge_dev->bus,
1735                          pdev);
1736         }
1737
1738         /* Check if everything were registered */
1739         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1740             !pvt-> pci_tad || !pvt->pci_ras  || !pvt->pci_ta)
1741                 goto enodev;
1742
1743         if (saw_chan_mask != 0x0f)
1744                 goto enodev;
1745         return 0;
1746
1747 enodev:
1748         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1749         return -ENODEV;
1750
1751 error:
1752         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1753                        PCI_VENDOR_ID_INTEL, pdev->device);
1754         return -EINVAL;
1755 }
1756
1757 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1758                                  struct sbridge_dev *sbridge_dev)
1759 {
1760         struct sbridge_pvt *pvt = mci->pvt_info;
1761         struct pci_dev *pdev;
1762         u8 saw_chan_mask = 0;
1763         int i;
1764
1765         for (i = 0; i < sbridge_dev->n_devs; i++) {
1766                 pdev = sbridge_dev->pdev[i];
1767                 if (!pdev)
1768                         continue;
1769
1770                 switch (pdev->device) {
1771                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1772                         pvt->pci_ha0 = pdev;
1773                         break;
1774                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1775                         pvt->pci_ta = pdev;
1776                         break;
1777                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1778                         pvt->pci_ras = pdev;
1779                         break;
1780                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1781                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
1782                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1783                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
1784                 {
1785                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1786                         pvt->pci_tad[id] = pdev;
1787                         saw_chan_mask |= 1 << id;
1788                 }
1789                         break;
1790                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1791                         pvt->pci_ddrio = pdev;
1792                         break;
1793                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
1794                         pvt->pci_ddrio = pdev;
1795                         break;
1796                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1797                         pvt->pci_sad0 = pdev;
1798                         break;
1799                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1800                         pvt->pci_br0 = pdev;
1801                         break;
1802                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1803                         pvt->pci_br1 = pdev;
1804                         break;
1805                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1806                         pvt->pci_ha1 = pdev;
1807                         break;
1808                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1809                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
1810                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
1811                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
1812                 {
1813                         int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
1814                         pvt->pci_tad[id] = pdev;
1815                         saw_chan_mask |= 1 << id;
1816                 }
1817                         break;
1818                 default:
1819                         goto error;
1820                 }
1821
1822                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1823                          sbridge_dev->bus,
1824                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1825                          pdev);
1826         }
1827
1828         /* Check if everything were registered */
1829         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1830             !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras  ||
1831             !pvt->pci_ta)
1832                 goto enodev;
1833
1834         if (saw_chan_mask != 0x0f && /* -EN */
1835             saw_chan_mask != 0x33 && /* -EP */
1836             saw_chan_mask != 0xff)   /* -EX */
1837                 goto enodev;
1838         return 0;
1839
1840 enodev:
1841         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1842         return -ENODEV;
1843
1844 error:
1845         sbridge_printk(KERN_ERR,
1846                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1847                         pdev->device);
1848         return -EINVAL;
1849 }
1850
1851 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1852                                  struct sbridge_dev *sbridge_dev)
1853 {
1854         struct sbridge_pvt *pvt = mci->pvt_info;
1855         struct pci_dev *pdev;
1856         u8 saw_chan_mask = 0;
1857         int i;
1858
1859         /* there's only one device per system; not tied to any bus */
1860         if (pvt->info.pci_vtd == NULL)
1861                 /* result will be checked later */
1862                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1863                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1864                                                    NULL);
1865
1866         for (i = 0; i < sbridge_dev->n_devs; i++) {
1867                 pdev = sbridge_dev->pdev[i];
1868                 if (!pdev)
1869                         continue;
1870
1871                 switch (pdev->device) {
1872                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1873                         pvt->pci_sad0 = pdev;
1874                         break;
1875                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1876                         pvt->pci_sad1 = pdev;
1877                         break;
1878                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1879                         pvt->pci_ha0 = pdev;
1880                         break;
1881                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1882                         pvt->pci_ta = pdev;
1883                         break;
1884                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1885                         pvt->pci_ras = pdev;
1886                         break;
1887                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
1888                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
1889                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
1890                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
1891                 {
1892                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
1893
1894                         pvt->pci_tad[id] = pdev;
1895                         saw_chan_mask |= 1 << id;
1896                 }
1897                         break;
1898                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1899                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1900                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
1901                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
1902                 {
1903                         int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
1904
1905                         pvt->pci_tad[id] = pdev;
1906                         saw_chan_mask |= 1 << id;
1907                 }
1908                         break;
1909                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1910                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
1911                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
1912                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
1913                         if (!pvt->pci_ddrio)
1914                                 pvt->pci_ddrio = pdev;
1915                         break;
1916                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1917                         pvt->pci_ha1 = pdev;
1918                         break;
1919                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1920                         pvt->pci_ha1_ta = pdev;
1921                         break;
1922                 default:
1923                         break;
1924                 }
1925
1926                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1927                          sbridge_dev->bus,
1928                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1929                          pdev);
1930         }
1931
1932         /* Check if everything were registered */
1933         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1934             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
1935                 goto enodev;
1936
1937         if (saw_chan_mask != 0x0f && /* -EN */
1938             saw_chan_mask != 0x33 && /* -EP */
1939             saw_chan_mask != 0xff)   /* -EX */
1940                 goto enodev;
1941         return 0;
1942
1943 enodev:
1944         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1945         return -ENODEV;
1946 }
1947
1948 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1949                                  struct sbridge_dev *sbridge_dev)
1950 {
1951         struct sbridge_pvt *pvt = mci->pvt_info;
1952         struct pci_dev *pdev;
1953         u8 saw_chan_mask = 0;
1954         int i;
1955
1956         /* there's only one device per system; not tied to any bus */
1957         if (pvt->info.pci_vtd == NULL)
1958                 /* result will be checked later */
1959                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1960                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
1961                                                    NULL);
1962
1963         for (i = 0; i < sbridge_dev->n_devs; i++) {
1964                 pdev = sbridge_dev->pdev[i];
1965                 if (!pdev)
1966                         continue;
1967
1968                 switch (pdev->device) {
1969                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
1970                         pvt->pci_sad0 = pdev;
1971                         break;
1972                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
1973                         pvt->pci_sad1 = pdev;
1974                         break;
1975                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
1976                         pvt->pci_ha0 = pdev;
1977                         break;
1978                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
1979                         pvt->pci_ta = pdev;
1980                         break;
1981                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
1982                         pvt->pci_ras = pdev;
1983                         break;
1984                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1985                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1986                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1987                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
1988                 {
1989                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
1990                         pvt->pci_tad[id] = pdev;
1991                         saw_chan_mask |= 1 << id;
1992                 }
1993                         break;
1994                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
1995                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
1996                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
1997                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
1998                 {
1999                         int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2000                         pvt->pci_tad[id] = pdev;
2001                         saw_chan_mask |= 1 << id;
2002                 }
2003                         break;
2004                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2005                         pvt->pci_ddrio = pdev;
2006                         break;
2007                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2008                         pvt->pci_ha1 = pdev;
2009                         break;
2010                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2011                         pvt->pci_ha1_ta = pdev;
2012                         break;
2013                 default:
2014                         break;
2015                 }
2016
2017                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2018                          sbridge_dev->bus,
2019                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2020                          pdev);
2021         }
2022
2023         /* Check if everything were registered */
2024         if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2025             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2026                 goto enodev;
2027
2028         if (saw_chan_mask != 0x0f && /* -EN */
2029             saw_chan_mask != 0x33 && /* -EP */
2030             saw_chan_mask != 0xff)   /* -EX */
2031                 goto enodev;
2032         return 0;
2033
2034 enodev:
2035         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2036         return -ENODEV;
2037 }
2038
2039 /****************************************************************************
2040                         Error check routines
2041  ****************************************************************************/
2042
2043 /*
2044  * While Sandy Bridge has error count registers, SMI BIOS read values from
2045  * and resets the counters. So, they are not reliable for the OS to read
2046  * from them. So, we have no option but to just trust on whatever MCE is
2047  * telling us about the errors.
2048  */
2049 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2050                                     const struct mce *m)
2051 {
2052         struct mem_ctl_info *new_mci;
2053         struct sbridge_pvt *pvt = mci->pvt_info;
2054         enum hw_event_mc_err_type tp_event;
2055         char *type, *optype, msg[256];
2056         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2057         bool overflow = GET_BITFIELD(m->status, 62, 62);
2058         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2059         bool recoverable;
2060         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2061         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2062         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2063         u32 channel = GET_BITFIELD(m->status, 0, 3);
2064         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2065         long channel_mask, first_channel;
2066         u8  rank, socket, ha;
2067         int rc, dimm;
2068         char *area_type = NULL;
2069
2070         if (pvt->info.type != SANDY_BRIDGE)
2071                 recoverable = true;
2072         else
2073                 recoverable = GET_BITFIELD(m->status, 56, 56);
2074
2075         if (uncorrected_error) {
2076                 if (ripv) {
2077                         type = "FATAL";
2078                         tp_event = HW_EVENT_ERR_FATAL;
2079                 } else {
2080                         type = "NON_FATAL";
2081                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2082                 }
2083         } else {
2084                 type = "CORRECTED";
2085                 tp_event = HW_EVENT_ERR_CORRECTED;
2086         }
2087
2088         /*
2089          * According with Table 15-9 of the Intel Architecture spec vol 3A,
2090          * memory errors should fit in this mask:
2091          *      000f 0000 1mmm cccc (binary)
2092          * where:
2093          *      f = Correction Report Filtering Bit. If 1, subsequent errors
2094          *          won't be shown
2095          *      mmm = error type
2096          *      cccc = channel
2097          * If the mask doesn't match, report an error to the parsing logic
2098          */
2099         if (! ((errcode & 0xef80) == 0x80)) {
2100                 optype = "Can't parse: it is not a mem";
2101         } else {
2102                 switch (optypenum) {
2103                 case 0:
2104                         optype = "generic undef request error";
2105                         break;
2106                 case 1:
2107                         optype = "memory read error";
2108                         break;
2109                 case 2:
2110                         optype = "memory write error";
2111                         break;
2112                 case 3:
2113                         optype = "addr/cmd error";
2114                         break;
2115                 case 4:
2116                         optype = "memory scrubbing error";
2117                         break;
2118                 default:
2119                         optype = "reserved";
2120                         break;
2121                 }
2122         }
2123
2124         /* Only decode errors with an valid address (ADDRV) */
2125         if (!GET_BITFIELD(m->status, 58, 58))
2126                 return;
2127
2128         rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2129                                    &channel_mask, &rank, &area_type, msg);
2130         if (rc < 0)
2131                 goto err_parsing;
2132         new_mci = get_mci_for_node_id(socket);
2133         if (!new_mci) {
2134                 strcpy(msg, "Error: socket got corrupted!");
2135                 goto err_parsing;
2136         }
2137         mci = new_mci;
2138         pvt = mci->pvt_info;
2139
2140         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2141
2142         if (rank < 4)
2143                 dimm = 0;
2144         else if (rank < 8)
2145                 dimm = 1;
2146         else
2147                 dimm = 2;
2148
2149
2150         /*
2151          * FIXME: On some memory configurations (mirror, lockstep), the
2152          * Memory Controller can't point the error to a single DIMM. The
2153          * EDAC core should be handling the channel mask, in order to point
2154          * to the group of dimm's where the error may be happening.
2155          */
2156         if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2157                 channel = first_channel;
2158
2159         snprintf(msg, sizeof(msg),
2160                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
2161                  overflow ? " OVERFLOW" : "",
2162                  (uncorrected_error && recoverable) ? " recoverable" : "",
2163                  area_type,
2164                  mscod, errcode,
2165                  socket, ha,
2166                  channel_mask,
2167                  rank);
2168
2169         edac_dbg(0, "%s\n", msg);
2170
2171         /* FIXME: need support for channel mask */
2172
2173         if (channel == CHANNEL_UNSPECIFIED)
2174                 channel = -1;
2175
2176         /* Call the helper to output message */
2177         edac_mc_handle_error(tp_event, mci, core_err_cnt,
2178                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2179                              4*ha+channel, dimm, -1,
2180                              optype, msg);
2181         return;
2182 err_parsing:
2183         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
2184                              -1, -1, -1,
2185                              msg, "");
2186
2187 }
2188
2189 /*
2190  *      sbridge_check_error     Retrieve and process errors reported by the
2191  *                              hardware. Called by the Core module.
2192  */
2193 static void sbridge_check_error(struct mem_ctl_info *mci)
2194 {
2195         struct sbridge_pvt *pvt = mci->pvt_info;
2196         int i;
2197         unsigned count = 0;
2198         struct mce *m;
2199
2200         /*
2201          * MCE first step: Copy all mce errors into a temporary buffer
2202          * We use a double buffering here, to reduce the risk of
2203          * loosing an error.
2204          */
2205         smp_rmb();
2206         count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2207                 % MCE_LOG_LEN;
2208         if (!count)
2209                 return;
2210
2211         m = pvt->mce_outentry;
2212         if (pvt->mce_in + count > MCE_LOG_LEN) {
2213                 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2214
2215                 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2216                 smp_wmb();
2217                 pvt->mce_in = 0;
2218                 count -= l;
2219                 m += l;
2220         }
2221         memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2222         smp_wmb();
2223         pvt->mce_in += count;
2224
2225         smp_rmb();
2226         if (pvt->mce_overrun) {
2227                 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2228                               pvt->mce_overrun);
2229                 smp_wmb();
2230                 pvt->mce_overrun = 0;
2231         }
2232
2233         /*
2234          * MCE second step: parse errors and display
2235          */
2236         for (i = 0; i < count; i++)
2237                 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2238 }
2239
2240 /*
2241  * sbridge_mce_check_error      Replicates mcelog routine to get errors
2242  *                              This routine simply queues mcelog errors, and
2243  *                              return. The error itself should be handled later
2244  *                              by sbridge_check_error.
2245  * WARNING: As this routine should be called at NMI time, extra care should
2246  * be taken to avoid deadlocks, and to be as fast as possible.
2247  */
2248 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2249                                    void *data)
2250 {
2251         struct mce *mce = (struct mce *)data;
2252         struct mem_ctl_info *mci;
2253         struct sbridge_pvt *pvt;
2254         char *type;
2255
2256         if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2257                 return NOTIFY_DONE;
2258
2259         mci = get_mci_for_node_id(mce->socketid);
2260         if (!mci)
2261                 return NOTIFY_DONE;
2262         pvt = mci->pvt_info;
2263
2264         /*
2265          * Just let mcelog handle it if the error is
2266          * outside the memory controller. A memory error
2267          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2268          * bit 12 has an special meaning.
2269          */
2270         if ((mce->status & 0xefff) >> 7 != 1)
2271                 return NOTIFY_DONE;
2272
2273         if (mce->mcgstatus & MCG_STATUS_MCIP)
2274                 type = "Exception";
2275         else
2276                 type = "Event";
2277
2278         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
2279
2280         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2281                           "Bank %d: %016Lx\n", mce->extcpu, type,
2282                           mce->mcgstatus, mce->bank, mce->status);
2283         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2284         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2285         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
2286
2287         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2288                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2289                           mce->time, mce->socketid, mce->apicid);
2290
2291         smp_rmb();
2292         if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2293                 smp_wmb();
2294                 pvt->mce_overrun++;
2295                 return NOTIFY_DONE;
2296         }
2297
2298         /* Copy memory error at the ringbuffer */
2299         memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2300         smp_wmb();
2301         pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2302
2303         /* Handle fatal errors immediately */
2304         if (mce->mcgstatus & 1)
2305                 sbridge_check_error(mci);
2306
2307         /* Advice mcelog that the error were handled */
2308         return NOTIFY_STOP;
2309 }
2310
2311 static struct notifier_block sbridge_mce_dec = {
2312         .notifier_call      = sbridge_mce_check_error,
2313 };
2314
2315 /****************************************************************************
2316                         EDAC register/unregister logic
2317  ****************************************************************************/
2318
2319 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2320 {
2321         struct mem_ctl_info *mci = sbridge_dev->mci;
2322         struct sbridge_pvt *pvt;
2323
2324         if (unlikely(!mci || !mci->pvt_info)) {
2325                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
2326
2327                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2328                 return;
2329         }
2330
2331         pvt = mci->pvt_info;
2332
2333         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2334                  mci, &sbridge_dev->pdev[0]->dev);
2335
2336         /* Remove MC sysfs nodes */
2337         edac_mc_del_mc(mci->pdev);
2338
2339         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2340         kfree(mci->ctl_name);
2341         edac_mc_free(mci);
2342         sbridge_dev->mci = NULL;
2343 }
2344
2345 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
2346 {
2347         struct mem_ctl_info *mci;
2348         struct edac_mc_layer layers[2];
2349         struct sbridge_pvt *pvt;
2350         struct pci_dev *pdev = sbridge_dev->pdev[0];
2351         int rc;
2352
2353         /* Check the number of active and not disabled channels */
2354         rc = check_if_ecc_is_active(sbridge_dev->bus, type);
2355         if (unlikely(rc < 0))
2356                 return rc;
2357
2358         /* allocate a new MC control structure */
2359         layers[0].type = EDAC_MC_LAYER_CHANNEL;
2360         layers[0].size = NUM_CHANNELS;
2361         layers[0].is_virt_csrow = false;
2362         layers[1].type = EDAC_MC_LAYER_SLOT;
2363         layers[1].size = MAX_DIMMS;
2364         layers[1].is_virt_csrow = true;
2365         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
2366                             sizeof(*pvt));
2367
2368         if (unlikely(!mci))
2369                 return -ENOMEM;
2370
2371         edac_dbg(0, "MC: mci = %p, dev = %p\n",
2372                  mci, &pdev->dev);
2373
2374         pvt = mci->pvt_info;
2375         memset(pvt, 0, sizeof(*pvt));
2376
2377         /* Associate sbridge_dev and mci for future usage */
2378         pvt->sbridge_dev = sbridge_dev;
2379         sbridge_dev->mci = mci;
2380
2381         mci->mtype_cap = MEM_FLAG_DDR3;
2382         mci->edac_ctl_cap = EDAC_FLAG_NONE;
2383         mci->edac_cap = EDAC_FLAG_NONE;
2384         mci->mod_name = "sbridge_edac.c";
2385         mci->mod_ver = SBRIDGE_REVISION;
2386         mci->dev_name = pci_name(pdev);
2387         mci->ctl_page_to_phys = NULL;
2388
2389         /* Set the function pointer to an actual operation function */
2390         mci->edac_check = sbridge_check_error;
2391
2392         pvt->info.type = type;
2393         switch (type) {
2394         case IVY_BRIDGE:
2395                 pvt->info.rankcfgr = IB_RANK_CFG_A;
2396                 pvt->info.get_tolm = ibridge_get_tolm;
2397                 pvt->info.get_tohm = ibridge_get_tohm;
2398                 pvt->info.dram_rule = ibridge_dram_rule;
2399                 pvt->info.get_memory_type = get_memory_type;
2400                 pvt->info.get_node_id = get_node_id;
2401                 pvt->info.rir_limit = rir_limit;
2402                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2403                 pvt->info.interleave_list = ibridge_interleave_list;
2404                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2405                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2406                 pvt->info.get_width = ibridge_get_width;
2407                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2408
2409                 /* Store pci devices at mci for faster access */
2410                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2411                 if (unlikely(rc < 0))
2412                         goto fail0;
2413                 break;
2414         case SANDY_BRIDGE:
2415                 pvt->info.rankcfgr = SB_RANK_CFG_A;
2416                 pvt->info.get_tolm = sbridge_get_tolm;
2417                 pvt->info.get_tohm = sbridge_get_tohm;
2418                 pvt->info.dram_rule = sbridge_dram_rule;
2419                 pvt->info.get_memory_type = get_memory_type;
2420                 pvt->info.get_node_id = get_node_id;
2421                 pvt->info.rir_limit = rir_limit;
2422                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2423                 pvt->info.interleave_list = sbridge_interleave_list;
2424                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2425                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
2426                 pvt->info.get_width = sbridge_get_width;
2427                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2428
2429                 /* Store pci devices at mci for faster access */
2430                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2431                 if (unlikely(rc < 0))
2432                         goto fail0;
2433                 break;
2434         case HASWELL:
2435                 /* rankcfgr isn't used */
2436                 pvt->info.get_tolm = haswell_get_tolm;
2437                 pvt->info.get_tohm = haswell_get_tohm;
2438                 pvt->info.dram_rule = ibridge_dram_rule;
2439                 pvt->info.get_memory_type = haswell_get_memory_type;
2440                 pvt->info.get_node_id = haswell_get_node_id;
2441                 pvt->info.rir_limit = haswell_rir_limit;
2442                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2443                 pvt->info.interleave_list = ibridge_interleave_list;
2444                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2445                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2446                 pvt->info.get_width = ibridge_get_width;
2447                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
2448
2449                 /* Store pci devices at mci for faster access */
2450                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2451                 if (unlikely(rc < 0))
2452                         goto fail0;
2453                 break;
2454         case BROADWELL:
2455                 /* rankcfgr isn't used */
2456                 pvt->info.get_tolm = haswell_get_tolm;
2457                 pvt->info.get_tohm = haswell_get_tohm;
2458                 pvt->info.dram_rule = ibridge_dram_rule;
2459                 pvt->info.get_memory_type = haswell_get_memory_type;
2460                 pvt->info.get_node_id = haswell_get_node_id;
2461                 pvt->info.rir_limit = haswell_rir_limit;
2462                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2463                 pvt->info.interleave_list = ibridge_interleave_list;
2464                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2465                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
2466                 pvt->info.get_width = broadwell_get_width;
2467                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2468
2469                 /* Store pci devices at mci for faster access */
2470                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2471                 if (unlikely(rc < 0))
2472                         goto fail0;
2473                 break;
2474         }
2475
2476         /* Get dimm basic config and the memory layout */
2477         get_dimm_config(mci);
2478         get_memory_layout(mci);
2479
2480         /* record ptr to the generic device */
2481         mci->pdev = &pdev->dev;
2482
2483         /* add this new MC control structure to EDAC's list of MCs */
2484         if (unlikely(edac_mc_add_mc(mci))) {
2485                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2486                 rc = -EINVAL;
2487                 goto fail0;
2488         }
2489
2490         return 0;
2491
2492 fail0:
2493         kfree(mci->ctl_name);
2494         edac_mc_free(mci);
2495         sbridge_dev->mci = NULL;
2496         return rc;
2497 }
2498
2499 /*
2500  *      sbridge_probe   Probe for ONE instance of device to see if it is
2501  *                      present.
2502  *      return:
2503  *              0 for FOUND a device
2504  *              < 0 for error code
2505  */
2506
2507 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2508 {
2509         int rc = -ENODEV;
2510         u8 mc, num_mc = 0;
2511         struct sbridge_dev *sbridge_dev;
2512         enum type type = SANDY_BRIDGE;
2513
2514         /* get the pci devices we want to reserve for our use */
2515         mutex_lock(&sbridge_edac_lock);
2516
2517         /*
2518          * All memory controllers are allocated at the first pass.
2519          */
2520         if (unlikely(probed >= 1)) {
2521                 mutex_unlock(&sbridge_edac_lock);
2522                 return -ENODEV;
2523         }
2524         probed++;
2525
2526         switch (pdev->device) {
2527         case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2528                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2529                 type = IVY_BRIDGE;
2530                 break;
2531         case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2532                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2533                 type = SANDY_BRIDGE;
2534                 break;
2535         case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2536                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2537                 type = HASWELL;
2538                 break;
2539         case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2540                 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2541                 type = BROADWELL;
2542                 break;
2543         }
2544         if (unlikely(rc < 0)) {
2545                 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
2546                 goto fail0;
2547         }
2548
2549         mc = 0;
2550
2551         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
2552                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2553                          mc, mc + 1, num_mc);
2554
2555                 sbridge_dev->mc = mc++;
2556                 rc = sbridge_register_mci(sbridge_dev, type);
2557                 if (unlikely(rc < 0))
2558                         goto fail1;
2559         }
2560
2561         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
2562
2563         mutex_unlock(&sbridge_edac_lock);
2564         return 0;
2565
2566 fail1:
2567         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2568                 sbridge_unregister_mci(sbridge_dev);
2569
2570         sbridge_put_all_devices();
2571 fail0:
2572         mutex_unlock(&sbridge_edac_lock);
2573         return rc;
2574 }
2575
2576 /*
2577  *      sbridge_remove  destructor for one instance of device
2578  *
2579  */
2580 static void sbridge_remove(struct pci_dev *pdev)
2581 {
2582         struct sbridge_dev *sbridge_dev;
2583
2584         edac_dbg(0, "\n");
2585
2586         /*
2587          * we have a trouble here: pdev value for removal will be wrong, since
2588          * it will point to the X58 register used to detect that the machine
2589          * is a Nehalem or upper design. However, due to the way several PCI
2590          * devices are grouped together to provide MC functionality, we need
2591          * to use a different method for releasing the devices
2592          */
2593
2594         mutex_lock(&sbridge_edac_lock);
2595
2596         if (unlikely(!probed)) {
2597                 mutex_unlock(&sbridge_edac_lock);
2598                 return;
2599         }
2600
2601         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2602                 sbridge_unregister_mci(sbridge_dev);
2603
2604         /* Release PCI resources */
2605         sbridge_put_all_devices();
2606
2607         probed--;
2608
2609         mutex_unlock(&sbridge_edac_lock);
2610 }
2611
2612 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2613
2614 /*
2615  *      sbridge_driver  pci_driver structure for this module
2616  *
2617  */
2618 static struct pci_driver sbridge_driver = {
2619         .name     = "sbridge_edac",
2620         .probe    = sbridge_probe,
2621         .remove   = sbridge_remove,
2622         .id_table = sbridge_pci_tbl,
2623 };
2624
2625 /*
2626  *      sbridge_init            Module entry function
2627  *                      Try to initialize this module for its devices
2628  */
2629 static int __init sbridge_init(void)
2630 {
2631         int pci_rc;
2632
2633         edac_dbg(2, "\n");
2634
2635         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2636         opstate_init();
2637
2638         pci_rc = pci_register_driver(&sbridge_driver);
2639         if (pci_rc >= 0) {
2640                 mce_register_decode_chain(&sbridge_mce_dec);
2641                 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2642                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
2643                 return 0;
2644         }
2645
2646         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2647                       pci_rc);
2648
2649         return pci_rc;
2650 }
2651
2652 /*
2653  *      sbridge_exit()  Module exit function
2654  *                      Unregister the driver
2655  */
2656 static void __exit sbridge_exit(void)
2657 {
2658         edac_dbg(2, "\n");
2659         pci_unregister_driver(&sbridge_driver);
2660         mce_unregister_decode_chain(&sbridge_mce_dec);
2661 }
2662
2663 module_init(sbridge_init);
2664 module_exit(sbridge_exit);
2665
2666 module_param(edac_op_state, int, 0444);
2667 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2668
2669 MODULE_LICENSE("GPL");
2670 MODULE_AUTHOR("Mauro Carvalho Chehab");
2671 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2672 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
2673                    SBRIDGE_REVISION);