drivers/edac/ie31200_edac.c

   1 /*
   2  * Intel E3-1200
   3  * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
   4  *
   5  * Support for the E3-1200 processor family. Heavily based on previous
   6  * Intel EDAC drivers.
   7  *
   8  * Since the DRAM controller is on the cpu chip, we can use its PCI device
   9  * id to identify these processors.
  10  *
  11  * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/)
  12  *
  13  * 0108: Xeon E3-1200 Processor Family DRAM Controller
  14  * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
  15  * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
  16  * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
  17  * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
  18  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
  19  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
  20  *
  21  * Based on Intel specification:
  22  * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
  23  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
  24  *
  25  * According to the above datasheet (p.16):
  26  * "
  27  * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
  28  * requests that cross a DW boundary.
  29  * "
  30  *
  31  * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
  32  * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
  33  * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/edac.h>
  41
  42 #include <linux/io-64-nonatomic-lo-hi.h>
  43 #include "edac_core.h"
  44
  45 #define IE31200_REVISION "1.0"
  46 #define EDAC_MOD_STR "ie31200_edac"
  47
  48 #define ie31200_printk(level, fmt, arg...) \
  49         edac_printk(level, "ie31200", fmt, ##arg)
  50
  51 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
  52 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
  53 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
  54 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
  55 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
  56 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
  57 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
  58
  59 #define IE31200_DIMMS                   4
  60 #define IE31200_RANKS                   8
  61 #define IE31200_RANKS_PER_CHANNEL       4
  62 #define IE31200_DIMMS_PER_CHANNEL       2
  63 #define IE31200_CHANNELS                2
  64
  65 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
  66 #define IE31200_MCHBAR_LOW              0x48
  67 #define IE31200_MCHBAR_HIGH             0x4c
  68 #define IE31200_MCHBAR_MASK             GENMASK_ULL(38, 15)
  69 #define IE31200_MMR_WINDOW_SIZE         BIT(15)
  70
  71 /*
  72  * Error Status Register (16b)
  73  *
  74  * 15    reserved
  75  * 14    Isochronous TBWRR Run Behind FIFO Full
  76  *       (ITCV)
  77  * 13    Isochronous TBWRR Run Behind FIFO Put
  78  *       (ITSTV)
  79  * 12    reserved
  80  * 11    MCH Thermal Sensor Event
  81  *       for SMI/SCI/SERR (GTSE)
  82  * 10    reserved
  83  *  9    LOCK to non-DRAM Memory Flag (LCKF)
  84  *  8    reserved
  85  *  7    DRAM Throttle Flag (DTF)
  86  *  6:2  reserved
  87  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
  88  *  0    Single-bit DRAM ECC Error Flag (DSERR)
  89  */
  90 #define IE31200_ERRSTS                  0xc8
  91 #define IE31200_ERRSTS_UE               BIT(1)
  92 #define IE31200_ERRSTS_CE               BIT(0)
  93 #define IE31200_ERRSTS_BITS             (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
  94
  95 /*
  96  * Channel 0 ECC Error Log (64b)
  97  *
  98  * 63:48 Error Column Address (ERRCOL)
  99  * 47:32 Error Row Address (ERRROW)
 100  * 31:29 Error Bank Address (ERRBANK)
 101  * 28:27 Error Rank Address (ERRRANK)
 102  * 26:24 reserved
 103  * 23:16 Error Syndrome (ERRSYND)
 104  * 15: 2 reserved
 105  *    1  Multiple Bit Error Status (MERRSTS)
 106  *    0  Correctable Error Status (CERRSTS)
 107  */
 108 #define IE31200_C0ECCERRLOG                     0x40c8
 109 #define IE31200_C1ECCERRLOG                     0x44c8
 110 #define IE31200_ECCERRLOG_CE                    BIT(0)
 111 #define IE31200_ECCERRLOG_UE                    BIT(1)
 112 #define IE31200_ECCERRLOG_RANK_BITS             GENMASK_ULL(28, 27)
 113 #define IE31200_ECCERRLOG_RANK_SHIFT            27
 114 #define IE31200_ECCERRLOG_SYNDROME_BITS         GENMASK_ULL(23, 16)
 115 #define IE31200_ECCERRLOG_SYNDROME_SHIFT        16
 116
 117 #define IE31200_ECCERRLOG_SYNDROME(log)            \
 118         ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
 119          IE31200_ECCERRLOG_SYNDROME_SHIFT)
 120
 121 #define IE31200_CAPID0                  0xe4
 122 #define IE31200_CAPID0_PDCD             BIT(4)
 123 #define IE31200_CAPID0_DDPCD            BIT(6)
 124 #define IE31200_CAPID0_ECC              BIT(1)
 125
 126 #define IE31200_MAD_DIMM_0_OFFSET       0x5004
 127 #define IE31200_MAD_DIMM_SIZE           GENMASK_ULL(7, 0)
 128 #define IE31200_MAD_DIMM_A_RANK         BIT(17)
 129 #define IE31200_MAD_DIMM_A_WIDTH        BIT(19)
 130
 131 #define IE31200_PAGES(n)                (n << (28 - PAGE_SHIFT))
 132
 133 static int nr_channels;
 134 static struct pci_dev *mci_pdev;
 135 static int ie31200_registered = 1;
 136
 137 struct ie31200_priv {
 138         void __iomem *window;
 139 };
 140
 141 enum ie31200_chips {
 142         IE31200 = 0,
 143 };
 144
 145 struct ie31200_dev_info {
 146         const char *ctl_name;
 147 };
 148
 149 struct ie31200_error_info {
 150         u16 errsts;
 151         u16 errsts2;
 152         u64 eccerrlog[IE31200_CHANNELS];
 153 };
 154
 155 static const struct ie31200_dev_info ie31200_devs[] = {
 156         [IE31200] = {
 157                 .ctl_name = "IE31200"
 158         },
 159 };
 160
 161 struct dimm_data {
 162         u8 size; /* in 256MB multiples */
 163         u8 dual_rank : 1,
 164            x16_width : 1; /* 0 means x8 width */
 165 };
 166
 167 static int how_many_channels(struct pci_dev *pdev)
 168 {
 169         int n_channels;
 170         unsigned char capid0_2b; /* 2nd byte of CAPID0 */
 171
 172         pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
 173
 174         /* check PDCD: Dual Channel Disable */
 175         if (capid0_2b & IE31200_CAPID0_PDCD) {
 176                 edac_dbg(0, "In single channel mode\n");
 177                 n_channels = 1;
 178         } else {
 179                 edac_dbg(0, "In dual channel mode\n");
 180                 n_channels = 2;
 181         }
 182
 183         /* check DDPCD - check if both channels are filled */
 184         if (capid0_2b & IE31200_CAPID0_DDPCD)
 185                 edac_dbg(0, "2 DIMMS per channel disabled\n");
 186         else
 187                 edac_dbg(0, "2 DIMMS per channel enabled\n");
 188
 189         return n_channels;
 190 }
 191
 192 static bool ecc_capable(struct pci_dev *pdev)
 193 {
 194         unsigned char capid0_4b; /* 4th byte of CAPID0 */
 195
 196         pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
 197         if (capid0_4b & IE31200_CAPID0_ECC)
 198                 return false;
 199         return true;
 200 }
 201
 202 static int eccerrlog_row(int channel, u64 log)
 203 {
 204         int rank = ((log & IE31200_ECCERRLOG_RANK_BITS) >>
 205                 IE31200_ECCERRLOG_RANK_SHIFT);
 206         return rank | (channel * IE31200_RANKS_PER_CHANNEL);
 207 }
 208
 209 static void ie31200_clear_error_info(struct mem_ctl_info *mci)
 210 {
 211         /*
 212          * Clear any error bits.
 213          * (Yes, we really clear bits by writing 1 to them.)
 214          */
 215         pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
 216                          IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
 217 }
 218
 219 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
 220                                              struct ie31200_error_info *info)
 221 {
 222         struct pci_dev *pdev;
 223         struct ie31200_priv *priv = mci->pvt_info;
 224         void __iomem *window = priv->window;
 225
 226         pdev = to_pci_dev(mci->pdev);
 227
 228         /*
 229          * This is a mess because there is no atomic way to read all the
 230          * registers at once and the registers can transition from CE being
 231          * overwritten by UE.
 232          */
 233         pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
 234         if (!(info->errsts & IE31200_ERRSTS_BITS))
 235                 return;
 236
 237         info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
 238         if (nr_channels == 2)
 239                 info->eccerrlog[1] = lo_hi_readq(window + IE31200_C1ECCERRLOG);
 240
 241         pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
 242
 243         /*
 244          * If the error is the same for both reads then the first set
 245          * of reads is valid.  If there is a change then there is a CE
 246          * with no info and the second set of reads is valid and
 247          * should be UE info.
 248          */
 249         if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
 250                 info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
 251                 if (nr_channels == 2)
 252                         info->eccerrlog[1] =
 253                                 lo_hi_readq(window + IE31200_C1ECCERRLOG);
 254         }
 255
 256         ie31200_clear_error_info(mci);
 257 }
 258
 259 static void ie31200_process_error_info(struct mem_ctl_info *mci,
 260                                        struct ie31200_error_info *info)
 261 {
 262         int channel;
 263         u64 log;
 264
 265         if (!(info->errsts & IE31200_ERRSTS_BITS))
 266                 return;
 267
 268         if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
 269                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
 270                                      -1, -1, -1, "UE overwrote CE", "");
 271                 info->errsts = info->errsts2;
 272         }
 273
 274         for (channel = 0; channel < nr_channels; channel++) {
 275                 log = info->eccerrlog[channel];
 276                 if (log & IE31200_ECCERRLOG_UE) {
 277                         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 278                                              0, 0, 0,
 279                                              eccerrlog_row(channel, log),
 280                                              channel, -1,
 281                                              "ie31200 UE", "");
 282                 } else if (log & IE31200_ECCERRLOG_CE) {
 283                         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 284                                              0, 0,
 285                                              IE31200_ECCERRLOG_SYNDROME(log),
 286                                              eccerrlog_row(channel, log),
 287                                              channel, -1,
 288                                              "ie31200 CE", "");
 289                 }
 290         }
 291 }
 292
 293 static void ie31200_check(struct mem_ctl_info *mci)
 294 {
 295         struct ie31200_error_info info;
 296
 297         edac_dbg(1, "MC%d\n", mci->mc_idx);
 298         ie31200_get_and_clear_error_info(mci, &info);
 299         ie31200_process_error_info(mci, &info);
 300 }
 301
 302 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
 303 {
 304         union {
 305                 u64 mchbar;
 306                 struct {
 307                         u32 mchbar_low;
 308                         u32 mchbar_high;
 309                 };
 310         } u;
 311         void __iomem *window;
 312
 313         pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
 314         pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
 315         u.mchbar &= IE31200_MCHBAR_MASK;
 316
 317         if (u.mchbar != (resource_size_t)u.mchbar) {
 318                 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
 319                                (unsigned long long)u.mchbar);
 320                 return NULL;
 321         }
 322
 323         window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
 324         if (!window)
 325                 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
 326                                (unsigned long long)u.mchbar);
 327
 328         return window;
 329 }
 330
 331 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
 332 {
 333         int i, j, ret;
 334         struct mem_ctl_info *mci = NULL;
 335         struct edac_mc_layer layers[2];
 336         struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
 337         void __iomem *window;
 338         struct ie31200_priv *priv;
 339         u32 addr_decode;
 340
 341         edac_dbg(0, "MC:\n");
 342
 343         if (!ecc_capable(pdev)) {
 344                 ie31200_printk(KERN_INFO, "No ECC support\n");
 345                 return -ENODEV;
 346         }
 347
 348         nr_channels = how_many_channels(pdev);
 349         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 350         layers[0].size = IE31200_DIMMS;
 351         layers[0].is_virt_csrow = true;
 352         layers[1].type = EDAC_MC_LAYER_CHANNEL;
 353         layers[1].size = nr_channels;
 354         layers[1].is_virt_csrow = false;
 355         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 356                             sizeof(struct ie31200_priv));
 357         if (!mci)
 358                 return -ENOMEM;
 359
 360         window = ie31200_map_mchbar(pdev);
 361         if (!window) {
 362                 ret = -ENODEV;
 363                 goto fail_free;
 364         }
 365
 366         edac_dbg(3, "MC: init mci\n");
 367         mci->pdev = &pdev->dev;
 368         mci->mtype_cap = MEM_FLAG_DDR3;
 369         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 370         mci->edac_cap = EDAC_FLAG_SECDED;
 371         mci->mod_name = EDAC_MOD_STR;
 372         mci->mod_ver = IE31200_REVISION;
 373         mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
 374         mci->dev_name = pci_name(pdev);
 375         mci->edac_check = ie31200_check;
 376         mci->ctl_page_to_phys = NULL;
 377         priv = mci->pvt_info;
 378         priv->window = window;
 379
 380         /* populate DIMM info */
 381         for (i = 0; i < IE31200_CHANNELS; i++) {
 382                 addr_decode = readl(window + IE31200_MAD_DIMM_0_OFFSET +
 383                                         (i * 4));
 384                 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
 385                 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
 386                         dimm_info[i][j].size = (addr_decode >> (j * 8)) &
 387                                                 IE31200_MAD_DIMM_SIZE;
 388                         dimm_info[i][j].dual_rank = (addr_decode &
 389                                 (IE31200_MAD_DIMM_A_RANK << j)) ? 1 : 0;
 390                         dimm_info[i][j].x16_width = (addr_decode &
 391                                 (IE31200_MAD_DIMM_A_WIDTH << j)) ? 1 : 0;
 392                         edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
 393                                  dimm_info[i][j].size,
 394                                  dimm_info[i][j].dual_rank,
 395                                  dimm_info[i][j].x16_width);
 396                 }
 397         }
 398
 399         /*
 400          * The dram rank boundary (DRB) reg values are boundary addresses
 401          * for each DRAM rank with a granularity of 64MB.  DRB regs are
 402          * cumulative; the last one will contain the total memory
 403          * contained in all ranks.
 404          */
 405         for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
 406                 for (j = 0; j < IE31200_CHANNELS; j++) {
 407                         struct dimm_info *dimm;
 408                         unsigned long nr_pages;
 409
 410                         nr_pages = IE31200_PAGES(dimm_info[j][i].size);
 411                         if (nr_pages == 0)
 412                                 continue;
 413
 414                         if (dimm_info[j][i].dual_rank) {
 415                                 nr_pages = nr_pages / 2;
 416                                 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
 417                                                      mci->n_layers, (i * 2) + 1,
 418                                                      j, 0);
 419                                 dimm->nr_pages = nr_pages;
 420                                 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
 421                                 dimm->grain = 8; /* just a guess */
 422                                 dimm->mtype = MEM_DDR3;
 423                                 dimm->dtype = DEV_UNKNOWN;
 424                                 dimm->edac_mode = EDAC_UNKNOWN;
 425                         }
 426                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
 427                                              mci->n_layers, i * 2, j, 0);
 428                         dimm->nr_pages = nr_pages;
 429                         edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
 430                         dimm->grain = 8; /* same guess */
 431                         dimm->mtype = MEM_DDR3;
 432                         dimm->dtype = DEV_UNKNOWN;
 433                         dimm->edac_mode = EDAC_UNKNOWN;
 434                 }
 435         }
 436
 437         ie31200_clear_error_info(mci);
 438
 439         if (edac_mc_add_mc(mci)) {
 440                 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
 441                 ret = -ENODEV;
 442                 goto fail_unmap;
 443         }
 444
 445         /* get this far and it's successful */
 446         edac_dbg(3, "MC: success\n");
 447         return 0;
 448
 449 fail_unmap:
 450         iounmap(window);
 451
 452 fail_free:
 453         edac_mc_free(mci);
 454
 455         return ret;
 456 }
 457
 458 static int ie31200_init_one(struct pci_dev *pdev,
 459                             const struct pci_device_id *ent)
 460 {
 461         int rc;
 462
 463         edac_dbg(0, "MC:\n");
 464         if (pci_enable_device(pdev) < 0)
 465                 return -EIO;
 466         rc = ie31200_probe1(pdev, ent->driver_data);
 467         if (rc == 0 && !mci_pdev)
 468                 mci_pdev = pci_dev_get(pdev);
 469
 470         return rc;
 471 }
 472
 473 static void ie31200_remove_one(struct pci_dev *pdev)
 474 {
 475         struct mem_ctl_info *mci;
 476         struct ie31200_priv *priv;
 477
 478         edac_dbg(0, "\n");
 479         pci_dev_put(mci_pdev);
 480         mci_pdev = NULL;
 481         mci = edac_mc_del_mc(&pdev->dev);
 482         if (!mci)
 483                 return;
 484         priv = mci->pvt_info;
 485         iounmap(priv->window);
 486         edac_mc_free(mci);
 487 }
 488
 489 static const struct pci_device_id ie31200_pci_tbl[] = {
 490         {
 491                 PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 492                 IE31200},
 493         {
 494                 PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 495                 IE31200},
 496         {
 497                 PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 498                 IE31200},
 499         {
 500                 PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 501                 IE31200},
 502         {
 503                 PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 504                 IE31200},
 505         {
 506                 PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 507                 IE31200},
 508         {
 509                 PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 510                 IE31200},
 511         {
 512                 0,
 513         }            /* 0 terminated list. */
 514 };
 515 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
 516
 517 static struct pci_driver ie31200_driver = {
 518         .name = EDAC_MOD_STR,
 519         .probe = ie31200_init_one,
 520         .remove = ie31200_remove_one,
 521         .id_table = ie31200_pci_tbl,
 522 };
 523
 524 static int __init ie31200_init(void)
 525 {
 526         int pci_rc, i;
 527
 528         edac_dbg(3, "MC:\n");
 529         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 530         opstate_init();
 531
 532         pci_rc = pci_register_driver(&ie31200_driver);
 533         if (pci_rc < 0)
 534                 goto fail0;
 535
 536         if (!mci_pdev) {
 537                 ie31200_registered = 0;
 538                 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
 539                         mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
 540                                                   ie31200_pci_tbl[i].device,
 541                                                   NULL);
 542                         if (mci_pdev)
 543                                 break;
 544                 }
 545                 if (!mci_pdev) {
 546                         edac_dbg(0, "ie31200 pci_get_device fail\n");
 547                         pci_rc = -ENODEV;
 548                         goto fail1;
 549                 }
 550                 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
 551                 if (pci_rc < 0) {
 552                         edac_dbg(0, "ie31200 init fail\n");
 553                         pci_rc = -ENODEV;
 554                         goto fail1;
 555                 }
 556         }
 557         return 0;
 558
 559 fail1:
 560         pci_unregister_driver(&ie31200_driver);
 561 fail0:
 562         pci_dev_put(mci_pdev);
 563
 564         return pci_rc;
 565 }
 566
 567 static void __exit ie31200_exit(void)
 568 {
 569         edac_dbg(3, "MC:\n");
 570         pci_unregister_driver(&ie31200_driver);
 571         if (!ie31200_registered)
 572                 ie31200_remove_one(mci_pdev);
 573 }
 574
 575 module_init(ie31200_init);
 576 module_exit(ie31200_exit);
 577
 578 MODULE_LICENSE("GPL");
 579 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
 580 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");