2 * Copyright 2011-2012 Calxeda, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/ctype.h>
19 #include <linux/edac.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_platform.h>
23 #include <linux/uaccess.h>
25 #include "edac_module.h"
27 /* DDR Ctrlr Error Registers */
29 #define HB_DDR_ECC_ERR_BASE 0x128
30 #define MW_DDR_ECC_ERR_BASE 0x1b4
32 #define HB_DDR_ECC_OPT 0x00
33 #define HB_DDR_ECC_U_ERR_ADDR 0x08
34 #define HB_DDR_ECC_U_ERR_STAT 0x0c
35 #define HB_DDR_ECC_U_ERR_DATAL 0x10
36 #define HB_DDR_ECC_U_ERR_DATAH 0x14
37 #define HB_DDR_ECC_C_ERR_ADDR 0x18
38 #define HB_DDR_ECC_C_ERR_STAT 0x1c
39 #define HB_DDR_ECC_C_ERR_DATAL 0x20
40 #define HB_DDR_ECC_C_ERR_DATAH 0x24
42 #define HB_DDR_ECC_OPT_MODE_MASK 0x3
43 #define HB_DDR_ECC_OPT_FWC 0x100
44 #define HB_DDR_ECC_OPT_XOR_SHIFT 16
46 /* DDR Ctrlr Interrupt Registers */
48 #define HB_DDR_ECC_INT_BASE 0x180
49 #define MW_DDR_ECC_INT_BASE 0x218
51 #define HB_DDR_ECC_INT_STATUS 0x00
52 #define HB_DDR_ECC_INT_ACK 0x04
54 #define HB_DDR_ECC_INT_STAT_CE 0x8
55 #define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
56 #define HB_DDR_ECC_INT_STAT_UE 0x20
57 #define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
59 struct hb_mc_drvdata {
60 void __iomem *mc_err_base;
61 void __iomem *mc_int_base;
64 static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
66 struct mem_ctl_info *mci = dev_id;
67 struct hb_mc_drvdata *drvdata = mci->pvt_info;
70 /* Read the interrupt status register */
71 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
73 if (status & HB_DDR_ECC_INT_STAT_UE) {
74 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
75 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
76 err_addr >> PAGE_SHIFT,
77 err_addr & ~PAGE_MASK, 0,
81 if (status & HB_DDR_ECC_INT_STAT_CE) {
82 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
83 syndrome = (syndrome >> 8) & 0xff;
84 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
85 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
86 err_addr >> PAGE_SHIFT,
87 err_addr & ~PAGE_MASK, syndrome,
92 /* clear the error, clears the interrupt */
93 writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
97 static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
99 struct hb_mc_drvdata *pdata = mci->pvt_info;
102 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
103 reg &= HB_DDR_ECC_OPT_MODE_MASK;
104 reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
105 writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
108 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
110 static ssize_t highbank_mc_inject_ctrl(struct device *dev,
111 struct device_attribute *attr, const char *buf, size_t count)
113 struct mem_ctl_info *mci = to_mci(dev);
116 if (kstrtou8(buf, 16, &synd))
119 highbank_mc_err_inject(mci, synd);
124 static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
126 static struct attribute *highbank_dev_attrs[] = {
127 &dev_attr_inject_ctrl.attr,
131 ATTRIBUTE_GROUPS(highbank_dev);
133 struct hb_mc_settings {
138 static struct hb_mc_settings hb_settings = {
139 .err_offset = HB_DDR_ECC_ERR_BASE,
140 .int_offset = HB_DDR_ECC_INT_BASE,
143 static struct hb_mc_settings mw_settings = {
144 .err_offset = MW_DDR_ECC_ERR_BASE,
145 .int_offset = MW_DDR_ECC_INT_BASE,
148 static const struct of_device_id hb_ddr_ctrl_of_match[] = {
149 { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
150 { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
153 MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
155 static int highbank_mc_probe(struct platform_device *pdev)
157 const struct of_device_id *id;
158 const struct hb_mc_settings *settings;
159 struct edac_mc_layer layers[2];
160 struct mem_ctl_info *mci;
161 struct hb_mc_drvdata *drvdata;
162 struct dimm_info *dimm;
169 id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
173 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
175 layers[0].is_virt_csrow = true;
176 layers[1].type = EDAC_MC_LAYER_CHANNEL;
178 layers[1].is_virt_csrow = false;
179 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
180 sizeof(struct hb_mc_drvdata));
184 mci->pdev = &pdev->dev;
185 drvdata = mci->pvt_info;
186 platform_set_drvdata(pdev, mci);
188 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
193 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195 dev_err(&pdev->dev, "Unable to get mem resource\n");
200 if (!devm_request_mem_region(&pdev->dev, r->start,
201 resource_size(r), dev_name(&pdev->dev))) {
202 dev_err(&pdev->dev, "Error while requesting mem region\n");
207 base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
209 dev_err(&pdev->dev, "Unable to map regs\n");
215 drvdata->mc_err_base = base + settings->err_offset;
216 drvdata->mc_int_base = base + settings->int_offset;
218 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
219 if (!control || (control == 0x2)) {
220 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
225 mci->mtype_cap = MEM_FLAG_DDR3;
226 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
227 mci->edac_cap = EDAC_FLAG_SECDED;
228 mci->mod_name = pdev->dev.driver->name;
229 mci->ctl_name = id->compatible;
230 mci->dev_name = dev_name(&pdev->dev);
231 mci->scrub_mode = SCRUB_SW_SRC;
233 /* Only a single 4GB DIMM is supported */
235 dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
237 dimm->dtype = DEV_X8;
238 dimm->mtype = MEM_DDR3;
239 dimm->edac_mode = EDAC_SECDED;
241 res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
245 irq = platform_get_irq(pdev, 0);
246 res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
247 0, dev_name(&pdev->dev), mci);
249 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
253 devres_close_group(&pdev->dev, NULL);
256 edac_mc_del_mc(&pdev->dev);
258 devres_release_group(&pdev->dev, NULL);
264 static int highbank_mc_remove(struct platform_device *pdev)
266 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
268 edac_mc_del_mc(&pdev->dev);
273 static struct platform_driver highbank_mc_edac_driver = {
274 .probe = highbank_mc_probe,
275 .remove = highbank_mc_remove,
277 .name = "hb_mc_edac",
278 .of_match_table = hb_ddr_ctrl_of_match,
282 module_platform_driver(highbank_mc_edac_driver);
284 MODULE_LICENSE("GPL v2");
285 MODULE_AUTHOR("Calxeda, Inc.");
286 MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");