1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dmapool.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/wait.h>
27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
29 #include "../dmaengine.h"
30 #include "../virt-dma.h"
33 #define XILINX_DPDMA_ERR_CTRL 0x000
34 #define XILINX_DPDMA_ISR 0x004
35 #define XILINX_DPDMA_IMR 0x008
36 #define XILINX_DPDMA_IEN 0x00c
37 #define XILINX_DPDMA_IDS 0x010
38 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0)
39 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)
40 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6)
41 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)
42 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12)
43 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)
44 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16)
45 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)
46 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24)
47 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25)
48 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26)
49 #define XILINX_DPDMA_INTR_VSYNC BIT(27)
50 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000
51 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000
52 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000
53 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000
54 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041
55 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000
56 #define XILINX_DPDMA_INTR_ALL 0x0fffffff
57 #define XILINX_DPDMA_EISR 0x014
58 #define XILINX_DPDMA_EIMR 0x018
59 #define XILINX_DPDMA_EIEN 0x01c
60 #define XILINX_DPDMA_EIDS 0x020
61 #define XILINX_DPDMA_EINTR_INV_APB BIT(0)
62 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
64 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7)
65 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)
66 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13)
67 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)
68 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19)
69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)
70 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25)
71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)
72 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32)
73 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082
74 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe
75 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001
76 #define XILINX_DPDMA_EINTR_ALL 0xffffffff
77 #define XILINX_DPDMA_CNTL 0x100
78 #define XILINX_DPDMA_GBL 0x104
79 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0)
80 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6)
81 #define XILINX_DPDMA_ALC0_CNTL 0x108
82 #define XILINX_DPDMA_ALC0_STATUS 0x10c
83 #define XILINX_DPDMA_ALC0_MAX 0x110
84 #define XILINX_DPDMA_ALC0_MIN 0x114
85 #define XILINX_DPDMA_ALC0_ACC 0x118
86 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c
87 #define XILINX_DPDMA_ALC1_CNTL 0x120
88 #define XILINX_DPDMA_ALC1_STATUS 0x124
89 #define XILINX_DPDMA_ALC1_MAX 0x128
90 #define XILINX_DPDMA_ALC1_MIN 0x12c
91 #define XILINX_DPDMA_ALC1_ACC 0x130
92 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134
94 /* Channel register */
95 #define XILINX_DPDMA_CH_BASE 0x200
96 #define XILINX_DPDMA_CH_OFFSET 0x100
97 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000
98 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)
99 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004
100 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008
101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c
102 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010
103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014
104 #define XILINX_DPDMA_CH_CNTL 0x018
105 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0)
106 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
107 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)
108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)
109 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)
110 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11
111 #define XILINX_DPDMA_CH_STATUS 0x01c
112 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)
113 #define XILINX_DPDMA_CH_VDO 0x020
114 #define XILINX_DPDMA_CH_PYLD_SZ 0x024
115 #define XILINX_DPDMA_CH_DESC_ID 0x028
116 #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
118 /* DPDMA descriptor fields */
119 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
120 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8)
121 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9)
122 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10)
123 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18)
124 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19)
125 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20)
126 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21)
127 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)
128 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)
129 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)
130 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)
131 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)
133 #define XILINX_DPDMA_ALIGN_BYTES 256
134 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128
136 #define XILINX_DPDMA_NUM_CHAN 6
138 struct xilinx_dpdma_chan;
141 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
142 * @control: control configuration field
143 * @desc_id: descriptor ID
144 * @xfer_size: transfer size
145 * @hsize_stride: horizontal size and stride
146 * @timestamp_lsb: LSB of time stamp
147 * @timestamp_msb: MSB of time stamp
148 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr)
149 * @next_desc: next descriptor 32 bit address
150 * @src_addr: payload source address (1st page, 32 LSB)
151 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs)
152 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs)
153 * @src_addr2: payload source address (2nd page, 32 LSB)
154 * @src_addr3: payload source address (3rd page, 32 LSB)
155 * @src_addr4: payload source address (4th page, 32 LSB)
156 * @src_addr5: payload source address (5th page, 32 LSB)
157 * @crc: descriptor CRC
159 struct xilinx_dpdma_hw_desc {
176 } __aligned(XILINX_DPDMA_ALIGN_BYTES);
179 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
180 * @hw: DPDMA hardware descriptor
181 * @node: list node for software descriptors
182 * @dma_addr: DMA address of the software descriptor
184 struct xilinx_dpdma_sw_desc {
185 struct xilinx_dpdma_hw_desc hw;
186 struct list_head node;
191 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
192 * @vdesc: virtual DMA descriptor
194 * @descriptors: list of software descriptors
195 * @error: an error has been detected with this descriptor
197 struct xilinx_dpdma_tx_desc {
198 struct virt_dma_desc vdesc;
199 struct xilinx_dpdma_chan *chan;
200 struct list_head descriptors;
204 #define to_dpdma_tx_desc(_desc) \
205 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc)
208 * struct xilinx_dpdma_chan - DPDMA channel
209 * @vchan: virtual DMA channel
210 * @reg: register base address
212 * @wait_to_stop: queue to wait for outstanding transacitons before stopping
213 * @running: true if the channel is running
214 * @first_frame: flag for the first frame of stream
215 * @video_group: flag if multi-channel operation is needed for video channels
216 * @lock: lock to access struct xilinx_dpdma_chan. Must be taken before
217 * @vchan.lock, if both are to be held.
218 * @desc_pool: descriptor allocation pool
219 * @err_task: error IRQ bottom half handler
220 * @desc: References to descriptors being processed
221 * @desc.pending: Descriptor schedule to the hardware, pending execution
222 * @desc.active: Descriptor being executed by the hardware
223 * @xdev: DPDMA device
225 struct xilinx_dpdma_chan {
226 struct virt_dma_chan vchan;
230 wait_queue_head_t wait_to_stop;
235 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */
236 struct dma_pool *desc_pool;
237 struct tasklet_struct err_task;
240 struct xilinx_dpdma_tx_desc *pending;
241 struct xilinx_dpdma_tx_desc *active;
244 struct xilinx_dpdma_device *xdev;
247 #define to_xilinx_chan(_chan) \
248 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
251 * struct xilinx_dpdma_device - DPDMA device
252 * @common: generic dma device structure
253 * @reg: register base address
254 * @dev: generic device structure
255 * @irq: the interrupt number
256 * @axi_clk: axi clock
257 * @chan: DPDMA channels
258 * @ext_addr: flag for 64 bit system (48 bit addressing)
260 struct xilinx_dpdma_device {
261 struct dma_device common;
267 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];
272 /* -----------------------------------------------------------------------------
276 #ifdef CONFIG_DEBUG_FS
278 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32
279 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535"
281 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
282 enum xilinx_dpdma_testcases {
287 struct xilinx_dpdma_debugfs {
288 enum xilinx_dpdma_testcases testcase;
289 u16 xilinx_dpdma_irq_done_count;
290 unsigned int chan_id;
293 static struct xilinx_dpdma_debugfs dpdma_debugfs;
294 struct xilinx_dpdma_debugfs_request {
296 enum xilinx_dpdma_testcases tc;
297 ssize_t (*read)(char *buf);
298 int (*write)(char *args);
301 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
303 if (chan->id == dpdma_debugfs.chan_id)
304 dpdma_debugfs.xilinx_dpdma_irq_done_count++;
307 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)
311 dpdma_debugfs.testcase = DPDMA_TC_NONE;
313 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR);
314 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE,
316 snprintf(buf, out_str_len, "%d",
317 dpdma_debugfs.xilinx_dpdma_irq_done_count);
322 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args)
328 arg = strsep(&args, " ");
329 if (!arg || strncasecmp(arg, "start", 5))
332 arg = strsep(&args, " ");
336 ret = kstrtou32(arg, 0, &id);
340 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1)
343 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE;
344 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0;
345 dpdma_debugfs.chan_id = id;
350 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
351 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = {
353 .name = "DESCRIPTOR_DONE_INTR",
354 .tc = DPDMA_TC_INTR_DONE,
355 .read = xilinx_dpdma_debugfs_desc_done_irq_read,
356 .write = xilinx_dpdma_debugfs_desc_done_irq_write,
360 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf,
361 size_t size, loff_t *pos)
363 enum xilinx_dpdma_testcases testcase;
367 if (*pos != 0 || size <= 0)
370 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL);
372 dpdma_debugfs.testcase = DPDMA_TC_NONE;
376 testcase = READ_ONCE(dpdma_debugfs.testcase);
377 if (testcase != DPDMA_TC_NONE) {
378 ret = dpdma_debugfs_reqs[testcase].read(kern_buff);
382 strlcpy(kern_buff, "No testcase executed",
383 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE);
386 size = min(size, strlen(kern_buff));
387 if (copy_to_user(buf, kern_buff, size))
399 static ssize_t xilinx_dpdma_debugfs_write(struct file *f,
400 const char __user *buf, size_t size,
403 char *kern_buff, *kern_buff_start;
408 if (*pos != 0 || size <= 0)
411 /* Supporting single instance of test as of now. */
412 if (dpdma_debugfs.testcase != DPDMA_TC_NONE)
415 kern_buff = kzalloc(size, GFP_KERNEL);
418 kern_buff_start = kern_buff;
420 ret = strncpy_from_user(kern_buff, buf, size);
424 /* Read the testcase name from a user request. */
425 testcase = strsep(&kern_buff, " ");
427 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) {
428 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name))
432 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) {
437 ret = dpdma_debugfs_reqs[i].write(kern_buff);
444 kfree(kern_buff_start);
448 static const struct file_operations fops_xilinx_dpdma_dbgfs = {
449 .owner = THIS_MODULE,
450 .read = xilinx_dpdma_debugfs_read,
451 .write = xilinx_dpdma_debugfs_write,
454 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
458 dpdma_debugfs.testcase = DPDMA_TC_NONE;
460 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root,
461 NULL, &fops_xilinx_dpdma_dbgfs);
463 dev_err(xdev->dev, "Failed to create debugfs testcase file\n");
467 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
471 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
474 #endif /* CONFIG_DEBUG_FS */
476 /* -----------------------------------------------------------------------------
480 static inline u32 dpdma_read(void __iomem *base, u32 offset)
482 return ioread32(base + offset);
485 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
487 iowrite32(val, base + offset);
490 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)
492 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
495 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)
497 dpdma_write(base, offset, dpdma_read(base, offset) | set);
500 /* -----------------------------------------------------------------------------
501 * Descriptor Operations
505 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor
506 * @xdev: DPDMA device
507 * @sw_desc: The software descriptor in which to set DMA addresses
508 * @prev: The previous descriptor
509 * @dma_addr: array of dma addresses
510 * @num_src_addr: number of addresses in @dma_addr
512 * Set all the DMA addresses in the hardware descriptor corresponding to @dev
513 * from @dma_addr. If a previous descriptor is specified in @prev, its next
514 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
515 * identical to @sw_desc for cyclic transfers.
517 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
518 struct xilinx_dpdma_sw_desc *sw_desc,
519 struct xilinx_dpdma_sw_desc *prev,
520 dma_addr_t dma_addr[],
521 unsigned int num_src_addr)
523 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
526 hw_desc->src_addr = lower_32_bits(dma_addr[0]);
529 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK,
530 upper_32_bits(dma_addr[0]));
532 for (i = 1; i < num_src_addr; i++) {
533 u32 *addr = &hw_desc->src_addr2;
535 addr[i-1] = lower_32_bits(dma_addr[i]);
537 if (xdev->ext_addr) {
538 u32 *addr_ext = &hw_desc->addr_ext_23;
541 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);
542 addr_msb <<= 16 * ((i - 1) % 2);
543 addr_ext[(i - 1) / 2] |= addr_msb;
550 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
553 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
554 upper_32_bits(sw_desc->dma_addr));
558 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor
559 * @chan: DPDMA channel
561 * Allocate a software descriptor from the channel's descriptor pool.
563 * Return: a software descriptor or NULL.
565 static struct xilinx_dpdma_sw_desc *
566 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan)
568 struct xilinx_dpdma_sw_desc *sw_desc;
571 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
575 sw_desc->dma_addr = dma_addr;
581 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor
582 * @chan: DPDMA channel
583 * @sw_desc: software descriptor to free
585 * Free a software descriptor from the channel's descriptor pool.
588 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan,
589 struct xilinx_dpdma_sw_desc *sw_desc)
591 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
595 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor
596 * @chan: DPDMA channel
597 * @tx_desc: tx descriptor to dump
599 * Dump contents of a tx descriptor
601 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,
602 struct xilinx_dpdma_tx_desc *tx_desc)
604 struct xilinx_dpdma_sw_desc *sw_desc;
605 struct device *dev = chan->xdev->dev;
608 dev_dbg(dev, "------- TX descriptor dump start -------\n");
609 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id);
611 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
612 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
614 dev_dbg(dev, "------- HW descriptor %d -------\n", i++);
615 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
616 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
617 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
618 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
619 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
620 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
621 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
622 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
623 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
624 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
625 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
626 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
627 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
628 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
629 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
630 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
631 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
634 dev_dbg(dev, "------- TX descriptor dump end -------\n");
638 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor
639 * @chan: DPDMA channel
641 * Allocate a tx descriptor.
643 * Return: a tx descriptor or NULL.
645 static struct xilinx_dpdma_tx_desc *
646 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
648 struct xilinx_dpdma_tx_desc *tx_desc;
650 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT);
654 INIT_LIST_HEAD(&tx_desc->descriptors);
655 tx_desc->chan = chan;
656 tx_desc->error = false;
662 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor
663 * @vdesc: virtual DMA descriptor
665 * Free the virtual DMA descriptor @vdesc including its software descriptors.
667 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)
669 struct xilinx_dpdma_sw_desc *sw_desc, *next;
670 struct xilinx_dpdma_tx_desc *desc;
675 desc = to_dpdma_tx_desc(vdesc);
677 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
678 list_del(&sw_desc->node);
679 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
686 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma
688 * @chan: DPDMA channel
689 * @xt: dma interleaved template
691 * Prepare a tx descriptor including internal software/hardware descriptors
694 * Return: A DPDMA TX descriptor on success, or NULL.
696 static struct xilinx_dpdma_tx_desc *
697 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
698 struct dma_interleaved_template *xt)
700 struct xilinx_dpdma_tx_desc *tx_desc;
701 struct xilinx_dpdma_sw_desc *sw_desc;
702 struct xilinx_dpdma_hw_desc *hw_desc;
703 size_t hsize = xt->sgl[0].size;
704 size_t stride = hsize + xt->sgl[0].icg;
706 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
707 dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n",
708 XILINX_DPDMA_ALIGN_BYTES);
712 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
716 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
718 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
722 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
725 hw_desc = &sw_desc->hw;
726 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8);
727 hw_desc->xfer_size = hsize * xt->numf;
728 hw_desc->hsize_stride =
729 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) |
730 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
732 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
733 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
734 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
735 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
737 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
742 /* -----------------------------------------------------------------------------
743 * DPDMA Channel Operations
747 * xilinx_dpdma_chan_enable - Enable the channel
748 * @chan: DPDMA channel
750 * Enable the channel and its interrupts. Set the QoS values for video class.
752 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)
756 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
757 | XILINX_DPDMA_INTR_GLOBAL_MASK;
758 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
759 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
760 | XILINX_DPDMA_INTR_GLOBAL_ERR;
761 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
763 reg = XILINX_DPDMA_CH_CNTL_ENABLE
764 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK,
765 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
766 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK,
767 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
768 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK,
769 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS);
770 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
774 * xilinx_dpdma_chan_disable - Disable the channel
775 * @chan: DPDMA channel
777 * Disable the channel and its interrupts.
779 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)
783 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
784 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
785 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
786 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
788 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
792 * xilinx_dpdma_chan_pause - Pause the channel
793 * @chan: DPDMA channel
797 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)
799 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
803 * xilinx_dpdma_chan_unpause - Unpause the channel
804 * @chan: DPDMA channel
806 * Unpause the channel.
808 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)
810 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
813 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)
815 struct xilinx_dpdma_device *xdev = chan->xdev;
819 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
820 if (xdev->chan[i]->video_group && !xdev->chan[i]->running)
823 if (xdev->chan[i]->video_group)
831 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer
832 * @chan: DPDMA channel
834 * Queue the next descriptor, if any, to the hardware. If the channel is
835 * stopped, start it first. Otherwise retrigger it with the next descriptor.
837 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
839 struct xilinx_dpdma_device *xdev = chan->xdev;
840 struct xilinx_dpdma_sw_desc *sw_desc;
841 struct xilinx_dpdma_tx_desc *desc;
842 struct virt_dma_desc *vdesc;
846 lockdep_assert_held(&chan->lock);
848 if (chan->desc.pending)
851 if (!chan->running) {
852 xilinx_dpdma_chan_unpause(chan);
853 xilinx_dpdma_chan_enable(chan);
854 chan->first_frame = true;
855 chan->running = true;
858 vdesc = vchan_next_desc(&chan->vchan);
862 desc = to_dpdma_tx_desc(vdesc);
863 chan->desc.pending = desc;
864 list_del(&desc->vdesc.node);
867 * Assign the cookie to descriptors in this transaction. Only 16 bit
868 * will be used, but it should be enough.
870 list_for_each_entry(sw_desc, &desc->descriptors, node)
871 sw_desc->hw.desc_id = desc->vdesc.tx.cookie
872 & XILINX_DPDMA_CH_DESC_ID_MASK;
874 sw_desc = list_first_entry(&desc->descriptors,
875 struct xilinx_dpdma_sw_desc, node);
876 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
877 lower_32_bits(sw_desc->dma_addr));
879 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
880 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
881 upper_32_bits(sw_desc->dma_addr)));
883 first_frame = chan->first_frame;
884 chan->first_frame = false;
886 if (chan->video_group) {
887 channels = xilinx_dpdma_chan_video_group_ready(chan);
889 * Trigger the transfer only when all channels in the group are
895 channels = BIT(chan->id);
899 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
901 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
903 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
907 * xilinx_dpdma_chan_ostand - Number of outstanding transactions
908 * @chan: DPDMA channel
910 * Read and return the number of outstanding transactions from register.
912 * Return: Number of outstanding transactions from the status register.
914 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
916 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,
917 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
921 * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event
922 * @chan: DPDMA channel
924 * Notify waiters for no outstanding event, so waiters can stop the channel
925 * safely. This function is supposed to be called when 'no outstanding'
926 * interrupt is generated. The 'no outstanding' interrupt is disabled and
927 * should be re-enabled when this event is handled. If the channel status
928 * register still shows some number of outstanding transactions, the interrupt
931 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding
934 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
938 cnt = xilinx_dpdma_chan_ostand(chan);
940 dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt);
944 /* Disable 'no outstanding' interrupt */
945 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
946 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
947 wake_up(&chan->wait_to_stop);
953 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq
954 * @chan: DPDMA channel
956 * Wait for the no outstanding transaction interrupt. This functions can sleep
959 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code
960 * from wait_event_interruptible_timeout().
962 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
966 /* Wait for a no outstanding transaction interrupt upto 50msec */
967 ret = wait_event_interruptible_timeout(chan->wait_to_stop,
968 !xilinx_dpdma_chan_ostand(chan),
969 msecs_to_jiffies(50));
971 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
972 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
976 dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
977 xilinx_dpdma_chan_ostand(chan));
986 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status
987 * @chan: DPDMA channel
989 * Poll the outstanding transaction status, and return when there's no
990 * outstanding transaction. This functions can be used in the interrupt context
991 * or where the atomicity is required. Calling thread may wait more than 50ms.
993 * Return: 0 on success, or -ETIMEDOUT.
995 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
997 u32 cnt, loop = 50000;
999 /* Poll at least for 50ms (20 fps). */
1001 cnt = xilinx_dpdma_chan_ostand(chan);
1003 } while (loop-- > 0 && cnt);
1006 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1007 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
1011 dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
1012 xilinx_dpdma_chan_ostand(chan));
1018 * xilinx_dpdma_chan_stop - Stop the channel
1019 * @chan: DPDMA channel
1021 * Stop a previously paused channel by first waiting for completion of all
1022 * outstanding transaction and then disabling the channel.
1024 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1026 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)
1028 unsigned long flags;
1031 ret = xilinx_dpdma_chan_wait_no_ostand(chan);
1035 spin_lock_irqsave(&chan->lock, flags);
1036 xilinx_dpdma_chan_disable(chan);
1037 chan->running = false;
1038 spin_unlock_irqrestore(&chan->lock, flags);
1044 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion
1045 * @chan: DPDMA channel
1047 * Handle completion of the currently active descriptor (@chan->desc.active). As
1048 * we currently support cyclic transfers only, this just invokes the cyclic
1049 * callback. The descriptor will be completed at the VSYNC interrupt when a new
1050 * descriptor replaces it.
1052 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
1054 struct xilinx_dpdma_tx_desc *active;
1055 unsigned long flags;
1057 spin_lock_irqsave(&chan->lock, flags);
1059 xilinx_dpdma_debugfs_desc_done_irq(chan);
1061 active = chan->desc.active;
1063 vchan_cyclic_callback(&active->vdesc);
1065 dev_warn(chan->xdev->dev,
1066 "DONE IRQ with no active descriptor!\n");
1068 spin_unlock_irqrestore(&chan->lock, flags);
1072 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling
1073 * @chan: DPDMA channel
1075 * At VSYNC the active descriptor may have been replaced by the pending
1076 * descriptor. Detect this through the DESC_ID and perform appropriate
1079 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
1081 struct xilinx_dpdma_tx_desc *pending;
1082 struct xilinx_dpdma_sw_desc *sw_desc;
1083 unsigned long flags;
1086 spin_lock_irqsave(&chan->lock, flags);
1088 pending = chan->desc.pending;
1089 if (!chan->running || !pending)
1092 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
1093 & XILINX_DPDMA_CH_DESC_ID_MASK;
1095 /* If the retrigger raced with vsync, retry at the next frame. */
1096 sw_desc = list_first_entry(&pending->descriptors,
1097 struct xilinx_dpdma_sw_desc, node);
1098 if (sw_desc->hw.desc_id != desc_id)
1102 * Complete the active descriptor, if any, promote the pending
1103 * descriptor to active, and queue the next transfer, if any.
1105 spin_lock(&chan->vchan.lock);
1106 if (chan->desc.active)
1107 vchan_cookie_complete(&chan->desc.active->vdesc);
1108 chan->desc.active = pending;
1109 chan->desc.pending = NULL;
1111 xilinx_dpdma_chan_queue_transfer(chan);
1112 spin_unlock(&chan->vchan.lock);
1115 spin_unlock_irqrestore(&chan->lock, flags);
1119 * xilinx_dpdma_chan_err - Detect any channel error
1120 * @chan: DPDMA channel
1121 * @isr: masked Interrupt Status Register
1122 * @eisr: Error Interrupt Status Register
1124 * Return: true if any channel error occurs, or false otherwise.
1127 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)
1132 if (chan->running &&
1133 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) ||
1134 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id))))
1141 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling
1142 * @chan: DPDMA channel
1144 * This function is called when any channel error or any global error occurs.
1145 * The function disables the paused channel by errors and determines
1146 * if the current active descriptor can be rescheduled depending on
1147 * the descriptor status.
1149 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
1151 struct xilinx_dpdma_device *xdev = chan->xdev;
1152 struct xilinx_dpdma_tx_desc *active;
1153 unsigned long flags;
1155 spin_lock_irqsave(&chan->lock, flags);
1157 dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n",
1158 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1159 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1160 dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n",
1161 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1162 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1164 xilinx_dpdma_chan_disable(chan);
1165 chan->running = false;
1167 if (!chan->desc.active)
1170 active = chan->desc.active;
1171 chan->desc.active = NULL;
1173 xilinx_dpdma_chan_dump_tx_desc(chan, active);
1176 dev_dbg(xdev->dev, "repeated error on desc\n");
1178 /* Reschedule if there's no new descriptor */
1179 if (!chan->desc.pending &&
1180 list_empty(&chan->vchan.desc_issued)) {
1181 active->error = true;
1182 list_add_tail(&active->vdesc.node,
1183 &chan->vchan.desc_issued);
1185 xilinx_dpdma_chan_free_tx_desc(&active->vdesc);
1189 spin_unlock_irqrestore(&chan->lock, flags);
1192 /* -----------------------------------------------------------------------------
1193 * DMA Engine Operations
1196 static struct dma_async_tx_descriptor *
1197 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan,
1198 struct dma_interleaved_template *xt,
1199 unsigned long flags)
1201 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1202 struct xilinx_dpdma_tx_desc *desc;
1204 if (xt->dir != DMA_MEM_TO_DEV)
1207 if (!xt->numf || !xt->sgl[0].size)
1210 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))
1213 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt);
1217 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK);
1219 return &desc->vdesc.tx;
1223 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel
1224 * @dchan: DMA channel
1226 * Allocate a descriptor pool for the channel.
1228 * Return: 0 on success, or -ENOMEM if failed to allocate a pool.
1230 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
1232 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1233 size_t align = __alignof__(struct xilinx_dpdma_sw_desc);
1235 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev),
1237 sizeof(struct xilinx_dpdma_sw_desc),
1239 if (!chan->desc_pool) {
1240 dev_err(chan->xdev->dev,
1241 "failed to allocate a descriptor pool\n");
1249 * xilinx_dpdma_free_chan_resources - Free all resources for the channel
1250 * @dchan: DMA channel
1252 * Free resources associated with the virtual DMA channel, and destroy the
1255 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)
1257 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1259 vchan_free_chan_resources(&chan->vchan);
1261 dma_pool_destroy(chan->desc_pool);
1262 chan->desc_pool = NULL;
1265 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)
1267 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1268 unsigned long flags;
1270 spin_lock_irqsave(&chan->lock, flags);
1271 spin_lock(&chan->vchan.lock);
1272 if (vchan_issue_pending(&chan->vchan))
1273 xilinx_dpdma_chan_queue_transfer(chan);
1274 spin_unlock(&chan->vchan.lock);
1275 spin_unlock_irqrestore(&chan->lock, flags);
1278 static int xilinx_dpdma_config(struct dma_chan *dchan,
1279 struct dma_slave_config *config)
1281 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1282 unsigned long flags;
1285 * The destination address doesn't need to be specified as the DPDMA is
1286 * hardwired to the destination (the DP controller). The transfer
1287 * width, burst size and port window size are thus meaningless, they're
1288 * fixed both on the DPDMA side and on the DP controller side.
1291 spin_lock_irqsave(&chan->lock, flags);
1294 * Abuse the slave_id to indicate that the channel is part of a video
1297 if (chan->id <= ZYNQMP_DPDMA_VIDEO2)
1298 chan->video_group = config->slave_id != 0;
1300 spin_unlock_irqrestore(&chan->lock, flags);
1305 static int xilinx_dpdma_pause(struct dma_chan *dchan)
1307 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan));
1312 static int xilinx_dpdma_resume(struct dma_chan *dchan)
1314 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan));
1320 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors
1321 * @dchan: DMA channel
1323 * Pause the channel without waiting for ongoing transfers to complete. Waiting
1324 * for completion is performed by xilinx_dpdma_synchronize() that will disable
1325 * the channel to complete the stop.
1327 * All the descriptors associated with the channel that are guaranteed not to
1328 * be touched by the hardware. The pending and active descriptor are not
1329 * touched, and will be freed either upon completion, or by
1330 * xilinx_dpdma_synchronize().
1332 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1334 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)
1336 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1337 struct xilinx_dpdma_device *xdev = chan->xdev;
1338 LIST_HEAD(descriptors);
1339 unsigned long flags;
1342 /* Pause the channel (including the whole video group if applicable). */
1343 if (chan->video_group) {
1344 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
1345 if (xdev->chan[i]->video_group &&
1346 xdev->chan[i]->running) {
1347 xilinx_dpdma_chan_pause(xdev->chan[i]);
1348 xdev->chan[i]->video_group = false;
1352 xilinx_dpdma_chan_pause(chan);
1355 /* Gather all the descriptors we can free and free them. */
1356 spin_lock_irqsave(&chan->vchan.lock, flags);
1357 vchan_get_all_descriptors(&chan->vchan, &descriptors);
1358 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1360 vchan_dma_desc_free_list(&chan->vchan, &descriptors);
1366 * xilinx_dpdma_synchronize - Synchronize callback execution
1367 * @dchan: DMA channel
1369 * Synchronizing callback execution ensures that all previously issued
1370 * transfers have completed and all associated callbacks have been called and
1373 * This function waits for the DMA channel to stop. It assumes it has been
1374 * paused by a previous call to dmaengine_terminate_async(), and that no new
1375 * pending descriptors have been issued with dma_async_issue_pending(). The
1376 * behaviour is undefined otherwise.
1378 static void xilinx_dpdma_synchronize(struct dma_chan *dchan)
1380 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1381 unsigned long flags;
1383 xilinx_dpdma_chan_stop(chan);
1385 spin_lock_irqsave(&chan->vchan.lock, flags);
1386 if (chan->desc.pending) {
1387 vchan_terminate_vdesc(&chan->desc.pending->vdesc);
1388 chan->desc.pending = NULL;
1390 if (chan->desc.active) {
1391 vchan_terminate_vdesc(&chan->desc.active->vdesc);
1392 chan->desc.active = NULL;
1394 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1396 vchan_synchronize(&chan->vchan);
1399 /* -----------------------------------------------------------------------------
1400 * Interrupt and Tasklet Handling
1404 * xilinx_dpdma_err - Detect any global error
1405 * @isr: Interrupt Status Register
1406 * @eisr: Error Interrupt Status Register
1408 * Return: True if any global error occurs, or false otherwise.
1410 static bool xilinx_dpdma_err(u32 isr, u32 eisr)
1412 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||
1413 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR)
1420 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt
1421 * @xdev: DPDMA device
1422 * @isr: masked Interrupt Status Register
1423 * @eisr: Error Interrupt Status Register
1425 * Handle if any error occurs based on @isr and @eisr. This function disables
1426 * corresponding error interrupts, and those should be re-enabled once handling
1429 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,
1432 bool err = xilinx_dpdma_err(isr, eisr);
1435 dev_dbg_ratelimited(xdev->dev,
1436 "error irq: isr = 0x%08x, eisr = 0x%08x\n",
1439 /* Disable channel error interrupts until errors are handled. */
1440 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1441 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR);
1442 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1443 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR);
1445 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1446 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))
1447 tasklet_schedule(&xdev->chan[i]->err_task);
1451 * xilinx_dpdma_enable_irq - Enable interrupts
1452 * @xdev: DPDMA device
1454 * Enable interrupts.
1456 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)
1458 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1459 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1463 * xilinx_dpdma_disable_irq - Disable interrupts
1464 * @xdev: DPDMA device
1466 * Disable interrupts.
1468 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
1470 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1471 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1475 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling
1476 * @t: pointer to the tasklet associated with this handler
1478 * Per channel error handling tasklet. This function waits for the outstanding
1479 * transaction to complete and triggers error handling. After error handling,
1480 * re-enable channel error interrupts, and restart the channel if needed.
1482 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t)
1484 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task);
1485 struct xilinx_dpdma_device *xdev = chan->xdev;
1486 unsigned long flags;
1488 /* Proceed error handling even when polling fails. */
1489 xilinx_dpdma_chan_poll_no_ostand(chan);
1491 xilinx_dpdma_chan_handle_err(chan);
1493 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1494 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id);
1495 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1496 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id);
1498 spin_lock_irqsave(&chan->lock, flags);
1499 spin_lock(&chan->vchan.lock);
1500 xilinx_dpdma_chan_queue_transfer(chan);
1501 spin_unlock(&chan->vchan.lock);
1502 spin_unlock_irqrestore(&chan->lock, flags);
1505 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)
1507 struct xilinx_dpdma_device *xdev = data;
1513 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1514 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1515 if (!status && !error)
1518 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1519 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1521 if (status & XILINX_DPDMA_INTR_VSYNC) {
1523 * There's a single VSYNC interrupt that needs to be processed
1524 * by each running channel to update the active descriptor.
1526 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1527 struct xilinx_dpdma_chan *chan = xdev->chan[i];
1530 xilinx_dpdma_chan_vsync_irq(chan);
1534 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status);
1536 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1537 xilinx_dpdma_chan_done_irq(xdev->chan[i]);
1540 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status);
1542 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1543 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]);
1546 mask = status & XILINX_DPDMA_INTR_ERR_ALL;
1548 xilinx_dpdma_handle_err_irq(xdev, mask, error);
1553 /* -----------------------------------------------------------------------------
1554 * Initialization & Cleanup
1557 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,
1558 unsigned int chan_id)
1560 struct xilinx_dpdma_chan *chan;
1562 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
1567 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1568 + XILINX_DPDMA_CH_OFFSET * chan->id;
1569 chan->running = false;
1572 spin_lock_init(&chan->lock);
1573 init_waitqueue_head(&chan->wait_to_stop);
1575 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task);
1577 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc;
1578 vchan_init(&chan->vchan, &xdev->common);
1580 xdev->chan[chan->id] = chan;
1585 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)
1590 tasklet_kill(&chan->err_task);
1591 list_del(&chan->vchan.chan.device_node);
1594 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
1595 struct of_dma *ofdma)
1597 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
1598 uint32_t chan_id = dma_spec->args[0];
1600 if (chan_id >= ARRAY_SIZE(xdev->chan))
1603 if (!xdev->chan[chan_id])
1606 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
1609 static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)
1614 /* Disable all interrupts */
1615 xilinx_dpdma_disable_irq(xdev);
1617 /* Stop all channels */
1618 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1619 reg = xdev->reg + XILINX_DPDMA_CH_BASE
1620 + XILINX_DPDMA_CH_OFFSET * i;
1621 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
1624 /* Clear the interrupt status registers */
1625 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
1626 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
1629 static int xilinx_dpdma_probe(struct platform_device *pdev)
1631 struct xilinx_dpdma_device *xdev;
1632 struct dma_device *ddev;
1636 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
1640 xdev->dev = &pdev->dev;
1641 xdev->ext_addr = sizeof(dma_addr_t) > 4;
1643 INIT_LIST_HEAD(&xdev->common.channels);
1645 platform_set_drvdata(pdev, xdev);
1647 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk");
1648 if (IS_ERR(xdev->axi_clk))
1649 return PTR_ERR(xdev->axi_clk);
1651 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1652 if (IS_ERR(xdev->reg))
1653 return PTR_ERR(xdev->reg);
1655 dpdma_hw_init(xdev);
1657 xdev->irq = platform_get_irq(pdev, 0);
1658 if (xdev->irq < 0) {
1659 dev_err(xdev->dev, "failed to get platform irq\n");
1663 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED,
1664 dev_name(xdev->dev), xdev);
1666 dev_err(xdev->dev, "failed to request IRQ\n");
1670 ddev = &xdev->common;
1671 ddev->dev = &pdev->dev;
1673 dma_cap_set(DMA_SLAVE, ddev->cap_mask);
1674 dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
1675 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask);
1676 dma_cap_set(DMA_REPEAT, ddev->cap_mask);
1677 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask);
1678 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1);
1680 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources;
1681 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources;
1682 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma;
1683 /* TODO: Can we achieve better granularity ? */
1684 ddev->device_tx_status = dma_cookie_status;
1685 ddev->device_issue_pending = xilinx_dpdma_issue_pending;
1686 ddev->device_config = xilinx_dpdma_config;
1687 ddev->device_pause = xilinx_dpdma_pause;
1688 ddev->device_resume = xilinx_dpdma_resume;
1689 ddev->device_terminate_all = xilinx_dpdma_terminate_all;
1690 ddev->device_synchronize = xilinx_dpdma_synchronize;
1691 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED);
1692 ddev->directions = BIT(DMA_MEM_TO_DEV);
1693 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1695 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) {
1696 ret = xilinx_dpdma_chan_init(xdev, i);
1698 dev_err(xdev->dev, "failed to initialize channel %u\n",
1704 ret = clk_prepare_enable(xdev->axi_clk);
1706 dev_err(xdev->dev, "failed to enable the axi clock\n");
1710 ret = dma_async_device_register(ddev);
1712 dev_err(xdev->dev, "failed to register the dma device\n");
1713 goto error_dma_async;
1716 ret = of_dma_controller_register(xdev->dev->of_node,
1717 of_dma_xilinx_xlate, ddev);
1719 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n");
1723 xilinx_dpdma_enable_irq(xdev);
1725 xilinx_dpdma_debugfs_init(xdev);
1727 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n");
1732 dma_async_device_unregister(ddev);
1734 clk_disable_unprepare(xdev->axi_clk);
1736 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1737 xilinx_dpdma_chan_remove(xdev->chan[i]);
1739 free_irq(xdev->irq, xdev);
1744 static int xilinx_dpdma_remove(struct platform_device *pdev)
1746 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);
1749 /* Start by disabling the IRQ to avoid races during cleanup. */
1750 free_irq(xdev->irq, xdev);
1752 xilinx_dpdma_disable_irq(xdev);
1753 of_dma_controller_free(pdev->dev.of_node);
1754 dma_async_device_unregister(&xdev->common);
1755 clk_disable_unprepare(xdev->axi_clk);
1757 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1758 xilinx_dpdma_chan_remove(xdev->chan[i]);
1763 static const struct of_device_id xilinx_dpdma_of_match[] = {
1764 { .compatible = "xlnx,zynqmp-dpdma",},
1765 { /* end of table */ },
1767 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match);
1769 static struct platform_driver xilinx_dpdma_driver = {
1770 .probe = xilinx_dpdma_probe,
1771 .remove = xilinx_dpdma_remove,
1773 .name = "xilinx-zynqmp-dpdma",
1774 .of_match_table = xilinx_dpdma_of_match,
1778 module_platform_driver(xilinx_dpdma_driver);
1780 MODULE_AUTHOR("Xilinx, Inc.");
1781 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver");
1782 MODULE_LICENSE("GPL v2");