drivers/dma/xilinx/xilinx_dma.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * DMA driver for Xilinx Video DMA Engine
   4  *
   5  * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
   6  *
   7  * Based on the Freescale DMA driver.
   8  *
   9  * Description:
  10  * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
  11  * core that provides high-bandwidth direct memory access between memory
  12  * and AXI4-Stream type video target peripherals. The core provides efficient
  13  * two dimensional DMA operations with independent asynchronous read (S2MM)
  14  * and write (MM2S) channel operation. It can be configured to have either
  15  * one channel or two channels. If configured as two channels, one is to
  16  * transmit to the video device (MM2S) and another is to receive from the
  17  * video device (S2MM). Initialization, status, interrupt and management
  18  * registers are accessed through an AXI4-Lite slave interface.
  19  *
  20  * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
  21  * provides high-bandwidth one dimensional direct memory access between memory
  22  * and AXI4-Stream target peripherals. It supports one receive and one
  23  * transmit channel, both of them optional at synthesis time.
  24  *
  25  * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
  26  * Access (DMA) between a memory-mapped source address and a memory-mapped
  27  * destination address.
  28  *
  29  * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
  30  * Xilinx IP that provides high-bandwidth direct memory access between
  31  * memory and AXI4-Stream target peripherals. It provides scatter gather
  32  * (SG) interface with multiple channels independent configuration support.
  33  *
  34  */
  35
  36 #include <linux/bitops.h>
  37 #include <linux/dmapool.h>
  38 #include <linux/dma/xilinx_dma.h>
  39 #include <linux/init.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/io.h>
  42 #include <linux/iopoll.h>
  43 #include <linux/module.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_dma.h>
  46 #include <linux/of_platform.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/slab.h>
  49 #include <linux/clk.h>
  50 #include <linux/io-64-nonatomic-lo-hi.h>
  51
  52 #include "../dmaengine.h"
  53
  54 /* Register/Descriptor Offsets */
  55 #define XILINX_DMA_MM2S_CTRL_OFFSET             0x0000
  56 #define XILINX_DMA_S2MM_CTRL_OFFSET             0x0030
  57 #define XILINX_VDMA_MM2S_DESC_OFFSET            0x0050
  58 #define XILINX_VDMA_S2MM_DESC_OFFSET            0x00a0
  59
  60 /* Control Registers */
  61 #define XILINX_DMA_REG_DMACR                    0x0000
  62 #define XILINX_DMA_DMACR_DELAY_MAX              0xff
  63 #define XILINX_DMA_DMACR_DELAY_SHIFT            24
  64 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX        0xff
  65 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT      16
  66 #define XILINX_DMA_DMACR_ERR_IRQ                BIT(14)
  67 #define XILINX_DMA_DMACR_DLY_CNT_IRQ            BIT(13)
  68 #define XILINX_DMA_DMACR_FRM_CNT_IRQ            BIT(12)
  69 #define XILINX_DMA_DMACR_MASTER_SHIFT           8
  70 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
  71 #define XILINX_DMA_DMACR_FRAMECNT_EN            BIT(4)
  72 #define XILINX_DMA_DMACR_GENLOCK_EN             BIT(3)
  73 #define XILINX_DMA_DMACR_RESET                  BIT(2)
  74 #define XILINX_DMA_DMACR_CIRC_EN                BIT(1)
  75 #define XILINX_DMA_DMACR_RUNSTOP                BIT(0)
  76 #define XILINX_DMA_DMACR_FSYNCSRC_MASK          GENMASK(6, 5)
  77 #define XILINX_DMA_DMACR_DELAY_MASK             GENMASK(31, 24)
  78 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK       GENMASK(23, 16)
  79 #define XILINX_DMA_DMACR_MASTER_MASK            GENMASK(11, 8)
  80
  81 #define XILINX_DMA_REG_DMASR                    0x0004
  82 #define XILINX_DMA_DMASR_EOL_LATE_ERR           BIT(15)
  83 #define XILINX_DMA_DMASR_ERR_IRQ                BIT(14)
  84 #define XILINX_DMA_DMASR_DLY_CNT_IRQ            BIT(13)
  85 #define XILINX_DMA_DMASR_FRM_CNT_IRQ            BIT(12)
  86 #define XILINX_DMA_DMASR_SOF_LATE_ERR           BIT(11)
  87 #define XILINX_DMA_DMASR_SG_DEC_ERR             BIT(10)
  88 #define XILINX_DMA_DMASR_SG_SLV_ERR             BIT(9)
  89 #define XILINX_DMA_DMASR_EOF_EARLY_ERR          BIT(8)
  90 #define XILINX_DMA_DMASR_SOF_EARLY_ERR          BIT(7)
  91 #define XILINX_DMA_DMASR_DMA_DEC_ERR            BIT(6)
  92 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR          BIT(5)
  93 #define XILINX_DMA_DMASR_DMA_INT_ERR            BIT(4)
  94 #define XILINX_DMA_DMASR_SG_MASK                BIT(3)
  95 #define XILINX_DMA_DMASR_IDLE                   BIT(1)
  96 #define XILINX_DMA_DMASR_HALTED         BIT(0)
  97 #define XILINX_DMA_DMASR_DELAY_MASK             GENMASK(31, 24)
  98 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK       GENMASK(23, 16)
  99
 100 #define XILINX_DMA_REG_CURDESC                  0x0008
 101 #define XILINX_DMA_REG_TAILDESC         0x0010
 102 #define XILINX_DMA_REG_REG_INDEX                0x0014
 103 #define XILINX_DMA_REG_FRMSTORE         0x0018
 104 #define XILINX_DMA_REG_THRESHOLD                0x001c
 105 #define XILINX_DMA_REG_FRMPTR_STS               0x0024
 106 #define XILINX_DMA_REG_PARK_PTR         0x0028
 107 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT        8
 108 #define XILINX_DMA_PARK_PTR_WR_REF_MASK         GENMASK(12, 8)
 109 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT        0
 110 #define XILINX_DMA_PARK_PTR_RD_REF_MASK         GENMASK(4, 0)
 111 #define XILINX_DMA_REG_VDMA_VERSION             0x002c
 112
 113 /* Register Direct Mode Registers */
 114 #define XILINX_DMA_REG_VSIZE                    0x0000
 115 #define XILINX_DMA_REG_HSIZE                    0x0004
 116
 117 #define XILINX_DMA_REG_FRMDLY_STRIDE            0x0008
 118 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT   24
 119 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT   0
 120
 121 #define XILINX_VDMA_REG_START_ADDRESS(n)        (0x000c + 4 * (n))
 122 #define XILINX_VDMA_REG_START_ADDRESS_64(n)     (0x000c + 8 * (n))
 123
 124 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP    0x00ec
 125 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP        BIT(0)
 126
 127 /* HW specific definitions */
 128 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE       0x20
 129 #define XILINX_DMA_MAX_CHANS_PER_DEVICE         0x2
 130 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE        0x1
 131
 132 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK   \
 133                 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
 134                  XILINX_DMA_DMASR_DLY_CNT_IRQ | \
 135                  XILINX_DMA_DMASR_ERR_IRQ)
 136
 137 #define XILINX_DMA_DMASR_ALL_ERR_MASK   \
 138                 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
 139                  XILINX_DMA_DMASR_SOF_LATE_ERR | \
 140                  XILINX_DMA_DMASR_SG_DEC_ERR | \
 141                  XILINX_DMA_DMASR_SG_SLV_ERR | \
 142                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 143                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 144                  XILINX_DMA_DMASR_DMA_DEC_ERR | \
 145                  XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
 146                  XILINX_DMA_DMASR_DMA_INT_ERR)
 147
 148 /*
 149  * Recoverable errors are DMA Internal error, SOF Early, EOF Early
 150  * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
 151  * is enabled in the h/w system.
 152  */
 153 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK       \
 154                 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
 155                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 156                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 157                  XILINX_DMA_DMASR_DMA_INT_ERR)
 158
 159 /* Axi VDMA Flush on Fsync bits */
 160 #define XILINX_DMA_FLUSH_S2MM           3
 161 #define XILINX_DMA_FLUSH_MM2S           2
 162 #define XILINX_DMA_FLUSH_BOTH           1
 163
 164 /* Delay loop counter to prevent hardware failure */
 165 #define XILINX_DMA_LOOP_COUNT           1000000
 166
 167 /* AXI DMA Specific Registers/Offsets */
 168 #define XILINX_DMA_REG_SRCDSTADDR       0x18
 169 #define XILINX_DMA_REG_BTT              0x28
 170
 171 /* AXI DMA Specific Masks/Bit fields */
 172 #define XILINX_DMA_MAX_TRANS_LEN_MIN    8
 173 #define XILINX_DMA_MAX_TRANS_LEN_MAX    23
 174 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
 175 #define XILINX_DMA_CR_COALESCE_MAX      GENMASK(23, 16)
 176 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
 177 #define XILINX_DMA_CR_COALESCE_SHIFT    16
 178 #define XILINX_DMA_BD_SOP               BIT(27)
 179 #define XILINX_DMA_BD_EOP               BIT(26)
 180 #define XILINX_DMA_COALESCE_MAX         255
 181 #define XILINX_DMA_NUM_DESCS            255
 182 #define XILINX_DMA_NUM_APP_WORDS        5
 183
 184 /* AXI CDMA Specific Registers/Offsets */
 185 #define XILINX_CDMA_REG_SRCADDR         0x18
 186 #define XILINX_CDMA_REG_DSTADDR         0x20
 187
 188 /* AXI CDMA Specific Masks */
 189 #define XILINX_CDMA_CR_SGMODE          BIT(3)
 190
 191 #define xilinx_prep_dma_addr_t(addr)    \
 192         ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
 193
 194 /* AXI MCDMA Specific Registers/Offsets */
 195 #define XILINX_MCDMA_MM2S_CTRL_OFFSET           0x0000
 196 #define XILINX_MCDMA_S2MM_CTRL_OFFSET           0x0500
 197 #define XILINX_MCDMA_CHEN_OFFSET                0x0008
 198 #define XILINX_MCDMA_CH_ERR_OFFSET              0x0010
 199 #define XILINX_MCDMA_RXINT_SER_OFFSET           0x0020
 200 #define XILINX_MCDMA_TXINT_SER_OFFSET           0x0028
 201 #define XILINX_MCDMA_CHAN_CR_OFFSET(x)          (0x40 + (x) * 0x40)
 202 #define XILINX_MCDMA_CHAN_SR_OFFSET(x)          (0x44 + (x) * 0x40)
 203 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x)       (0x48 + (x) * 0x40)
 204 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x)       (0x50 + (x) * 0x40)
 205
 206 /* AXI MCDMA Specific Masks/Shifts */
 207 #define XILINX_MCDMA_COALESCE_SHIFT             16
 208 #define XILINX_MCDMA_COALESCE_MAX               24
 209 #define XILINX_MCDMA_IRQ_ALL_MASK               GENMASK(7, 5)
 210 #define XILINX_MCDMA_COALESCE_MASK              GENMASK(23, 16)
 211 #define XILINX_MCDMA_CR_RUNSTOP_MASK            BIT(0)
 212 #define XILINX_MCDMA_IRQ_IOC_MASK               BIT(5)
 213 #define XILINX_MCDMA_IRQ_DELAY_MASK             BIT(6)
 214 #define XILINX_MCDMA_IRQ_ERR_MASK               BIT(7)
 215 #define XILINX_MCDMA_BD_EOP                     BIT(30)
 216 #define XILINX_MCDMA_BD_SOP                     BIT(31)
 217
 218 /**
 219  * struct xilinx_vdma_desc_hw - Hardware Descriptor
 220  * @next_desc: Next Descriptor Pointer @0x00
 221  * @pad1: Reserved @0x04
 222  * @buf_addr: Buffer address @0x08
 223  * @buf_addr_msb: MSB of Buffer address @0x0C
 224  * @vsize: Vertical Size @0x10
 225  * @hsize: Horizontal Size @0x14
 226  * @stride: Number of bytes between the first
 227  *          pixels of each horizontal line @0x18
 228  */
 229 struct xilinx_vdma_desc_hw {
 230         u32 next_desc;
 231         u32 pad1;
 232         u32 buf_addr;
 233         u32 buf_addr_msb;
 234         u32 vsize;
 235         u32 hsize;
 236         u32 stride;
 237 } __aligned(64);
 238
 239 /**
 240  * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
 241  * @next_desc: Next Descriptor Pointer @0x00
 242  * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 243  * @buf_addr: Buffer address @0x08
 244  * @buf_addr_msb: MSB of Buffer address @0x0C
 245  * @reserved1: Reserved @0x10
 246  * @reserved2: Reserved @0x14
 247  * @control: Control field @0x18
 248  * @status: Status field @0x1C
 249  * @app: APP Fields @0x20 - 0x30
 250  */
 251 struct xilinx_axidma_desc_hw {
 252         u32 next_desc;
 253         u32 next_desc_msb;
 254         u32 buf_addr;
 255         u32 buf_addr_msb;
 256         u32 reserved1;
 257         u32 reserved2;
 258         u32 control;
 259         u32 status;
 260         u32 app[XILINX_DMA_NUM_APP_WORDS];
 261 } __aligned(64);
 262
 263 /**
 264  * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
 265  * @next_desc: Next Descriptor Pointer @0x00
 266  * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 267  * @buf_addr: Buffer address @0x08
 268  * @buf_addr_msb: MSB of Buffer address @0x0C
 269  * @rsvd: Reserved field @0x10
 270  * @control: Control Information field @0x14
 271  * @status: Status field @0x18
 272  * @sideband_status: Status of sideband signals @0x1C
 273  * @app: APP Fields @0x20 - 0x30
 274  */
 275 struct xilinx_aximcdma_desc_hw {
 276         u32 next_desc;
 277         u32 next_desc_msb;
 278         u32 buf_addr;
 279         u32 buf_addr_msb;
 280         u32 rsvd;
 281         u32 control;
 282         u32 status;
 283         u32 sideband_status;
 284         u32 app[XILINX_DMA_NUM_APP_WORDS];
 285 } __aligned(64);
 286
 287 /**
 288  * struct xilinx_cdma_desc_hw - Hardware Descriptor
 289  * @next_desc: Next Descriptor Pointer @0x00
 290  * @next_desc_msb: Next Descriptor Pointer MSB @0x04
 291  * @src_addr: Source address @0x08
 292  * @src_addr_msb: Source address MSB @0x0C
 293  * @dest_addr: Destination address @0x10
 294  * @dest_addr_msb: Destination address MSB @0x14
 295  * @control: Control field @0x18
 296  * @status: Status field @0x1C
 297  */
 298 struct xilinx_cdma_desc_hw {
 299         u32 next_desc;
 300         u32 next_desc_msb;
 301         u32 src_addr;
 302         u32 src_addr_msb;
 303         u32 dest_addr;
 304         u32 dest_addr_msb;
 305         u32 control;
 306         u32 status;
 307 } __aligned(64);
 308
 309 /**
 310  * struct xilinx_vdma_tx_segment - Descriptor segment
 311  * @hw: Hardware descriptor
 312  * @node: Node in the descriptor segments list
 313  * @phys: Physical address of segment
 314  */
 315 struct xilinx_vdma_tx_segment {
 316         struct xilinx_vdma_desc_hw hw;
 317         struct list_head node;
 318         dma_addr_t phys;
 319 } __aligned(64);
 320
 321 /**
 322  * struct xilinx_axidma_tx_segment - Descriptor segment
 323  * @hw: Hardware descriptor
 324  * @node: Node in the descriptor segments list
 325  * @phys: Physical address of segment
 326  */
 327 struct xilinx_axidma_tx_segment {
 328         struct xilinx_axidma_desc_hw hw;
 329         struct list_head node;
 330         dma_addr_t phys;
 331 } __aligned(64);
 332
 333 /**
 334  * struct xilinx_aximcdma_tx_segment - Descriptor segment
 335  * @hw: Hardware descriptor
 336  * @node: Node in the descriptor segments list
 337  * @phys: Physical address of segment
 338  */
 339 struct xilinx_aximcdma_tx_segment {
 340         struct xilinx_aximcdma_desc_hw hw;
 341         struct list_head node;
 342         dma_addr_t phys;
 343 } __aligned(64);
 344
 345 /**
 346  * struct xilinx_cdma_tx_segment - Descriptor segment
 347  * @hw: Hardware descriptor
 348  * @node: Node in the descriptor segments list
 349  * @phys: Physical address of segment
 350  */
 351 struct xilinx_cdma_tx_segment {
 352         struct xilinx_cdma_desc_hw hw;
 353         struct list_head node;
 354         dma_addr_t phys;
 355 } __aligned(64);
 356
 357 /**
 358  * struct xilinx_dma_tx_descriptor - Per Transaction structure
 359  * @async_tx: Async transaction descriptor
 360  * @segments: TX segments list
 361  * @node: Node in the channel descriptors list
 362  * @cyclic: Check for cyclic transfers.
 363  * @err: Whether the descriptor has an error.
 364  * @residue: Residue of the completed descriptor
 365  */
 366 struct xilinx_dma_tx_descriptor {
 367         struct dma_async_tx_descriptor async_tx;
 368         struct list_head segments;
 369         struct list_head node;
 370         bool cyclic;
 371         bool err;
 372         u32 residue;
 373 };
 374
 375 /**
 376  * struct xilinx_dma_chan - Driver specific DMA channel structure
 377  * @xdev: Driver specific device structure
 378  * @ctrl_offset: Control registers offset
 379  * @desc_offset: TX descriptor registers offset
 380  * @lock: Descriptor operation lock
 381  * @pending_list: Descriptors waiting
 382  * @active_list: Descriptors ready to submit
 383  * @done_list: Complete descriptors
 384  * @free_seg_list: Free descriptors
 385  * @common: DMA common channel
 386  * @desc_pool: Descriptors pool
 387  * @dev: The dma device
 388  * @irq: Channel IRQ
 389  * @id: Channel ID
 390  * @direction: Transfer direction
 391  * @num_frms: Number of frames
 392  * @has_sg: Support scatter transfers
 393  * @cyclic: Check for cyclic transfers.
 394  * @genlock: Support genlock mode
 395  * @err: Channel has errors
 396  * @idle: Check for channel idle
 397  * @terminating: Check for channel being synchronized by user
 398  * @tasklet: Cleanup work after irq
 399  * @config: Device configuration info
 400  * @flush_on_fsync: Flush on Frame sync
 401  * @desc_pendingcount: Descriptor pending count
 402  * @ext_addr: Indicates 64 bit addressing is supported by dma channel
 403  * @desc_submitcount: Descriptor h/w submitted count
 404  * @seg_v: Statically allocated segments base
 405  * @seg_mv: Statically allocated segments base for MCDMA
 406  * @seg_p: Physical allocated segments base
 407  * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
 408  * @cyclic_seg_p: Physical allocated segments base for cyclic dma
 409  * @start_transfer: Differentiate b/w DMA IP's transfer
 410  * @stop_transfer: Differentiate b/w DMA IP's quiesce
 411  * @tdest: TDEST value for mcdma
 412  * @has_vflip: S2MM vertical flip
 413  */
 414 struct xilinx_dma_chan {
 415         struct xilinx_dma_device *xdev;
 416         u32 ctrl_offset;
 417         u32 desc_offset;
 418         spinlock_t lock;
 419         struct list_head pending_list;
 420         struct list_head active_list;
 421         struct list_head done_list;
 422         struct list_head free_seg_list;
 423         struct dma_chan common;
 424         struct dma_pool *desc_pool;
 425         struct device *dev;
 426         int irq;
 427         int id;
 428         enum dma_transfer_direction direction;
 429         int num_frms;
 430         bool has_sg;
 431         bool cyclic;
 432         bool genlock;
 433         bool err;
 434         bool idle;
 435         bool terminating;
 436         struct tasklet_struct tasklet;
 437         struct xilinx_vdma_config config;
 438         bool flush_on_fsync;
 439         u32 desc_pendingcount;
 440         bool ext_addr;
 441         u32 desc_submitcount;
 442         struct xilinx_axidma_tx_segment *seg_v;
 443         struct xilinx_aximcdma_tx_segment *seg_mv;
 444         dma_addr_t seg_p;
 445         struct xilinx_axidma_tx_segment *cyclic_seg_v;
 446         dma_addr_t cyclic_seg_p;
 447         void (*start_transfer)(struct xilinx_dma_chan *chan);
 448         int (*stop_transfer)(struct xilinx_dma_chan *chan);
 449         u16 tdest;
 450         bool has_vflip;
 451 };
 452
 453 /**
 454  * enum xdma_ip_type - DMA IP type.
 455  *
 456  * @XDMA_TYPE_AXIDMA: Axi dma ip.
 457  * @XDMA_TYPE_CDMA: Axi cdma ip.
 458  * @XDMA_TYPE_VDMA: Axi vdma ip.
 459  * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
 460  *
 461  */
 462 enum xdma_ip_type {
 463         XDMA_TYPE_AXIDMA = 0,
 464         XDMA_TYPE_CDMA,
 465         XDMA_TYPE_VDMA,
 466         XDMA_TYPE_AXIMCDMA
 467 };
 468
 469 struct xilinx_dma_config {
 470         enum xdma_ip_type dmatype;
 471         int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
 472                         struct clk **tx_clk, struct clk **txs_clk,
 473                         struct clk **rx_clk, struct clk **rxs_clk);
 474         irqreturn_t (*irq_handler)(int irq, void *data);
 475         const int max_channels;
 476 };
 477
 478 /**
 479  * struct xilinx_dma_device - DMA device structure
 480  * @regs: I/O mapped base address
 481  * @dev: Device Structure
 482  * @common: DMA device structure
 483  * @chan: Driver specific DMA channel
 484  * @flush_on_fsync: Flush on frame sync
 485  * @ext_addr: Indicates 64 bit addressing is supported by dma device
 486  * @pdev: Platform device structure pointer
 487  * @dma_config: DMA config structure
 488  * @axi_clk: DMA Axi4-lite interace clock
 489  * @tx_clk: DMA mm2s clock
 490  * @txs_clk: DMA mm2s stream clock
 491  * @rx_clk: DMA s2mm clock
 492  * @rxs_clk: DMA s2mm stream clock
 493  * @s2mm_chan_id: DMA s2mm channel identifier
 494  * @mm2s_chan_id: DMA mm2s channel identifier
 495  * @max_buffer_len: Max buffer length
 496  */
 497 struct xilinx_dma_device {
 498         void __iomem *regs;
 499         struct device *dev;
 500         struct dma_device common;
 501         struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
 502         u32 flush_on_fsync;
 503         bool ext_addr;
 504         struct platform_device  *pdev;
 505         const struct xilinx_dma_config *dma_config;
 506         struct clk *axi_clk;
 507         struct clk *tx_clk;
 508         struct clk *txs_clk;
 509         struct clk *rx_clk;
 510         struct clk *rxs_clk;
 511         u32 s2mm_chan_id;
 512         u32 mm2s_chan_id;
 513         u32 max_buffer_len;
 514 };
 515
 516 /* Macros */
 517 #define to_xilinx_chan(chan) \
 518         container_of(chan, struct xilinx_dma_chan, common)
 519 #define to_dma_tx_descriptor(tx) \
 520         container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
 521 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
 522         readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
 523                                   val, cond, delay_us, timeout_us)
 524
 525 /* IO accessors */
 526 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
 527 {
 528         return ioread32(chan->xdev->regs + reg);
 529 }
 530
 531 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
 532 {
 533         iowrite32(value, chan->xdev->regs + reg);
 534 }
 535
 536 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
 537                                    u32 value)
 538 {
 539         dma_write(chan, chan->desc_offset + reg, value);
 540 }
 541
 542 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
 543 {
 544         return dma_read(chan, chan->ctrl_offset + reg);
 545 }
 546
 547 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
 548                                    u32 value)
 549 {
 550         dma_write(chan, chan->ctrl_offset + reg, value);
 551 }
 552
 553 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
 554                                  u32 clr)
 555 {
 556         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
 557 }
 558
 559 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
 560                                  u32 set)
 561 {
 562         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
 563 }
 564
 565 /**
 566  * vdma_desc_write_64 - 64-bit descriptor write
 567  * @chan: Driver specific VDMA channel
 568  * @reg: Register to write
 569  * @value_lsb: lower address of the descriptor.
 570  * @value_msb: upper address of the descriptor.
 571  *
 572  * Since vdma driver is trying to write to a register offset which is not a
 573  * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
 574  * instead of a single 64 bit register write.
 575  */
 576 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
 577                                       u32 value_lsb, u32 value_msb)
 578 {
 579         /* Write the lsb 32 bits*/
 580         writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
 581
 582         /* Write the msb 32 bits */
 583         writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
 584 }
 585
 586 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
 587 {
 588         lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
 589 }
 590
 591 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
 592                                 dma_addr_t addr)
 593 {
 594         if (chan->ext_addr)
 595                 dma_writeq(chan, reg, addr);
 596         else
 597                 dma_ctrl_write(chan, reg, addr);
 598 }
 599
 600 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
 601                                      struct xilinx_axidma_desc_hw *hw,
 602                                      dma_addr_t buf_addr, size_t sg_used,
 603                                      size_t period_len)
 604 {
 605         if (chan->ext_addr) {
 606                 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
 607                 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
 608                                                  period_len);
 609         } else {
 610                 hw->buf_addr = buf_addr + sg_used + period_len;
 611         }
 612 }
 613
 614 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
 615                                        struct xilinx_aximcdma_desc_hw *hw,
 616                                        dma_addr_t buf_addr, size_t sg_used)
 617 {
 618         if (chan->ext_addr) {
 619                 hw->buf_addr = lower_32_bits(buf_addr + sg_used);
 620                 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used);
 621         } else {
 622                 hw->buf_addr = buf_addr + sg_used;
 623         }
 624 }
 625
 626 /* -----------------------------------------------------------------------------
 627  * Descriptors and segments alloc and free
 628  */
 629
 630 /**
 631  * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
 632  * @chan: Driver specific DMA channel
 633  *
 634  * Return: The allocated segment on success and NULL on failure.
 635  */
 636 static struct xilinx_vdma_tx_segment *
 637 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 638 {
 639         struct xilinx_vdma_tx_segment *segment;
 640         dma_addr_t phys;
 641
 642         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 643         if (!segment)
 644                 return NULL;
 645
 646         segment->phys = phys;
 647
 648         return segment;
 649 }
 650
 651 /**
 652  * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
 653  * @chan: Driver specific DMA channel
 654  *
 655  * Return: The allocated segment on success and NULL on failure.
 656  */
 657 static struct xilinx_cdma_tx_segment *
 658 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 659 {
 660         struct xilinx_cdma_tx_segment *segment;
 661         dma_addr_t phys;
 662
 663         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 664         if (!segment)
 665                 return NULL;
 666
 667         segment->phys = phys;
 668
 669         return segment;
 670 }
 671
 672 /**
 673  * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
 674  * @chan: Driver specific DMA channel
 675  *
 676  * Return: The allocated segment on success and NULL on failure.
 677  */
 678 static struct xilinx_axidma_tx_segment *
 679 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 680 {
 681         struct xilinx_axidma_tx_segment *segment = NULL;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&chan->lock, flags);
 685         if (!list_empty(&chan->free_seg_list)) {
 686                 segment = list_first_entry(&chan->free_seg_list,
 687                                            struct xilinx_axidma_tx_segment,
 688                                            node);
 689                 list_del(&segment->node);
 690         }
 691         spin_unlock_irqrestore(&chan->lock, flags);
 692
 693         if (!segment)
 694                 dev_dbg(chan->dev, "Could not find free tx segment\n");
 695
 696         return segment;
 697 }
 698
 699 /**
 700  * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
 701  * @chan: Driver specific DMA channel
 702  *
 703  * Return: The allocated segment on success and NULL on failure.
 704  */
 705 static struct xilinx_aximcdma_tx_segment *
 706 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 707 {
 708         struct xilinx_aximcdma_tx_segment *segment = NULL;
 709         unsigned long flags;
 710
 711         spin_lock_irqsave(&chan->lock, flags);
 712         if (!list_empty(&chan->free_seg_list)) {
 713                 segment = list_first_entry(&chan->free_seg_list,
 714                                            struct xilinx_aximcdma_tx_segment,
 715                                            node);
 716                 list_del(&segment->node);
 717         }
 718         spin_unlock_irqrestore(&chan->lock, flags);
 719
 720         return segment;
 721 }
 722
 723 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
 724 {
 725         u32 next_desc = hw->next_desc;
 726         u32 next_desc_msb = hw->next_desc_msb;
 727
 728         memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
 729
 730         hw->next_desc = next_desc;
 731         hw->next_desc_msb = next_desc_msb;
 732 }
 733
 734 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
 735 {
 736         u32 next_desc = hw->next_desc;
 737         u32 next_desc_msb = hw->next_desc_msb;
 738
 739         memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw));
 740
 741         hw->next_desc = next_desc;
 742         hw->next_desc_msb = next_desc_msb;
 743 }
 744
 745 /**
 746  * xilinx_dma_free_tx_segment - Free transaction segment
 747  * @chan: Driver specific DMA channel
 748  * @segment: DMA transaction segment
 749  */
 750 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
 751                                 struct xilinx_axidma_tx_segment *segment)
 752 {
 753         xilinx_dma_clean_hw_desc(&segment->hw);
 754
 755         list_add_tail(&segment->node, &chan->free_seg_list);
 756 }
 757
 758 /**
 759  * xilinx_mcdma_free_tx_segment - Free transaction segment
 760  * @chan: Driver specific DMA channel
 761  * @segment: DMA transaction segment
 762  */
 763 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
 764                                          struct xilinx_aximcdma_tx_segment *
 765                                          segment)
 766 {
 767         xilinx_mcdma_clean_hw_desc(&segment->hw);
 768
 769         list_add_tail(&segment->node, &chan->free_seg_list);
 770 }
 771
 772 /**
 773  * xilinx_cdma_free_tx_segment - Free transaction segment
 774  * @chan: Driver specific DMA channel
 775  * @segment: DMA transaction segment
 776  */
 777 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
 778                                 struct xilinx_cdma_tx_segment *segment)
 779 {
 780         dma_pool_free(chan->desc_pool, segment, segment->phys);
 781 }
 782
 783 /**
 784  * xilinx_vdma_free_tx_segment - Free transaction segment
 785  * @chan: Driver specific DMA channel
 786  * @segment: DMA transaction segment
 787  */
 788 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
 789                                         struct xilinx_vdma_tx_segment *segment)
 790 {
 791         dma_pool_free(chan->desc_pool, segment, segment->phys);
 792 }
 793
 794 /**
 795  * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor
 796  * @chan: Driver specific DMA channel
 797  *
 798  * Return: The allocated descriptor on success and NULL on failure.
 799  */
 800 static struct xilinx_dma_tx_descriptor *
 801 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
 802 {
 803         struct xilinx_dma_tx_descriptor *desc;
 804
 805         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 806         if (!desc)
 807                 return NULL;
 808
 809         INIT_LIST_HEAD(&desc->segments);
 810
 811         return desc;
 812 }
 813
 814 /**
 815  * xilinx_dma_free_tx_descriptor - Free transaction descriptor
 816  * @chan: Driver specific DMA channel
 817  * @desc: DMA transaction descriptor
 818  */
 819 static void
 820 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
 821                                struct xilinx_dma_tx_descriptor *desc)
 822 {
 823         struct xilinx_vdma_tx_segment *segment, *next;
 824         struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
 825         struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
 826         struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next;
 827
 828         if (!desc)
 829                 return;
 830
 831         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
 832                 list_for_each_entry_safe(segment, next, &desc->segments, node) {
 833                         list_del(&segment->node);
 834                         xilinx_vdma_free_tx_segment(chan, segment);
 835                 }
 836         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 837                 list_for_each_entry_safe(cdma_segment, cdma_next,
 838                                          &desc->segments, node) {
 839                         list_del(&cdma_segment->node);
 840                         xilinx_cdma_free_tx_segment(chan, cdma_segment);
 841                 }
 842         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 843                 list_for_each_entry_safe(axidma_segment, axidma_next,
 844                                          &desc->segments, node) {
 845                         list_del(&axidma_segment->node);
 846                         xilinx_dma_free_tx_segment(chan, axidma_segment);
 847                 }
 848         } else {
 849                 list_for_each_entry_safe(aximcdma_segment, aximcdma_next,
 850                                          &desc->segments, node) {
 851                         list_del(&aximcdma_segment->node);
 852                         xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
 853                 }
 854         }
 855
 856         kfree(desc);
 857 }
 858
 859 /* Required functions */
 860
 861 /**
 862  * xilinx_dma_free_desc_list - Free descriptors list
 863  * @chan: Driver specific DMA channel
 864  * @list: List to parse and delete the descriptor
 865  */
 866 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
 867                                         struct list_head *list)
 868 {
 869         struct xilinx_dma_tx_descriptor *desc, *next;
 870
 871         list_for_each_entry_safe(desc, next, list, node) {
 872                 list_del(&desc->node);
 873                 xilinx_dma_free_tx_descriptor(chan, desc);
 874         }
 875 }
 876
 877 /**
 878  * xilinx_dma_free_descriptors - Free channel descriptors
 879  * @chan: Driver specific DMA channel
 880  */
 881 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
 882 {
 883         unsigned long flags;
 884
 885         spin_lock_irqsave(&chan->lock, flags);
 886
 887         xilinx_dma_free_desc_list(chan, &chan->pending_list);
 888         xilinx_dma_free_desc_list(chan, &chan->done_list);
 889         xilinx_dma_free_desc_list(chan, &chan->active_list);
 890
 891         spin_unlock_irqrestore(&chan->lock, flags);
 892 }
 893
 894 /**
 895  * xilinx_dma_free_chan_resources - Free channel resources
 896  * @dchan: DMA channel
 897  */
 898 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
 899 {
 900         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
 901         unsigned long flags;
 902
 903         dev_dbg(chan->dev, "Free all channel resources.\n");
 904
 905         xilinx_dma_free_descriptors(chan);
 906
 907         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 908                 spin_lock_irqsave(&chan->lock, flags);
 909                 INIT_LIST_HEAD(&chan->free_seg_list);
 910                 spin_unlock_irqrestore(&chan->lock, flags);
 911
 912                 /* Free memory that is allocated for BD */
 913                 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
 914                                   XILINX_DMA_NUM_DESCS, chan->seg_v,
 915                                   chan->seg_p);
 916
 917                 /* Free Memory that is allocated for cyclic DMA Mode */
 918                 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
 919                                   chan->cyclic_seg_v, chan->cyclic_seg_p);
 920         }
 921
 922         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
 923                 spin_lock_irqsave(&chan->lock, flags);
 924                 INIT_LIST_HEAD(&chan->free_seg_list);
 925                 spin_unlock_irqrestore(&chan->lock, flags);
 926
 927                 /* Free memory that is allocated for BD */
 928                 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
 929                                   XILINX_DMA_NUM_DESCS, chan->seg_mv,
 930                                   chan->seg_p);
 931         }
 932
 933         if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
 934             chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
 935                 dma_pool_destroy(chan->desc_pool);
 936                 chan->desc_pool = NULL;
 937         }
 938
 939 }
 940
 941 /**
 942  * xilinx_dma_get_residue - Compute residue for a given descriptor
 943  * @chan: Driver specific dma channel
 944  * @desc: dma transaction descriptor
 945  *
 946  * Return: The number of residue bytes for the descriptor.
 947  */
 948 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
 949                                   struct xilinx_dma_tx_descriptor *desc)
 950 {
 951         struct xilinx_cdma_tx_segment *cdma_seg;
 952         struct xilinx_axidma_tx_segment *axidma_seg;
 953         struct xilinx_aximcdma_tx_segment *aximcdma_seg;
 954         struct xilinx_cdma_desc_hw *cdma_hw;
 955         struct xilinx_axidma_desc_hw *axidma_hw;
 956         struct xilinx_aximcdma_desc_hw *aximcdma_hw;
 957         struct list_head *entry;
 958         u32 residue = 0;
 959
 960         list_for_each(entry, &desc->segments) {
 961                 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 962                         cdma_seg = list_entry(entry,
 963                                               struct xilinx_cdma_tx_segment,
 964                                               node);
 965                         cdma_hw = &cdma_seg->hw;
 966                         residue += (cdma_hw->control - cdma_hw->status) &
 967                                    chan->xdev->max_buffer_len;
 968                 } else if (chan->xdev->dma_config->dmatype ==
 969                            XDMA_TYPE_AXIDMA) {
 970                         axidma_seg = list_entry(entry,
 971                                                 struct xilinx_axidma_tx_segment,
 972                                                 node);
 973                         axidma_hw = &axidma_seg->hw;
 974                         residue += (axidma_hw->control - axidma_hw->status) &
 975                                    chan->xdev->max_buffer_len;
 976                 } else {
 977                         aximcdma_seg =
 978                                 list_entry(entry,
 979                                            struct xilinx_aximcdma_tx_segment,
 980                                            node);
 981                         aximcdma_hw = &aximcdma_seg->hw;
 982                         residue +=
 983                                 (aximcdma_hw->control - aximcdma_hw->status) &
 984                                 chan->xdev->max_buffer_len;
 985                 }
 986         }
 987
 988         return residue;
 989 }
 990
 991 /**
 992  * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
 993  * @chan: Driver specific dma channel
 994  * @desc: dma transaction descriptor
 995  * @flags: flags for spin lock
 996  */
 997 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
 998                                           struct xilinx_dma_tx_descriptor *desc,
 999                                           unsigned long *flags)
1000 {
1001         struct dmaengine_desc_callback cb;
1002
1003         dmaengine_desc_get_callback(&desc->async_tx, &cb);
1004         if (dmaengine_desc_callback_valid(&cb)) {
1005                 spin_unlock_irqrestore(&chan->lock, *flags);
1006                 dmaengine_desc_callback_invoke(&cb, NULL);
1007                 spin_lock_irqsave(&chan->lock, *flags);
1008         }
1009 }
1010
1011 /**
1012  * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1013  * @chan: Driver specific DMA channel
1014  */
1015 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1016 {
1017         struct xilinx_dma_tx_descriptor *desc, *next;
1018         unsigned long flags;
1019
1020         spin_lock_irqsave(&chan->lock, flags);
1021
1022         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1023                 struct dmaengine_result result;
1024
1025                 if (desc->cyclic) {
1026                         xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1027                         break;
1028                 }
1029
1030                 /* Remove from the list of running transactions */
1031                 list_del(&desc->node);
1032
1033                 if (unlikely(desc->err)) {
1034                         if (chan->direction == DMA_DEV_TO_MEM)
1035                                 result.result = DMA_TRANS_READ_FAILED;
1036                         else
1037                                 result.result = DMA_TRANS_WRITE_FAILED;
1038                 } else {
1039                         result.result = DMA_TRANS_NOERROR;
1040                 }
1041
1042                 result.residue = desc->residue;
1043
1044                 /* Run the link descriptor callback function */
1045                 spin_unlock_irqrestore(&chan->lock, flags);
1046                 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
1047                 spin_lock_irqsave(&chan->lock, flags);
1048
1049                 /* Run any dependencies, then free the descriptor */
1050                 dma_run_dependencies(&desc->async_tx);
1051                 xilinx_dma_free_tx_descriptor(chan, desc);
1052
1053                 /*
1054                  * While we ran a callback the user called a terminate function,
1055                  * which takes care of cleaning up any remaining descriptors
1056                  */
1057                 if (chan->terminating)
1058                         break;
1059         }
1060
1061         spin_unlock_irqrestore(&chan->lock, flags);
1062 }
1063
1064 /**
1065  * xilinx_dma_do_tasklet - Schedule completion tasklet
1066  * @t: Pointer to the Xilinx DMA channel structure
1067  */
1068 static void xilinx_dma_do_tasklet(struct tasklet_struct *t)
1069 {
1070         struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1071
1072         xilinx_dma_chan_desc_cleanup(chan);
1073 }
1074
1075 /**
1076  * xilinx_dma_alloc_chan_resources - Allocate channel resources
1077  * @dchan: DMA channel
1078  *
1079  * Return: '0' on success and failure value on error
1080  */
1081 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
1082 {
1083         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1084         int i;
1085
1086         /* Has this channel already been allocated? */
1087         if (chan->desc_pool)
1088                 return 0;
1089
1090         /*
1091          * We need the descriptor to be aligned to 64bytes
1092          * for meeting Xilinx VDMA specification requirement.
1093          */
1094         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1095                 /* Allocate the buffer descriptors. */
1096                 chan->seg_v = dma_alloc_coherent(chan->dev,
1097                                                  sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1098                                                  &chan->seg_p, GFP_KERNEL);
1099                 if (!chan->seg_v) {
1100                         dev_err(chan->dev,
1101                                 "unable to allocate channel %d descriptors\n",
1102                                 chan->id);
1103                         return -ENOMEM;
1104                 }
1105                 /*
1106                  * For cyclic DMA mode we need to program the tail Descriptor
1107                  * register with a value which is not a part of the BD chain
1108                  * so allocating a desc segment during channel allocation for
1109                  * programming tail descriptor.
1110                  */
1111                 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1112                                                         sizeof(*chan->cyclic_seg_v),
1113                                                         &chan->cyclic_seg_p,
1114                                                         GFP_KERNEL);
1115                 if (!chan->cyclic_seg_v) {
1116                         dev_err(chan->dev,
1117                                 "unable to allocate desc segment for cyclic DMA\n");
1118                         dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1119                                 XILINX_DMA_NUM_DESCS, chan->seg_v,
1120                                 chan->seg_p);
1121                         return -ENOMEM;
1122                 }
1123                 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1124
1125                 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1126                         chan->seg_v[i].hw.next_desc =
1127                         lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1128                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1129                         chan->seg_v[i].hw.next_desc_msb =
1130                         upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1131                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1132                         chan->seg_v[i].phys = chan->seg_p +
1133                                 sizeof(*chan->seg_v) * i;
1134                         list_add_tail(&chan->seg_v[i].node,
1135                                       &chan->free_seg_list);
1136                 }
1137         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1138                 /* Allocate the buffer descriptors. */
1139                 chan->seg_mv = dma_alloc_coherent(chan->dev,
1140                                                   sizeof(*chan->seg_mv) *
1141                                                   XILINX_DMA_NUM_DESCS,
1142                                                   &chan->seg_p, GFP_KERNEL);
1143                 if (!chan->seg_mv) {
1144                         dev_err(chan->dev,
1145                                 "unable to allocate channel %d descriptors\n",
1146                                 chan->id);
1147                         return -ENOMEM;
1148                 }
1149                 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1150                         chan->seg_mv[i].hw.next_desc =
1151                         lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1152                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1153                         chan->seg_mv[i].hw.next_desc_msb =
1154                         upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1155                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
1156                         chan->seg_mv[i].phys = chan->seg_p +
1157                                 sizeof(*chan->seg_mv) * i;
1158                         list_add_tail(&chan->seg_mv[i].node,
1159                                       &chan->free_seg_list);
1160                 }
1161         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1162                 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1163                                    chan->dev,
1164                                    sizeof(struct xilinx_cdma_tx_segment),
1165                                    __alignof__(struct xilinx_cdma_tx_segment),
1166                                    0);
1167         } else {
1168                 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1169                                      chan->dev,
1170                                      sizeof(struct xilinx_vdma_tx_segment),
1171                                      __alignof__(struct xilinx_vdma_tx_segment),
1172                                      0);
1173         }
1174
1175         if (!chan->desc_pool &&
1176             ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1177                 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1178                 dev_err(chan->dev,
1179                         "unable to allocate channel %d descriptor pool\n",
1180                         chan->id);
1181                 return -ENOMEM;
1182         }
1183
1184         dma_cookie_init(dchan);
1185
1186         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1187                 /* For AXI DMA resetting once channel will reset the
1188                  * other channel as well so enable the interrupts here.
1189                  */
1190                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1191                               XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1192         }
1193
1194         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1195                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1196                              XILINX_CDMA_CR_SGMODE);
1197
1198         return 0;
1199 }
1200
1201 /**
1202  * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1203  * @chan: Driver specific DMA channel
1204  * @size: Total data that needs to be copied
1205  * @done: Amount of data that has been already copied
1206  *
1207  * Return: Amount of data that has to be copied
1208  */
1209 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1210                                     int size, int done)
1211 {
1212         size_t copy;
1213
1214         copy = min_t(size_t, size - done,
1215                      chan->xdev->max_buffer_len);
1216
1217         if ((copy + done < size) &&
1218             chan->xdev->common.copy_align) {
1219                 /*
1220                  * If this is not the last descriptor, make sure
1221                  * the next one will be properly aligned
1222                  */
1223                 copy = rounddown(copy,
1224                                  (1 << chan->xdev->common.copy_align));
1225         }
1226         return copy;
1227 }
1228
1229 /**
1230  * xilinx_dma_tx_status - Get DMA transaction status
1231  * @dchan: DMA channel
1232  * @cookie: Transaction identifier
1233  * @txstate: Transaction state
1234  *
1235  * Return: DMA transaction status
1236  */
1237 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1238                                         dma_cookie_t cookie,
1239                                         struct dma_tx_state *txstate)
1240 {
1241         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1242         struct xilinx_dma_tx_descriptor *desc;
1243         enum dma_status ret;
1244         unsigned long flags;
1245         u32 residue = 0;
1246
1247         ret = dma_cookie_status(dchan, cookie, txstate);
1248         if (ret == DMA_COMPLETE || !txstate)
1249                 return ret;
1250
1251         spin_lock_irqsave(&chan->lock, flags);
1252         if (!list_empty(&chan->active_list)) {
1253                 desc = list_last_entry(&chan->active_list,
1254                                        struct xilinx_dma_tx_descriptor, node);
1255                 /*
1256                  * VDMA and simple mode do not support residue reporting, so the
1257                  * residue field will always be 0.
1258                  */
1259                 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1260                         residue = xilinx_dma_get_residue(chan, desc);
1261         }
1262         spin_unlock_irqrestore(&chan->lock, flags);
1263
1264         dma_set_residue(txstate, residue);
1265
1266         return ret;
1267 }
1268
1269 /**
1270  * xilinx_dma_stop_transfer - Halt DMA channel
1271  * @chan: Driver specific DMA channel
1272  *
1273  * Return: '0' on success and failure value on error
1274  */
1275 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1276 {
1277         u32 val;
1278
1279         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1280
1281         /* Wait for the hardware to halt */
1282         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1283                                        val & XILINX_DMA_DMASR_HALTED, 0,
1284                                        XILINX_DMA_LOOP_COUNT);
1285 }
1286
1287 /**
1288  * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1289  * @chan: Driver specific DMA channel
1290  *
1291  * Return: '0' on success and failure value on error
1292  */
1293 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1294 {
1295         u32 val;
1296
1297         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1298                                        val & XILINX_DMA_DMASR_IDLE, 0,
1299                                        XILINX_DMA_LOOP_COUNT);
1300 }
1301
1302 /**
1303  * xilinx_dma_start - Start DMA channel
1304  * @chan: Driver specific DMA channel
1305  */
1306 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1307 {
1308         int err;
1309         u32 val;
1310
1311         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1312
1313         /* Wait for the hardware to start */
1314         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1315                                       !(val & XILINX_DMA_DMASR_HALTED), 0,
1316                                       XILINX_DMA_LOOP_COUNT);
1317
1318         if (err) {
1319                 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1320                         chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1321
1322                 chan->err = true;
1323         }
1324 }
1325
1326 /**
1327  * xilinx_vdma_start_transfer - Starts VDMA transfer
1328  * @chan: Driver specific channel struct pointer
1329  */
1330 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1331 {
1332         struct xilinx_vdma_config *config = &chan->config;
1333         struct xilinx_dma_tx_descriptor *desc;
1334         u32 reg, j;
1335         struct xilinx_vdma_tx_segment *segment, *last = NULL;
1336         int i = 0;
1337
1338         /* This function was invoked with lock held */
1339         if (chan->err)
1340                 return;
1341
1342         if (!chan->idle)
1343                 return;
1344
1345         if (list_empty(&chan->pending_list))
1346                 return;
1347
1348         desc = list_first_entry(&chan->pending_list,
1349                                 struct xilinx_dma_tx_descriptor, node);
1350
1351         /* Configure the hardware using info in the config structure */
1352         if (chan->has_vflip) {
1353                 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1354                 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1355                 reg |= config->vflip_en;
1356                 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1357                           reg);
1358         }
1359
1360         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1361
1362         if (config->frm_cnt_en)
1363                 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1364         else
1365                 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1366
1367         /* If not parking, enable circular mode */
1368         if (config->park)
1369                 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1370         else
1371                 reg |= XILINX_DMA_DMACR_CIRC_EN;
1372
1373         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1374
1375         j = chan->desc_submitcount;
1376         reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1377         if (chan->direction == DMA_MEM_TO_DEV) {
1378                 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1379                 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1380         } else {
1381                 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1382                 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1383         }
1384         dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1385
1386         /* Start the hardware */
1387         xilinx_dma_start(chan);
1388
1389         if (chan->err)
1390                 return;
1391
1392         /* Start the transfer */
1393         if (chan->desc_submitcount < chan->num_frms)
1394                 i = chan->desc_submitcount;
1395
1396         list_for_each_entry(segment, &desc->segments, node) {
1397                 if (chan->ext_addr)
1398                         vdma_desc_write_64(chan,
1399                                    XILINX_VDMA_REG_START_ADDRESS_64(i++),
1400                                    segment->hw.buf_addr,
1401                                    segment->hw.buf_addr_msb);
1402                 else
1403                         vdma_desc_write(chan,
1404                                         XILINX_VDMA_REG_START_ADDRESS(i++),
1405                                         segment->hw.buf_addr);
1406
1407                 last = segment;
1408         }
1409
1410         if (!last)
1411                 return;
1412
1413         /* HW expects these parameters to be same for one transaction */
1414         vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1415         vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1416                         last->hw.stride);
1417         vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1418
1419         chan->desc_submitcount++;
1420         chan->desc_pendingcount--;
1421         list_move_tail(&desc->node, &chan->active_list);
1422         if (chan->desc_submitcount == chan->num_frms)
1423                 chan->desc_submitcount = 0;
1424
1425         chan->idle = false;
1426 }
1427
1428 /**
1429  * xilinx_cdma_start_transfer - Starts cdma transfer
1430  * @chan: Driver specific channel struct pointer
1431  */
1432 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1433 {
1434         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1435         struct xilinx_cdma_tx_segment *tail_segment;
1436         u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1437
1438         if (chan->err)
1439                 return;
1440
1441         if (!chan->idle)
1442                 return;
1443
1444         if (list_empty(&chan->pending_list))
1445                 return;
1446
1447         head_desc = list_first_entry(&chan->pending_list,
1448                                      struct xilinx_dma_tx_descriptor, node);
1449         tail_desc = list_last_entry(&chan->pending_list,
1450                                     struct xilinx_dma_tx_descriptor, node);
1451         tail_segment = list_last_entry(&tail_desc->segments,
1452                                        struct xilinx_cdma_tx_segment, node);
1453
1454         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1455                 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1456                 ctrl_reg |= chan->desc_pendingcount <<
1457                                 XILINX_DMA_CR_COALESCE_SHIFT;
1458                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1459         }
1460
1461         if (chan->has_sg) {
1462                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1463                              XILINX_CDMA_CR_SGMODE);
1464
1465                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1466                              XILINX_CDMA_CR_SGMODE);
1467
1468                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1469                              head_desc->async_tx.phys);
1470
1471                 /* Update tail ptr register which will start the transfer */
1472                 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1473                              tail_segment->phys);
1474         } else {
1475                 /* In simple mode */
1476                 struct xilinx_cdma_tx_segment *segment;
1477                 struct xilinx_cdma_desc_hw *hw;
1478
1479                 segment = list_first_entry(&head_desc->segments,
1480                                            struct xilinx_cdma_tx_segment,
1481                                            node);
1482
1483                 hw = &segment->hw;
1484
1485                 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1486                              xilinx_prep_dma_addr_t(hw->src_addr));
1487                 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1488                              xilinx_prep_dma_addr_t(hw->dest_addr));
1489
1490                 /* Start the transfer */
1491                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1492                                 hw->control & chan->xdev->max_buffer_len);
1493         }
1494
1495         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1496         chan->desc_pendingcount = 0;
1497         chan->idle = false;
1498 }
1499
1500 /**
1501  * xilinx_dma_start_transfer - Starts DMA transfer
1502  * @chan: Driver specific channel struct pointer
1503  */
1504 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1505 {
1506         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1507         struct xilinx_axidma_tx_segment *tail_segment;
1508         u32 reg;
1509
1510         if (chan->err)
1511                 return;
1512
1513         if (list_empty(&chan->pending_list))
1514                 return;
1515
1516         if (!chan->idle)
1517                 return;
1518
1519         head_desc = list_first_entry(&chan->pending_list,
1520                                      struct xilinx_dma_tx_descriptor, node);
1521         tail_desc = list_last_entry(&chan->pending_list,
1522                                     struct xilinx_dma_tx_descriptor, node);
1523         tail_segment = list_last_entry(&tail_desc->segments,
1524                                        struct xilinx_axidma_tx_segment, node);
1525
1526         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1527
1528         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1529                 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1530                 reg |= chan->desc_pendingcount <<
1531                                   XILINX_DMA_CR_COALESCE_SHIFT;
1532                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1533         }
1534
1535         if (chan->has_sg)
1536                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1537                              head_desc->async_tx.phys);
1538
1539         xilinx_dma_start(chan);
1540
1541         if (chan->err)
1542                 return;
1543
1544         /* Start the transfer */
1545         if (chan->has_sg) {
1546                 if (chan->cyclic)
1547                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1548                                      chan->cyclic_seg_v->phys);
1549                 else
1550                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1551                                      tail_segment->phys);
1552         } else {
1553                 struct xilinx_axidma_tx_segment *segment;
1554                 struct xilinx_axidma_desc_hw *hw;
1555
1556                 segment = list_first_entry(&head_desc->segments,
1557                                            struct xilinx_axidma_tx_segment,
1558                                            node);
1559                 hw = &segment->hw;
1560
1561                 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1562                              xilinx_prep_dma_addr_t(hw->buf_addr));
1563
1564                 /* Start the transfer */
1565                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1566                                hw->control & chan->xdev->max_buffer_len);
1567         }
1568
1569         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1570         chan->desc_pendingcount = 0;
1571         chan->idle = false;
1572 }
1573
1574 /**
1575  * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1576  * @chan: Driver specific channel struct pointer
1577  */
1578 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1579 {
1580         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1581         struct xilinx_aximcdma_tx_segment *tail_segment;
1582         u32 reg;
1583
1584         /*
1585          * lock has been held by calling functions, so we don't need it
1586          * to take it here again.
1587          */
1588
1589         if (chan->err)
1590                 return;
1591
1592         if (!chan->idle)
1593                 return;
1594
1595         if (list_empty(&chan->pending_list))
1596                 return;
1597
1598         head_desc = list_first_entry(&chan->pending_list,
1599                                      struct xilinx_dma_tx_descriptor, node);
1600         tail_desc = list_last_entry(&chan->pending_list,
1601                                     struct xilinx_dma_tx_descriptor, node);
1602         tail_segment = list_last_entry(&tail_desc->segments,
1603                                        struct xilinx_aximcdma_tx_segment, node);
1604
1605         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1606
1607         if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1608                 reg &= ~XILINX_MCDMA_COALESCE_MASK;
1609                 reg |= chan->desc_pendingcount <<
1610                         XILINX_MCDMA_COALESCE_SHIFT;
1611         }
1612
1613         reg |= XILINX_MCDMA_IRQ_ALL_MASK;
1614         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1615
1616         /* Program current descriptor */
1617         xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1618                      head_desc->async_tx.phys);
1619
1620         /* Program channel enable register */
1621         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1622         reg |= BIT(chan->tdest);
1623         dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1624
1625         /* Start the fetch of BDs for the channel */
1626         reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1627         reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
1628         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1629
1630         xilinx_dma_start(chan);
1631
1632         if (chan->err)
1633                 return;
1634
1635         /* Start the transfer */
1636         xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1637                      tail_segment->phys);
1638
1639         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1640         chan->desc_pendingcount = 0;
1641         chan->idle = false;
1642 }
1643
1644 /**
1645  * xilinx_dma_issue_pending - Issue pending transactions
1646  * @dchan: DMA channel
1647  */
1648 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1649 {
1650         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1651         unsigned long flags;
1652
1653         spin_lock_irqsave(&chan->lock, flags);
1654         chan->start_transfer(chan);
1655         spin_unlock_irqrestore(&chan->lock, flags);
1656 }
1657
1658 /**
1659  * xilinx_dma_device_config - Configure the DMA channel
1660  * @dchan: DMA channel
1661  * @config: channel configuration
1662  */
1663 static int xilinx_dma_device_config(struct dma_chan *dchan,
1664                                     struct dma_slave_config *config)
1665 {
1666         return 0;
1667 }
1668
1669 /**
1670  * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1671  * @chan : xilinx DMA channel
1672  *
1673  * CONTEXT: hardirq
1674  */
1675 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1676 {
1677         struct xilinx_dma_tx_descriptor *desc, *next;
1678
1679         /* This function was invoked with lock held */
1680         if (list_empty(&chan->active_list))
1681                 return;
1682
1683         list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1684                 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1685                     XDMA_TYPE_VDMA)
1686                         desc->residue = xilinx_dma_get_residue(chan, desc);
1687                 else
1688                         desc->residue = 0;
1689                 desc->err = chan->err;
1690
1691                 list_del(&desc->node);
1692                 if (!desc->cyclic)
1693                         dma_cookie_complete(&desc->async_tx);
1694                 list_add_tail(&desc->node, &chan->done_list);
1695         }
1696 }
1697
1698 /**
1699  * xilinx_dma_reset - Reset DMA channel
1700  * @chan: Driver specific DMA channel
1701  *
1702  * Return: '0' on success and failure value on error
1703  */
1704 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1705 {
1706         int err;
1707         u32 tmp;
1708
1709         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1710
1711         /* Wait for the hardware to finish reset */
1712         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1713                                       !(tmp & XILINX_DMA_DMACR_RESET), 0,
1714                                       XILINX_DMA_LOOP_COUNT);
1715
1716         if (err) {
1717                 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1718                         dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1719                         dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1720                 return -ETIMEDOUT;
1721         }
1722
1723         chan->err = false;
1724         chan->idle = true;
1725         chan->desc_pendingcount = 0;
1726         chan->desc_submitcount = 0;
1727
1728         return err;
1729 }
1730
1731 /**
1732  * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1733  * @chan: Driver specific DMA channel
1734  *
1735  * Return: '0' on success and failure value on error
1736  */
1737 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1738 {
1739         int err;
1740
1741         /* Reset VDMA */
1742         err = xilinx_dma_reset(chan);
1743         if (err)
1744                 return err;
1745
1746         /* Enable interrupts */
1747         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1748                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1749
1750         return 0;
1751 }
1752
1753 /**
1754  * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1755  * @irq: IRQ number
1756  * @data: Pointer to the Xilinx MCDMA channel structure
1757  *
1758  * Return: IRQ_HANDLED/IRQ_NONE
1759  */
1760 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
1761 {
1762         struct xilinx_dma_chan *chan = data;
1763         u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id;
1764
1765         if (chan->direction == DMA_DEV_TO_MEM)
1766                 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET;
1767         else
1768                 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET;
1769
1770         /* Read the channel id raising the interrupt*/
1771         chan_sermask = dma_ctrl_read(chan, ser_offset);
1772         chan_id = ffs(chan_sermask);
1773
1774         if (!chan_id)
1775                 return IRQ_NONE;
1776
1777         if (chan->direction == DMA_DEV_TO_MEM)
1778                 chan_offset = chan->xdev->dma_config->max_channels / 2;
1779
1780         chan_offset = chan_offset + (chan_id - 1);
1781         chan = chan->xdev->chan[chan_offset];
1782         /* Read the status and ack the interrupts. */
1783         status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1784         if (!(status & XILINX_MCDMA_IRQ_ALL_MASK))
1785                 return IRQ_NONE;
1786
1787         dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1788                        status & XILINX_MCDMA_IRQ_ALL_MASK);
1789
1790         if (status & XILINX_MCDMA_IRQ_ERR_MASK) {
1791                 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1792                         chan,
1793                         dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1794                         dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1795                                       (chan->tdest)),
1796                         dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1797                                       (chan->tdest)));
1798                 chan->err = true;
1799         }
1800
1801         if (status & XILINX_MCDMA_IRQ_DELAY_MASK) {
1802                 /*
1803                  * Device takes too long to do the transfer when user requires
1804                  * responsiveness.
1805                  */
1806                 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1807         }
1808
1809         if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
1810                 spin_lock(&chan->lock);
1811                 xilinx_dma_complete_descriptor(chan);
1812                 chan->idle = true;
1813                 chan->start_transfer(chan);
1814                 spin_unlock(&chan->lock);
1815         }
1816
1817         tasklet_schedule(&chan->tasklet);
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * xilinx_dma_irq_handler - DMA Interrupt handler
1823  * @irq: IRQ number
1824  * @data: Pointer to the Xilinx DMA channel structure
1825  *
1826  * Return: IRQ_HANDLED/IRQ_NONE
1827  */
1828 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1829 {
1830         struct xilinx_dma_chan *chan = data;
1831         u32 status;
1832
1833         /* Read the status and ack the interrupts. */
1834         status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1835         if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1836                 return IRQ_NONE;
1837
1838         dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1839                         status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1840
1841         if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1842                 /*
1843                  * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1844                  * error is recoverable, ignore it. Otherwise flag the error.
1845                  *
1846                  * Only recoverable errors can be cleared in the DMASR register,
1847                  * make sure not to write to other error bits to 1.
1848                  */
1849                 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1850
1851                 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1852                                 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1853
1854                 if (!chan->flush_on_fsync ||
1855                     (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1856                         dev_err(chan->dev,
1857                                 "Channel %p has errors %x, cdr %x tdr %x\n",
1858                                 chan, errors,
1859                                 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1860                                 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1861                         chan->err = true;
1862                 }
1863         }
1864
1865         if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1866                 /*
1867                  * Device takes too long to do the transfer when user requires
1868                  * responsiveness.
1869                  */
1870                 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1871         }
1872
1873         if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1874                 spin_lock(&chan->lock);
1875                 xilinx_dma_complete_descriptor(chan);
1876                 chan->idle = true;
1877                 chan->start_transfer(chan);
1878                 spin_unlock(&chan->lock);
1879         }
1880
1881         tasklet_schedule(&chan->tasklet);
1882         return IRQ_HANDLED;
1883 }
1884
1885 /**
1886  * append_desc_queue - Queuing descriptor
1887  * @chan: Driver specific dma channel
1888  * @desc: dma transaction descriptor
1889  */
1890 static void append_desc_queue(struct xilinx_dma_chan *chan,
1891                               struct xilinx_dma_tx_descriptor *desc)
1892 {
1893         struct xilinx_vdma_tx_segment *tail_segment;
1894         struct xilinx_dma_tx_descriptor *tail_desc;
1895         struct xilinx_axidma_tx_segment *axidma_tail_segment;
1896         struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment;
1897         struct xilinx_cdma_tx_segment *cdma_tail_segment;
1898
1899         if (list_empty(&chan->pending_list))
1900                 goto append;
1901
1902         /*
1903          * Add the hardware descriptor to the chain of hardware descriptors
1904          * that already exists in memory.
1905          */
1906         tail_desc = list_last_entry(&chan->pending_list,
1907                                     struct xilinx_dma_tx_descriptor, node);
1908         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1909                 tail_segment = list_last_entry(&tail_desc->segments,
1910                                                struct xilinx_vdma_tx_segment,
1911                                                node);
1912                 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1913         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1914                 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1915                                                 struct xilinx_cdma_tx_segment,
1916                                                 node);
1917                 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1918         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1919                 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1920                                                struct xilinx_axidma_tx_segment,
1921                                                node);
1922                 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1923         } else {
1924                 aximcdma_tail_segment =
1925                         list_last_entry(&tail_desc->segments,
1926                                         struct xilinx_aximcdma_tx_segment,
1927                                         node);
1928                 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1929         }
1930
1931         /*
1932          * Add the software descriptor and all children to the list
1933          * of pending transactions
1934          */
1935 append:
1936         list_add_tail(&desc->node, &chan->pending_list);
1937         chan->desc_pendingcount++;
1938
1939         if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1940             && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1941                 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1942                 chan->desc_pendingcount = chan->num_frms;
1943         }
1944 }
1945
1946 /**
1947  * xilinx_dma_tx_submit - Submit DMA transaction
1948  * @tx: Async transaction descriptor
1949  *
1950  * Return: cookie value on success and failure value on error
1951  */
1952 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1953 {
1954         struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1955         struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1956         dma_cookie_t cookie;
1957         unsigned long flags;
1958         int err;
1959
1960         if (chan->cyclic) {
1961                 xilinx_dma_free_tx_descriptor(chan, desc);
1962                 return -EBUSY;
1963         }
1964
1965         if (chan->err) {
1966                 /*
1967                  * If reset fails, need to hard reset the system.
1968                  * Channel is no longer functional
1969                  */
1970                 err = xilinx_dma_chan_reset(chan);
1971                 if (err < 0)
1972                         return err;
1973         }
1974
1975         spin_lock_irqsave(&chan->lock, flags);
1976
1977         cookie = dma_cookie_assign(tx);
1978
1979         /* Put this transaction onto the tail of the pending queue */
1980         append_desc_queue(chan, desc);
1981
1982         if (desc->cyclic)
1983                 chan->cyclic = true;
1984
1985         chan->terminating = false;
1986
1987         spin_unlock_irqrestore(&chan->lock, flags);
1988
1989         return cookie;
1990 }
1991
1992 /**
1993  * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1994  *      DMA_SLAVE transaction
1995  * @dchan: DMA channel
1996  * @xt: Interleaved template pointer
1997  * @flags: transfer ack flags
1998  *
1999  * Return: Async transaction descriptor on success and NULL on failure
2000  */
2001 static struct dma_async_tx_descriptor *
2002 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
2003                                  struct dma_interleaved_template *xt,
2004                                  unsigned long flags)
2005 {
2006         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2007         struct xilinx_dma_tx_descriptor *desc;
2008         struct xilinx_vdma_tx_segment *segment;
2009         struct xilinx_vdma_desc_hw *hw;
2010
2011         if (!is_slave_direction(xt->dir))
2012                 return NULL;
2013
2014         if (!xt->numf || !xt->sgl[0].size)
2015                 return NULL;
2016
2017         if (xt->frame_size != 1)
2018                 return NULL;
2019
2020         /* Allocate a transaction descriptor. */
2021         desc = xilinx_dma_alloc_tx_descriptor(chan);
2022         if (!desc)
2023                 return NULL;
2024
2025         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2026         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2027         async_tx_ack(&desc->async_tx);
2028
2029         /* Allocate the link descriptor from DMA pool */
2030         segment = xilinx_vdma_alloc_tx_segment(chan);
2031         if (!segment)
2032                 goto error;
2033
2034         /* Fill in the hardware descriptor */
2035         hw = &segment->hw;
2036         hw->vsize = xt->numf;
2037         hw->hsize = xt->sgl[0].size;
2038         hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
2039                         XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
2040         hw->stride |= chan->config.frm_dly <<
2041                         XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
2042
2043         if (xt->dir != DMA_MEM_TO_DEV) {
2044                 if (chan->ext_addr) {
2045                         hw->buf_addr = lower_32_bits(xt->dst_start);
2046                         hw->buf_addr_msb = upper_32_bits(xt->dst_start);
2047                 } else {
2048                         hw->buf_addr = xt->dst_start;
2049                 }
2050         } else {
2051                 if (chan->ext_addr) {
2052                         hw->buf_addr = lower_32_bits(xt->src_start);
2053                         hw->buf_addr_msb = upper_32_bits(xt->src_start);
2054                 } else {
2055                         hw->buf_addr = xt->src_start;
2056                 }
2057         }
2058
2059         /* Insert the segment into the descriptor segments list. */
2060         list_add_tail(&segment->node, &desc->segments);
2061
2062         /* Link the last hardware descriptor with the first. */
2063         segment = list_first_entry(&desc->segments,
2064                                    struct xilinx_vdma_tx_segment, node);
2065         desc->async_tx.phys = segment->phys;
2066
2067         return &desc->async_tx;
2068
2069 error:
2070         xilinx_dma_free_tx_descriptor(chan, desc);
2071         return NULL;
2072 }
2073
2074 /**
2075  * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2076  * @dchan: DMA channel
2077  * @dma_dst: destination address
2078  * @dma_src: source address
2079  * @len: transfer length
2080  * @flags: transfer ack flags
2081  *
2082  * Return: Async transaction descriptor on success and NULL on failure
2083  */
2084 static struct dma_async_tx_descriptor *
2085 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
2086                         dma_addr_t dma_src, size_t len, unsigned long flags)
2087 {
2088         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2089         struct xilinx_dma_tx_descriptor *desc;
2090         struct xilinx_cdma_tx_segment *segment;
2091         struct xilinx_cdma_desc_hw *hw;
2092
2093         if (!len || len > chan->xdev->max_buffer_len)
2094                 return NULL;
2095
2096         desc = xilinx_dma_alloc_tx_descriptor(chan);
2097         if (!desc)
2098                 return NULL;
2099
2100         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2101         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2102
2103         /* Allocate the link descriptor from DMA pool */
2104         segment = xilinx_cdma_alloc_tx_segment(chan);
2105         if (!segment)
2106                 goto error;
2107
2108         hw = &segment->hw;
2109         hw->control = len;
2110         hw->src_addr = dma_src;
2111         hw->dest_addr = dma_dst;
2112         if (chan->ext_addr) {
2113                 hw->src_addr_msb = upper_32_bits(dma_src);
2114                 hw->dest_addr_msb = upper_32_bits(dma_dst);
2115         }
2116
2117         /* Insert the segment into the descriptor segments list. */
2118         list_add_tail(&segment->node, &desc->segments);
2119
2120         desc->async_tx.phys = segment->phys;
2121         hw->next_desc = segment->phys;
2122
2123         return &desc->async_tx;
2124
2125 error:
2126         xilinx_dma_free_tx_descriptor(chan, desc);
2127         return NULL;
2128 }
2129
2130 /**
2131  * xilinx_cdma_prep_memcpy_sg - prepare descriptors for a memcpy_sg transaction
2132  * @dchan: DMA channel
2133  * @dst_sg: Destination scatter list
2134  * @dst_sg_len: Number of entries in destination scatter list
2135  * @src_sg: Source scatter list
2136  * @src_sg_len: Number of entries in source scatter list
2137  * @flags: transfer ack flags
2138  *
2139  * Return: Async transaction descriptor on success and NULL on failure
2140  */
2141 static struct dma_async_tx_descriptor *xilinx_cdma_prep_memcpy_sg(
2142                         struct dma_chan *dchan, struct scatterlist *dst_sg,
2143                         unsigned int dst_sg_len, struct scatterlist *src_sg,
2144                         unsigned int src_sg_len, unsigned long flags)
2145 {
2146         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2147         struct xilinx_dma_tx_descriptor *desc;
2148         struct xilinx_cdma_tx_segment *segment, *prev = NULL;
2149         struct xilinx_cdma_desc_hw *hw;
2150         size_t len, dst_avail, src_avail;
2151         dma_addr_t dma_dst, dma_src;
2152
2153         if (unlikely(dst_sg_len == 0 || src_sg_len == 0))
2154                 return NULL;
2155
2156         if (unlikely(!dst_sg  || !src_sg))
2157                 return NULL;
2158
2159         desc = xilinx_dma_alloc_tx_descriptor(chan);
2160         if (!desc)
2161                 return NULL;
2162
2163         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2164         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2165
2166         dst_avail = sg_dma_len(dst_sg);
2167         src_avail = sg_dma_len(src_sg);
2168         /*
2169          * loop until there is either no more source or no more destination
2170          * scatterlist entry
2171          */
2172         while (true) {
2173                 len = min_t(size_t, src_avail, dst_avail);
2174                 len = min_t(size_t, len, chan->xdev->max_buffer_len);
2175                 if (len == 0)
2176                         goto fetch;
2177
2178                 /* Allocate the link descriptor from DMA pool */
2179                 segment = xilinx_cdma_alloc_tx_segment(chan);
2180                 if (!segment)
2181                         goto error;
2182
2183                 dma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -
2184                         dst_avail;
2185                 dma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -
2186                         src_avail;
2187                 hw = &segment->hw;
2188                 hw->control = len;
2189                 hw->src_addr = dma_src;
2190                 hw->dest_addr = dma_dst;
2191                 if (chan->ext_addr) {
2192                         hw->src_addr_msb = upper_32_bits(dma_src);
2193                         hw->dest_addr_msb = upper_32_bits(dma_dst);
2194                 }
2195
2196                 if (prev) {
2197                         prev->hw.next_desc = segment->phys;
2198                         if (chan->ext_addr)
2199                                 prev->hw.next_desc_msb =
2200                                         upper_32_bits(segment->phys);
2201                 }
2202
2203                 prev = segment;
2204                 dst_avail -= len;
2205                 src_avail -= len;
2206                 list_add_tail(&segment->node, &desc->segments);
2207
2208 fetch:
2209                 /* Fetch the next dst scatterlist entry */
2210                 if (dst_avail == 0) {
2211                         if (dst_sg_len == 0)
2212                                 break;
2213                         dst_sg = sg_next(dst_sg);
2214                         if (dst_sg == NULL)
2215                                 break;
2216                         dst_sg_len--;
2217                         dst_avail = sg_dma_len(dst_sg);
2218                 }
2219                 /* Fetch the next src scatterlist entry */
2220                 if (src_avail == 0) {
2221                         if (src_sg_len == 0)
2222                                 break;
2223                         src_sg = sg_next(src_sg);
2224                         if (src_sg == NULL)
2225                                 break;
2226                         src_sg_len--;
2227                         src_avail = sg_dma_len(src_sg);
2228                 }
2229         }
2230
2231         if (list_empty(&desc->segments)) {
2232                 dev_err(chan->xdev->dev,
2233                         "%s: Zero-size SG transfer requested\n", __func__);
2234                 goto error;
2235         }
2236
2237         /* Link the last hardware descriptor with the first. */
2238         segment = list_first_entry(&desc->segments,
2239                                 struct xilinx_cdma_tx_segment, node);
2240         desc->async_tx.phys = segment->phys;
2241         prev->hw.next_desc = segment->phys;
2242
2243         return &desc->async_tx;
2244
2245 error:
2246         xilinx_dma_free_tx_descriptor(chan, desc);
2247         return NULL;
2248 }
2249
2250 /**
2251  * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2252  * @dchan: DMA channel
2253  * @sgl: scatterlist to transfer to/from
2254  * @sg_len: number of entries in @scatterlist
2255  * @direction: DMA direction
2256  * @flags: transfer ack flags
2257  * @context: APP words of the descriptor
2258  *
2259  * Return: Async transaction descriptor on success and NULL on failure
2260  */
2261 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
2262         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
2263         enum dma_transfer_direction direction, unsigned long flags,
2264         void *context)
2265 {
2266         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2267         struct xilinx_dma_tx_descriptor *desc;
2268         struct xilinx_axidma_tx_segment *segment = NULL;
2269         u32 *app_w = (u32 *)context;
2270         struct scatterlist *sg;
2271         size_t copy;
2272         size_t sg_used;
2273         unsigned int i;
2274
2275         if (!is_slave_direction(direction))
2276                 return NULL;
2277
2278         /* Allocate a transaction descriptor. */
2279         desc = xilinx_dma_alloc_tx_descriptor(chan);
2280         if (!desc)
2281                 return NULL;
2282
2283         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2284         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2285
2286         /* Build transactions using information in the scatter gather list */
2287         for_each_sg(sgl, sg, sg_len, i) {
2288                 sg_used = 0;
2289
2290                 /* Loop until the entire scatterlist entry is used */
2291                 while (sg_used < sg_dma_len(sg)) {
2292                         struct xilinx_axidma_desc_hw *hw;
2293
2294                         /* Get a free segment */
2295                         segment = xilinx_axidma_alloc_tx_segment(chan);
2296                         if (!segment)
2297                                 goto error;
2298
2299                         /*
2300                          * Calculate the maximum number of bytes to transfer,
2301                          * making sure it is less than the hw limit
2302                          */
2303                         copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2304                                                         sg_used);
2305                         hw = &segment->hw;
2306
2307                         /* Fill in the descriptor */
2308                         xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2309                                           sg_used, 0);
2310
2311                         hw->control = copy;
2312
2313                         if (chan->direction == DMA_MEM_TO_DEV) {
2314                                 if (app_w)
2315                                         memcpy(hw->app, app_w, sizeof(u32) *
2316                                                XILINX_DMA_NUM_APP_WORDS);
2317                         }
2318
2319                         sg_used += copy;
2320
2321                         /*
2322                          * Insert the segment into the descriptor segments
2323                          * list.
2324                          */
2325                         list_add_tail(&segment->node, &desc->segments);
2326                 }
2327         }
2328
2329         segment = list_first_entry(&desc->segments,
2330                                    struct xilinx_axidma_tx_segment, node);
2331         desc->async_tx.phys = segment->phys;
2332
2333         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2334         if (chan->direction == DMA_MEM_TO_DEV) {
2335                 segment->hw.control |= XILINX_DMA_BD_SOP;
2336                 segment = list_last_entry(&desc->segments,
2337                                           struct xilinx_axidma_tx_segment,
2338                                           node);
2339                 segment->hw.control |= XILINX_DMA_BD_EOP;
2340         }
2341
2342         return &desc->async_tx;
2343
2344 error:
2345         xilinx_dma_free_tx_descriptor(chan, desc);
2346         return NULL;
2347 }
2348
2349 /**
2350  * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2351  * @dchan: DMA channel
2352  * @buf_addr: Physical address of the buffer
2353  * @buf_len: Total length of the cyclic buffers
2354  * @period_len: length of individual cyclic buffer
2355  * @direction: DMA direction
2356  * @flags: transfer ack flags
2357  *
2358  * Return: Async transaction descriptor on success and NULL on failure
2359  */
2360 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
2361         struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
2362         size_t period_len, enum dma_transfer_direction direction,
2363         unsigned long flags)
2364 {
2365         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2366         struct xilinx_dma_tx_descriptor *desc;
2367         struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
2368         size_t copy, sg_used;
2369         unsigned int num_periods;
2370         int i;
2371         u32 reg;
2372
2373         if (!period_len)
2374                 return NULL;
2375
2376         num_periods = buf_len / period_len;
2377
2378         if (!num_periods)
2379                 return NULL;
2380
2381         if (!is_slave_direction(direction))
2382                 return NULL;
2383
2384         /* Allocate a transaction descriptor. */
2385         desc = xilinx_dma_alloc_tx_descriptor(chan);
2386         if (!desc)
2387                 return NULL;
2388
2389         chan->direction = direction;
2390         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2391         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2392
2393         for (i = 0; i < num_periods; ++i) {
2394                 sg_used = 0;
2395
2396                 while (sg_used < period_len) {
2397                         struct xilinx_axidma_desc_hw *hw;
2398
2399                         /* Get a free segment */
2400                         segment = xilinx_axidma_alloc_tx_segment(chan);
2401                         if (!segment)
2402                                 goto error;
2403
2404                         /*
2405                          * Calculate the maximum number of bytes to transfer,
2406                          * making sure it is less than the hw limit
2407                          */
2408                         copy = xilinx_dma_calc_copysize(chan, period_len,
2409                                                         sg_used);
2410                         hw = &segment->hw;
2411                         xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2412                                           period_len * i);
2413                         hw->control = copy;
2414
2415                         if (prev)
2416                                 prev->hw.next_desc = segment->phys;
2417
2418                         prev = segment;
2419                         sg_used += copy;
2420
2421                         /*
2422                          * Insert the segment into the descriptor segments
2423                          * list.
2424                          */
2425                         list_add_tail(&segment->node, &desc->segments);
2426                 }
2427         }
2428
2429         head_segment = list_first_entry(&desc->segments,
2430                                    struct xilinx_axidma_tx_segment, node);
2431         desc->async_tx.phys = head_segment->phys;
2432
2433         desc->cyclic = true;
2434         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2435         reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2436         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2437
2438         segment = list_last_entry(&desc->segments,
2439                                   struct xilinx_axidma_tx_segment,
2440                                   node);
2441         segment->hw.next_desc = (u32) head_segment->phys;
2442
2443         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2444         if (direction == DMA_MEM_TO_DEV) {
2445                 head_segment->hw.control |= XILINX_DMA_BD_SOP;
2446                 segment->hw.control |= XILINX_DMA_BD_EOP;
2447         }
2448
2449         return &desc->async_tx;
2450
2451 error:
2452         xilinx_dma_free_tx_descriptor(chan, desc);
2453         return NULL;
2454 }
2455
2456 /**
2457  * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2458  * @dchan: DMA channel
2459  * @sgl: scatterlist to transfer to/from
2460  * @sg_len: number of entries in @scatterlist
2461  * @direction: DMA direction
2462  * @flags: transfer ack flags
2463  * @context: APP words of the descriptor
2464  *
2465  * Return: Async transaction descriptor on success and NULL on failure
2466  */
2467 static struct dma_async_tx_descriptor *
2468 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
2469                            unsigned int sg_len,
2470                            enum dma_transfer_direction direction,
2471                            unsigned long flags, void *context)
2472 {
2473         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2474         struct xilinx_dma_tx_descriptor *desc;
2475         struct xilinx_aximcdma_tx_segment *segment = NULL;
2476         u32 *app_w = (u32 *)context;
2477         struct scatterlist *sg;
2478         size_t copy;
2479         size_t sg_used;
2480         unsigned int i;
2481
2482         if (!is_slave_direction(direction))
2483                 return NULL;
2484
2485         /* Allocate a transaction descriptor. */
2486         desc = xilinx_dma_alloc_tx_descriptor(chan);
2487         if (!desc)
2488                 return NULL;
2489
2490         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2491         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2492
2493         /* Build transactions using information in the scatter gather list */
2494         for_each_sg(sgl, sg, sg_len, i) {
2495                 sg_used = 0;
2496
2497                 /* Loop until the entire scatterlist entry is used */
2498                 while (sg_used < sg_dma_len(sg)) {
2499                         struct xilinx_aximcdma_desc_hw *hw;
2500
2501                         /* Get a free segment */
2502                         segment = xilinx_aximcdma_alloc_tx_segment(chan);
2503                         if (!segment)
2504                                 goto error;
2505
2506                         /*
2507                          * Calculate the maximum number of bytes to transfer,
2508                          * making sure it is less than the hw limit
2509                          */
2510                         copy = min_t(size_t, sg_dma_len(sg) - sg_used,
2511                                      chan->xdev->max_buffer_len);
2512                         hw = &segment->hw;
2513
2514                         /* Fill in the descriptor */
2515                         xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2516                                             sg_used);
2517                         hw->control = copy;
2518
2519                         if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2520                                 memcpy(hw->app, app_w, sizeof(u32) *
2521                                        XILINX_DMA_NUM_APP_WORDS);
2522                         }
2523
2524                         sg_used += copy;
2525                         /*
2526                          * Insert the segment into the descriptor segments
2527                          * list.
2528                          */
2529                         list_add_tail(&segment->node, &desc->segments);
2530                 }
2531         }
2532
2533         segment = list_first_entry(&desc->segments,
2534                                    struct xilinx_aximcdma_tx_segment, node);
2535         desc->async_tx.phys = segment->phys;
2536
2537         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2538         if (chan->direction == DMA_MEM_TO_DEV) {
2539                 segment->hw.control |= XILINX_MCDMA_BD_SOP;
2540                 segment = list_last_entry(&desc->segments,
2541                                           struct xilinx_aximcdma_tx_segment,
2542                                           node);
2543                 segment->hw.control |= XILINX_MCDMA_BD_EOP;
2544         }
2545
2546         return &desc->async_tx;
2547
2548 error:
2549         xilinx_dma_free_tx_descriptor(chan, desc);
2550
2551         return NULL;
2552 }
2553
2554 /**
2555  * xilinx_dma_terminate_all - Halt the channel and free descriptors
2556  * @dchan: Driver specific DMA Channel pointer
2557  *
2558  * Return: '0' always.
2559  */
2560 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2561 {
2562         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2563         u32 reg;
2564         int err;
2565
2566         if (!chan->cyclic) {
2567                 err = chan->stop_transfer(chan);
2568                 if (err) {
2569                         dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2570                                 chan, dma_ctrl_read(chan,
2571                                 XILINX_DMA_REG_DMASR));
2572                         chan->err = true;
2573                 }
2574         }
2575
2576         xilinx_dma_chan_reset(chan);
2577         /* Remove and free all of the descriptors in the lists */
2578         chan->terminating = true;
2579         xilinx_dma_free_descriptors(chan);
2580         chan->idle = true;
2581
2582         if (chan->cyclic) {
2583                 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2584                 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2585                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2586                 chan->cyclic = false;
2587         }
2588
2589         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2590                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2591                              XILINX_CDMA_CR_SGMODE);
2592
2593         return 0;
2594 }
2595
2596 static void xilinx_dma_synchronize(struct dma_chan *dchan)
2597 {
2598         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2599
2600         tasklet_kill(&chan->tasklet);
2601 }
2602
2603 /**
2604  * xilinx_vdma_channel_set_config - Configure VDMA channel
2605  * Run-time configuration for Axi VDMA, supports:
2606  * . halt the channel
2607  * . configure interrupt coalescing and inter-packet delay threshold
2608  * . start/stop parking
2609  * . enable genlock
2610  *
2611  * @dchan: DMA channel
2612  * @cfg: VDMA device configuration pointer
2613  *
2614  * Return: '0' on success and failure value on error
2615  */
2616 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2617                                         struct xilinx_vdma_config *cfg)
2618 {
2619         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2620         u32 dmacr;
2621
2622         if (cfg->reset)
2623                 return xilinx_dma_chan_reset(chan);
2624
2625         dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2626
2627         chan->config.frm_dly = cfg->frm_dly;
2628         chan->config.park = cfg->park;
2629
2630         /* genlock settings */
2631         chan->config.gen_lock = cfg->gen_lock;
2632         chan->config.master = cfg->master;
2633
2634         dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2635         if (cfg->gen_lock && chan->genlock) {
2636                 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2637                 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2638                 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2639         }
2640
2641         chan->config.frm_cnt_en = cfg->frm_cnt_en;
2642         chan->config.vflip_en = cfg->vflip_en;
2643
2644         if (cfg->park)
2645                 chan->config.park_frm = cfg->park_frm;
2646         else
2647                 chan->config.park_frm = -1;
2648
2649         chan->config.coalesc = cfg->coalesc;
2650         chan->config.delay = cfg->delay;
2651
2652         if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2653                 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2654                 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2655                 chan->config.coalesc = cfg->coalesc;
2656         }
2657
2658         if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2659                 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2660                 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2661                 chan->config.delay = cfg->delay;
2662         }
2663
2664         /* FSync Source selection */
2665         dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2666         dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2667
2668         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2669
2670         return 0;
2671 }
2672 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2673
2674 /* -----------------------------------------------------------------------------
2675  * Probe and remove
2676  */
2677
2678 /**
2679  * xilinx_dma_chan_remove - Per Channel remove function
2680  * @chan: Driver specific DMA channel
2681  */
2682 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2683 {
2684         /* Disable all interrupts */
2685         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2686                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2687
2688         if (chan->irq > 0)
2689                 free_irq(chan->irq, chan);
2690
2691         tasklet_kill(&chan->tasklet);
2692
2693         list_del(&chan->common.device_node);
2694 }
2695
2696 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2697                             struct clk **tx_clk, struct clk **rx_clk,
2698                             struct clk **sg_clk, struct clk **tmp_clk)
2699 {
2700         int err;
2701
2702         *tmp_clk = NULL;
2703
2704         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2705         if (IS_ERR(*axi_clk))
2706                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2707
2708         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2709         if (IS_ERR(*tx_clk))
2710                 *tx_clk = NULL;
2711
2712         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2713         if (IS_ERR(*rx_clk))
2714                 *rx_clk = NULL;
2715
2716         *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2717         if (IS_ERR(*sg_clk))
2718                 *sg_clk = NULL;
2719
2720         err = clk_prepare_enable(*axi_clk);
2721         if (err) {
2722                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2723                 return err;
2724         }
2725
2726         err = clk_prepare_enable(*tx_clk);
2727         if (err) {
2728                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2729                 goto err_disable_axiclk;
2730         }
2731
2732         err = clk_prepare_enable(*rx_clk);
2733         if (err) {
2734                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2735                 goto err_disable_txclk;
2736         }
2737
2738         err = clk_prepare_enable(*sg_clk);
2739         if (err) {
2740                 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2741                 goto err_disable_rxclk;
2742         }
2743
2744         return 0;
2745
2746 err_disable_rxclk:
2747         clk_disable_unprepare(*rx_clk);
2748 err_disable_txclk:
2749         clk_disable_unprepare(*tx_clk);
2750 err_disable_axiclk:
2751         clk_disable_unprepare(*axi_clk);
2752
2753         return err;
2754 }
2755
2756 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2757                             struct clk **dev_clk, struct clk **tmp_clk,
2758                             struct clk **tmp1_clk, struct clk **tmp2_clk)
2759 {
2760         int err;
2761
2762         *tmp_clk = NULL;
2763         *tmp1_clk = NULL;
2764         *tmp2_clk = NULL;
2765
2766         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2767         if (IS_ERR(*axi_clk))
2768                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2769
2770         *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2771         if (IS_ERR(*dev_clk))
2772                 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n");
2773
2774         err = clk_prepare_enable(*axi_clk);
2775         if (err) {
2776                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2777                 return err;
2778         }
2779
2780         err = clk_prepare_enable(*dev_clk);
2781         if (err) {
2782                 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2783                 goto err_disable_axiclk;
2784         }
2785
2786         return 0;
2787
2788 err_disable_axiclk:
2789         clk_disable_unprepare(*axi_clk);
2790
2791         return err;
2792 }
2793
2794 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2795                             struct clk **tx_clk, struct clk **txs_clk,
2796                             struct clk **rx_clk, struct clk **rxs_clk)
2797 {
2798         int err;
2799
2800         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2801         if (IS_ERR(*axi_clk))
2802                 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2803
2804         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2805         if (IS_ERR(*tx_clk))
2806                 *tx_clk = NULL;
2807
2808         *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2809         if (IS_ERR(*txs_clk))
2810                 *txs_clk = NULL;
2811
2812         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2813         if (IS_ERR(*rx_clk))
2814                 *rx_clk = NULL;
2815
2816         *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2817         if (IS_ERR(*rxs_clk))
2818                 *rxs_clk = NULL;
2819
2820         err = clk_prepare_enable(*axi_clk);
2821         if (err) {
2822                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n",
2823                         err);
2824                 return err;
2825         }
2826
2827         err = clk_prepare_enable(*tx_clk);
2828         if (err) {
2829                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2830                 goto err_disable_axiclk;
2831         }
2832
2833         err = clk_prepare_enable(*txs_clk);
2834         if (err) {
2835                 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2836                 goto err_disable_txclk;
2837         }
2838
2839         err = clk_prepare_enable(*rx_clk);
2840         if (err) {
2841                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2842                 goto err_disable_txsclk;
2843         }
2844
2845         err = clk_prepare_enable(*rxs_clk);
2846         if (err) {
2847                 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2848                 goto err_disable_rxclk;
2849         }
2850
2851         return 0;
2852
2853 err_disable_rxclk:
2854         clk_disable_unprepare(*rx_clk);
2855 err_disable_txsclk:
2856         clk_disable_unprepare(*txs_clk);
2857 err_disable_txclk:
2858         clk_disable_unprepare(*tx_clk);
2859 err_disable_axiclk:
2860         clk_disable_unprepare(*axi_clk);
2861
2862         return err;
2863 }
2864
2865 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2866 {
2867         clk_disable_unprepare(xdev->rxs_clk);
2868         clk_disable_unprepare(xdev->rx_clk);
2869         clk_disable_unprepare(xdev->txs_clk);
2870         clk_disable_unprepare(xdev->tx_clk);
2871         clk_disable_unprepare(xdev->axi_clk);
2872 }
2873
2874 /**
2875  * xilinx_dma_chan_probe - Per Channel Probing
2876  * It get channel features from the device tree entry and
2877  * initialize special channel handling routines
2878  *
2879  * @xdev: Driver specific device structure
2880  * @node: Device node
2881  *
2882  * Return: '0' on success and failure value on error
2883  */
2884 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2885                                   struct device_node *node)
2886 {
2887         struct xilinx_dma_chan *chan;
2888         bool has_dre = false;
2889         u32 value, width;
2890         int err;
2891
2892         /* Allocate and initialize the channel structure */
2893         chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2894         if (!chan)
2895                 return -ENOMEM;
2896
2897         chan->dev = xdev->dev;
2898         chan->xdev = xdev;
2899         chan->desc_pendingcount = 0x0;
2900         chan->ext_addr = xdev->ext_addr;
2901         /* This variable ensures that descriptors are not
2902          * Submitted when dma engine is in progress. This variable is
2903          * Added to avoid polling for a bit in the status register to
2904          * Know dma state in the driver hot path.
2905          */
2906         chan->idle = true;
2907
2908         spin_lock_init(&chan->lock);
2909         INIT_LIST_HEAD(&chan->pending_list);
2910         INIT_LIST_HEAD(&chan->done_list);
2911         INIT_LIST_HEAD(&chan->active_list);
2912         INIT_LIST_HEAD(&chan->free_seg_list);
2913
2914         /* Retrieve the channel properties from the device tree */
2915         has_dre = of_property_read_bool(node, "xlnx,include-dre");
2916
2917         chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2918
2919         err = of_property_read_u32(node, "xlnx,datawidth", &value);
2920         if (err) {
2921                 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2922                 return err;
2923         }
2924         width = value >> 3; /* Convert bits to bytes */
2925
2926         /* If data width is greater than 8 bytes, DRE is not in hw */
2927         if (width > 8)
2928                 has_dre = false;
2929
2930         if (!has_dre)
2931                 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2932
2933         if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2934             of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2935             of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2936                 chan->direction = DMA_MEM_TO_DEV;
2937                 chan->id = xdev->mm2s_chan_id++;
2938                 chan->tdest = chan->id;
2939
2940                 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2941                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2942                         chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2943                         chan->config.park = 1;
2944
2945                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2946                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2947                                 chan->flush_on_fsync = true;
2948                 }
2949         } else if (of_device_is_compatible(node,
2950                                            "xlnx,axi-vdma-s2mm-channel") ||
2951                    of_device_is_compatible(node,
2952                                            "xlnx,axi-dma-s2mm-channel")) {
2953                 chan->direction = DMA_DEV_TO_MEM;
2954                 chan->id = xdev->s2mm_chan_id++;
2955                 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2956                 chan->has_vflip = of_property_read_bool(node,
2957                                         "xlnx,enable-vert-flip");
2958                 if (chan->has_vflip) {
2959                         chan->config.vflip_en = dma_read(chan,
2960                                 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2961                                 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2962                 }
2963
2964                 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
2965                         chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2966                 else
2967                         chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2968
2969                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2970                         chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2971                         chan->config.park = 1;
2972
2973                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2974                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2975                                 chan->flush_on_fsync = true;
2976                 }
2977         } else {
2978                 dev_err(xdev->dev, "Invalid channel compatible node\n");
2979                 return -EINVAL;
2980         }
2981
2982         /* Request the interrupt */
2983         chan->irq = of_irq_get(node, chan->tdest);
2984         if (chan->irq < 0)
2985                 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n");
2986         err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2987                           IRQF_SHARED, "xilinx-dma-controller", chan);
2988         if (err) {
2989                 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2990                 return err;
2991         }
2992
2993         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2994                 chan->start_transfer = xilinx_dma_start_transfer;
2995                 chan->stop_transfer = xilinx_dma_stop_transfer;
2996         } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
2997                 chan->start_transfer = xilinx_mcdma_start_transfer;
2998                 chan->stop_transfer = xilinx_dma_stop_transfer;
2999         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3000                 chan->start_transfer = xilinx_cdma_start_transfer;
3001                 chan->stop_transfer = xilinx_cdma_stop_transfer;
3002         } else {
3003                 chan->start_transfer = xilinx_vdma_start_transfer;
3004                 chan->stop_transfer = xilinx_dma_stop_transfer;
3005         }
3006
3007         /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */
3008         if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
3009                 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA ||
3010                     dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
3011                             XILINX_DMA_DMASR_SG_MASK)
3012                         chan->has_sg = true;
3013                 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
3014                         chan->has_sg ? "enabled" : "disabled");
3015         }
3016
3017         /* Initialize the tasklet */
3018         tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
3019
3020         /*
3021          * Initialize the DMA channel and add it to the DMA engine channels
3022          * list.
3023          */
3024         chan->common.device = &xdev->common;
3025
3026         list_add_tail(&chan->common.device_node, &xdev->common.channels);
3027         xdev->chan[chan->id] = chan;
3028
3029         /* Reset the channel */
3030         err = xilinx_dma_chan_reset(chan);
3031         if (err < 0) {
3032                 dev_err(xdev->dev, "Reset channel failed\n");
3033                 return err;
3034         }
3035
3036         return 0;
3037 }
3038
3039 /**
3040  * xilinx_dma_child_probe - Per child node probe
3041  * It get number of dma-channels per child node from
3042  * device-tree and initializes all the channels.
3043  *
3044  * @xdev: Driver specific device structure
3045  * @node: Device node
3046  *
3047  * Return: 0 always.
3048  */
3049 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
3050                                     struct device_node *node)
3051 {
3052         int ret, i;
3053         u32 nr_channels = 1;
3054
3055         ret = of_property_read_u32(node, "dma-channels", &nr_channels);
3056         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
3057                 dev_warn(xdev->dev, "missing dma-channels property\n");
3058
3059         for (i = 0; i < nr_channels; i++) {
3060                 ret = xilinx_dma_chan_probe(xdev, node);
3061                 if (ret)
3062                         return ret;
3063         }
3064
3065         return 0;
3066 }
3067
3068 /**
3069  * of_dma_xilinx_xlate - Translation function
3070  * @dma_spec: Pointer to DMA specifier as found in the device tree
3071  * @ofdma: Pointer to DMA controller data
3072  *
3073  * Return: DMA channel pointer on success and NULL on error
3074  */
3075 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
3076                                                 struct of_dma *ofdma)
3077 {
3078         struct xilinx_dma_device *xdev = ofdma->of_dma_data;
3079         int chan_id = dma_spec->args[0];
3080
3081         if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
3082                 return NULL;
3083
3084         return dma_get_slave_channel(&xdev->chan[chan_id]->common);
3085 }
3086
3087 static const struct xilinx_dma_config axidma_config = {
3088         .dmatype = XDMA_TYPE_AXIDMA,
3089         .clk_init = axidma_clk_init,
3090         .irq_handler = xilinx_dma_irq_handler,
3091         .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
3092 };
3093
3094 static const struct xilinx_dma_config aximcdma_config = {
3095         .dmatype = XDMA_TYPE_AXIMCDMA,
3096         .clk_init = axidma_clk_init,
3097         .irq_handler = xilinx_mcdma_irq_handler,
3098         .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE,
3099 };
3100 static const struct xilinx_dma_config axicdma_config = {
3101         .dmatype = XDMA_TYPE_CDMA,
3102         .clk_init = axicdma_clk_init,
3103         .irq_handler = xilinx_dma_irq_handler,
3104         .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE,
3105 };
3106
3107 static const struct xilinx_dma_config axivdma_config = {
3108         .dmatype = XDMA_TYPE_VDMA,
3109         .clk_init = axivdma_clk_init,
3110         .irq_handler = xilinx_dma_irq_handler,
3111         .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
3112 };
3113
3114 static const struct of_device_id xilinx_dma_of_ids[] = {
3115         { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
3116         { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
3117         { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
3118         { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
3119         {}
3120 };
3121 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
3122
3123 /**
3124  * xilinx_dma_probe - Driver probe function
3125  * @pdev: Pointer to the platform_device structure
3126  *
3127  * Return: '0' on success and failure value on error
3128  */
3129 static int xilinx_dma_probe(struct platform_device *pdev)
3130 {
3131         int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
3132                         struct clk **, struct clk **, struct clk **)
3133                                         = axivdma_clk_init;
3134         struct device_node *node = pdev->dev.of_node;
3135         struct xilinx_dma_device *xdev;
3136         struct device_node *child, *np = pdev->dev.of_node;
3137         u32 num_frames, addr_width, len_width;
3138         int i, err;
3139
3140         /* Allocate and initialize the DMA engine structure */
3141         xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
3142         if (!xdev)
3143                 return -ENOMEM;
3144
3145         xdev->dev = &pdev->dev;
3146         if (np) {
3147                 const struct of_device_id *match;
3148
3149                 match = of_match_node(xilinx_dma_of_ids, np);
3150                 if (match && match->data) {
3151                         xdev->dma_config = match->data;
3152                         clk_init = xdev->dma_config->clk_init;
3153                 }
3154         }
3155
3156         err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
3157                        &xdev->rx_clk, &xdev->rxs_clk);
3158         if (err)
3159                 return err;
3160
3161         /* Request and map I/O memory */
3162         xdev->regs = devm_platform_ioremap_resource(pdev, 0);
3163         if (IS_ERR(xdev->regs))
3164                 return PTR_ERR(xdev->regs);
3165
3166         /* Retrieve the DMA engine properties from the device tree */
3167         xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
3168         xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
3169
3170         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
3171             xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3172                 if (!of_property_read_u32(node, "xlnx,sg-length-width",
3173                                           &len_width)) {
3174                         if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
3175                             len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
3176                                 dev_warn(xdev->dev,
3177                                          "invalid xlnx,sg-length-width property value. Using default width\n");
3178                         } else {
3179                                 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
3180                                         dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
3181                                 xdev->max_buffer_len =
3182                                         GENMASK(len_width - 1, 0);
3183                         }
3184                 }
3185         }
3186
3187         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3188                 err = of_property_read_u32(node, "xlnx,num-fstores",
3189                                            &num_frames);
3190                 if (err < 0) {
3191                         dev_err(xdev->dev,
3192                                 "missing xlnx,num-fstores property\n");
3193                         return err;
3194                 }
3195
3196                 err = of_property_read_u32(node, "xlnx,flush-fsync",
3197                                            &xdev->flush_on_fsync);
3198                 if (err < 0)
3199                         dev_warn(xdev->dev,
3200                                  "missing xlnx,flush-fsync property\n");
3201         }
3202
3203         err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
3204         if (err < 0)
3205                 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
3206
3207         if (addr_width > 32)
3208                 xdev->ext_addr = true;
3209         else
3210                 xdev->ext_addr = false;
3211
3212         /* Set the dma mask bits */
3213         dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
3214
3215         /* Initialize the DMA engine */
3216         xdev->common.dev = &pdev->dev;
3217
3218         INIT_LIST_HEAD(&xdev->common.channels);
3219         if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
3220                 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
3221                 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
3222         }
3223
3224         xdev->common.device_alloc_chan_resources =
3225                                 xilinx_dma_alloc_chan_resources;
3226         xdev->common.device_free_chan_resources =
3227                                 xilinx_dma_free_chan_resources;
3228         xdev->common.device_terminate_all = xilinx_dma_terminate_all;
3229         xdev->common.device_synchronize = xilinx_dma_synchronize;
3230         xdev->common.device_tx_status = xilinx_dma_tx_status;
3231         xdev->common.device_issue_pending = xilinx_dma_issue_pending;
3232         xdev->common.device_config = xilinx_dma_device_config;
3233         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3234                 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
3235                 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
3236                 xdev->common.device_prep_dma_cyclic =
3237                                           xilinx_dma_prep_dma_cyclic;
3238                 /* Residue calculation is supported by only AXI DMA and CDMA */
3239                 xdev->common.residue_granularity =
3240                                           DMA_RESIDUE_GRANULARITY_SEGMENT;
3241         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3242                 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
3243                 dma_cap_set(DMA_MEMCPY_SG, xdev->common.cap_mask);
3244                 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
3245                 xdev->common.device_prep_dma_memcpy_sg = xilinx_cdma_prep_memcpy_sg;
3246                 /* Residue calculation is supported by only AXI DMA and CDMA */
3247                 xdev->common.residue_granularity =
3248                                           DMA_RESIDUE_GRANULARITY_SEGMENT;
3249         } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3250                 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg;
3251         } else {
3252                 xdev->common.device_prep_interleaved_dma =
3253                                 xilinx_vdma_dma_prep_interleaved;
3254         }
3255
3256         platform_set_drvdata(pdev, xdev);
3257
3258         /* Initialize the channels */
3259         for_each_child_of_node(node, child) {
3260                 err = xilinx_dma_child_probe(xdev, child);
3261                 if (err < 0)
3262                         goto disable_clks;
3263         }
3264
3265         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3266                 for (i = 0; i < xdev->dma_config->max_channels; i++)
3267                         if (xdev->chan[i])
3268                                 xdev->chan[i]->num_frms = num_frames;
3269         }
3270
3271         /* Register the DMA engine with the core */
3272         err = dma_async_device_register(&xdev->common);
3273         if (err) {
3274                 dev_err(xdev->dev, "failed to register the dma device\n");
3275                 goto error;
3276         }
3277
3278         err = of_dma_controller_register(node, of_dma_xilinx_xlate,
3279                                          xdev);
3280         if (err < 0) {
3281                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
3282                 dma_async_device_unregister(&xdev->common);
3283                 goto error;
3284         }
3285
3286         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
3287                 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
3288         else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
3289                 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
3290         else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
3291                 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n");
3292         else
3293                 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
3294
3295         return 0;
3296
3297 disable_clks:
3298         xdma_disable_allclks(xdev);
3299 error:
3300         for (i = 0; i < xdev->dma_config->max_channels; i++)
3301                 if (xdev->chan[i])
3302                         xilinx_dma_chan_remove(xdev->chan[i]);
3303
3304         return err;
3305 }
3306
3307 /**
3308  * xilinx_dma_remove - Driver remove function
3309  * @pdev: Pointer to the platform_device structure
3310  *
3311  * Return: Always '0'
3312  */
3313 static int xilinx_dma_remove(struct platform_device *pdev)
3314 {
3315         struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
3316         int i;
3317
3318         of_dma_controller_free(pdev->dev.of_node);
3319
3320         dma_async_device_unregister(&xdev->common);
3321
3322         for (i = 0; i < xdev->dma_config->max_channels; i++)
3323                 if (xdev->chan[i])
3324                         xilinx_dma_chan_remove(xdev->chan[i]);
3325
3326         xdma_disable_allclks(xdev);
3327
3328         return 0;
3329 }
3330
3331 static struct platform_driver xilinx_vdma_driver = {
3332         .driver = {
3333                 .name = "xilinx-vdma",
3334                 .of_match_table = xilinx_dma_of_ids,
3335         },
3336         .probe = xilinx_dma_probe,
3337         .remove = xilinx_dma_remove,
3338 };
3339
3340 module_platform_driver(xilinx_vdma_driver);
3341
3342 MODULE_AUTHOR("Xilinx, Inc.");
3343 MODULE_DESCRIPTION("Xilinx VDMA driver");
3344 MODULE_LICENSE("GPL v2");