drivers/dma/xilinx/xilinx_dma.c

   1 /*
   2  * DMA driver for Xilinx Video DMA Engine
   3  *
   4  * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
   5  *
   6  * Based on the Freescale DMA driver.
   7  *
   8  * Description:
   9  * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
  10  * core that provides high-bandwidth direct memory access between memory
  11  * and AXI4-Stream type video target peripherals. The core provides efficient
  12  * two dimensional DMA operations with independent asynchronous read (S2MM)
  13  * and write (MM2S) channel operation. It can be configured to have either
  14  * one channel or two channels. If configured as two channels, one is to
  15  * transmit to the video device (MM2S) and another is to receive from the
  16  * video device (S2MM). Initialization, status, interrupt and management
  17  * registers are accessed through an AXI4-Lite slave interface.
  18  *
  19  * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
  20  * provides high-bandwidth one dimensional direct memory access between memory
  21  * and AXI4-Stream target peripherals. It supports one receive and one
  22  * transmit channel, both of them optional at synthesis time.
  23  *
  24  * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
  25  * Access (DMA) between a memory-mapped source address and a memory-mapped
  26  * destination address.
  27  *
  28  * This program is free software: you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License as published by
  30  * the Free Software Foundation, either version 2 of the License, or
  31  * (at your option) any later version.
  32  */
  33
  34 #include <linux/bitops.h>
  35 #include <linux/dmapool.h>
  36 #include <linux/dma/xilinx_dma.h>
  37 #include <linux/init.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/io.h>
  40 #include <linux/iopoll.h>
  41 #include <linux/module.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_dma.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/of_irq.h>
  46 #include <linux/slab.h>
  47 #include <linux/clk.h>
  48 #include <linux/io-64-nonatomic-lo-hi.h>
  49
  50 #include "../dmaengine.h"
  51
  52 /* Register/Descriptor Offsets */
  53 #define XILINX_DMA_MM2S_CTRL_OFFSET             0x0000
  54 #define XILINX_DMA_S2MM_CTRL_OFFSET             0x0030
  55 #define XILINX_VDMA_MM2S_DESC_OFFSET            0x0050
  56 #define XILINX_VDMA_S2MM_DESC_OFFSET            0x00a0
  57
  58 /* Control Registers */
  59 #define XILINX_DMA_REG_DMACR                    0x0000
  60 #define XILINX_DMA_DMACR_DELAY_MAX              0xff
  61 #define XILINX_DMA_DMACR_DELAY_SHIFT            24
  62 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX        0xff
  63 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT      16
  64 #define XILINX_DMA_DMACR_ERR_IRQ                BIT(14)
  65 #define XILINX_DMA_DMACR_DLY_CNT_IRQ            BIT(13)
  66 #define XILINX_DMA_DMACR_FRM_CNT_IRQ            BIT(12)
  67 #define XILINX_DMA_DMACR_MASTER_SHIFT           8
  68 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
  69 #define XILINX_DMA_DMACR_FRAMECNT_EN            BIT(4)
  70 #define XILINX_DMA_DMACR_GENLOCK_EN             BIT(3)
  71 #define XILINX_DMA_DMACR_RESET                  BIT(2)
  72 #define XILINX_DMA_DMACR_CIRC_EN                BIT(1)
  73 #define XILINX_DMA_DMACR_RUNSTOP                BIT(0)
  74 #define XILINX_DMA_DMACR_FSYNCSRC_MASK          GENMASK(6, 5)
  75 #define XILINX_DMA_DMACR_DELAY_MASK             GENMASK(31, 24)
  76 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK       GENMASK(23, 16)
  77 #define XILINX_DMA_DMACR_MASTER_MASK            GENMASK(11, 8)
  78
  79 #define XILINX_DMA_REG_DMASR                    0x0004
  80 #define XILINX_DMA_DMASR_EOL_LATE_ERR           BIT(15)
  81 #define XILINX_DMA_DMASR_ERR_IRQ                BIT(14)
  82 #define XILINX_DMA_DMASR_DLY_CNT_IRQ            BIT(13)
  83 #define XILINX_DMA_DMASR_FRM_CNT_IRQ            BIT(12)
  84 #define XILINX_DMA_DMASR_SOF_LATE_ERR           BIT(11)
  85 #define XILINX_DMA_DMASR_SG_DEC_ERR             BIT(10)
  86 #define XILINX_DMA_DMASR_SG_SLV_ERR             BIT(9)
  87 #define XILINX_DMA_DMASR_EOF_EARLY_ERR          BIT(8)
  88 #define XILINX_DMA_DMASR_SOF_EARLY_ERR          BIT(7)
  89 #define XILINX_DMA_DMASR_DMA_DEC_ERR            BIT(6)
  90 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR          BIT(5)
  91 #define XILINX_DMA_DMASR_DMA_INT_ERR            BIT(4)
  92 #define XILINX_DMA_DMASR_IDLE                   BIT(1)
  93 #define XILINX_DMA_DMASR_HALTED         BIT(0)
  94 #define XILINX_DMA_DMASR_DELAY_MASK             GENMASK(31, 24)
  95 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK       GENMASK(23, 16)
  96
  97 #define XILINX_DMA_REG_CURDESC                  0x0008
  98 #define XILINX_DMA_REG_TAILDESC         0x0010
  99 #define XILINX_DMA_REG_REG_INDEX                0x0014
 100 #define XILINX_DMA_REG_FRMSTORE         0x0018
 101 #define XILINX_DMA_REG_THRESHOLD                0x001c
 102 #define XILINX_DMA_REG_FRMPTR_STS               0x0024
 103 #define XILINX_DMA_REG_PARK_PTR         0x0028
 104 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT        8
 105 #define XILINX_DMA_PARK_PTR_WR_REF_MASK         GENMASK(12, 8)
 106 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT        0
 107 #define XILINX_DMA_PARK_PTR_RD_REF_MASK         GENMASK(4, 0)
 108 #define XILINX_DMA_REG_VDMA_VERSION             0x002c
 109
 110 /* Register Direct Mode Registers */
 111 #define XILINX_DMA_REG_VSIZE                    0x0000
 112 #define XILINX_DMA_REG_HSIZE                    0x0004
 113
 114 #define XILINX_DMA_REG_FRMDLY_STRIDE            0x0008
 115 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT   24
 116 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT   0
 117
 118 #define XILINX_VDMA_REG_START_ADDRESS(n)        (0x000c + 4 * (n))
 119 #define XILINX_VDMA_REG_START_ADDRESS_64(n)     (0x000c + 8 * (n))
 120
 121 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP    0x00ec
 122 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP        BIT(0)
 123
 124 /* HW specific definitions */
 125 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
 126
 127 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK   \
 128                 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
 129                  XILINX_DMA_DMASR_DLY_CNT_IRQ | \
 130                  XILINX_DMA_DMASR_ERR_IRQ)
 131
 132 #define XILINX_DMA_DMASR_ALL_ERR_MASK   \
 133                 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
 134                  XILINX_DMA_DMASR_SOF_LATE_ERR | \
 135                  XILINX_DMA_DMASR_SG_DEC_ERR | \
 136                  XILINX_DMA_DMASR_SG_SLV_ERR | \
 137                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 138                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 139                  XILINX_DMA_DMASR_DMA_DEC_ERR | \
 140                  XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
 141                  XILINX_DMA_DMASR_DMA_INT_ERR)
 142
 143 /*
 144  * Recoverable errors are DMA Internal error, SOF Early, EOF Early
 145  * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
 146  * is enabled in the h/w system.
 147  */
 148 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK       \
 149                 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
 150                  XILINX_DMA_DMASR_EOF_EARLY_ERR | \
 151                  XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 152                  XILINX_DMA_DMASR_DMA_INT_ERR)
 153
 154 /* Axi VDMA Flush on Fsync bits */
 155 #define XILINX_DMA_FLUSH_S2MM           3
 156 #define XILINX_DMA_FLUSH_MM2S           2
 157 #define XILINX_DMA_FLUSH_BOTH           1
 158
 159 /* Delay loop counter to prevent hardware failure */
 160 #define XILINX_DMA_LOOP_COUNT           1000000
 161
 162 /* AXI DMA Specific Registers/Offsets */
 163 #define XILINX_DMA_REG_SRCDSTADDR       0x18
 164 #define XILINX_DMA_REG_BTT              0x28
 165
 166 /* AXI DMA Specific Masks/Bit fields */
 167 #define XILINX_DMA_MAX_TRANS_LEN_MIN    8
 168 #define XILINX_DMA_MAX_TRANS_LEN_MAX    23
 169 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
 170 #define XILINX_DMA_CR_COALESCE_MAX      GENMASK(23, 16)
 171 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
 172 #define XILINX_DMA_CR_COALESCE_SHIFT    16
 173 #define XILINX_DMA_BD_SOP               BIT(27)
 174 #define XILINX_DMA_BD_EOP               BIT(26)
 175 #define XILINX_DMA_COALESCE_MAX         255
 176 #define XILINX_DMA_NUM_DESCS            255
 177 #define XILINX_DMA_NUM_APP_WORDS        5
 178
 179 /* Multi-Channel DMA Descriptor offsets*/
 180 #define XILINX_DMA_MCRX_CDESC(x)        (0x40 + (x-1) * 0x20)
 181 #define XILINX_DMA_MCRX_TDESC(x)        (0x48 + (x-1) * 0x20)
 182
 183 /* Multi-Channel DMA Masks/Shifts */
 184 #define XILINX_DMA_BD_HSIZE_MASK        GENMASK(15, 0)
 185 #define XILINX_DMA_BD_STRIDE_MASK       GENMASK(15, 0)
 186 #define XILINX_DMA_BD_VSIZE_MASK        GENMASK(31, 19)
 187 #define XILINX_DMA_BD_TDEST_MASK        GENMASK(4, 0)
 188 #define XILINX_DMA_BD_STRIDE_SHIFT      0
 189 #define XILINX_DMA_BD_VSIZE_SHIFT       19
 190
 191 /* AXI CDMA Specific Registers/Offsets */
 192 #define XILINX_CDMA_REG_SRCADDR         0x18
 193 #define XILINX_CDMA_REG_DSTADDR         0x20
 194
 195 /* AXI CDMA Specific Masks */
 196 #define XILINX_CDMA_CR_SGMODE          BIT(3)
 197
 198 /**
 199  * struct xilinx_vdma_desc_hw - Hardware Descriptor
 200  * @next_desc: Next Descriptor Pointer @0x00
 201  * @pad1: Reserved @0x04
 202  * @buf_addr: Buffer address @0x08
 203  * @buf_addr_msb: MSB of Buffer address @0x0C
 204  * @vsize: Vertical Size @0x10
 205  * @hsize: Horizontal Size @0x14
 206  * @stride: Number of bytes between the first
 207  *          pixels of each horizontal line @0x18
 208  */
 209 struct xilinx_vdma_desc_hw {
 210         u32 next_desc;
 211         u32 pad1;
 212         u32 buf_addr;
 213         u32 buf_addr_msb;
 214         u32 vsize;
 215         u32 hsize;
 216         u32 stride;
 217 } __aligned(64);
 218
 219 /**
 220  * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
 221  * @next_desc: Next Descriptor Pointer @0x00
 222  * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
 223  * @buf_addr: Buffer address @0x08
 224  * @buf_addr_msb: MSB of Buffer address @0x0C
 225  * @mcdma_control: Control field for mcdma @0x10
 226  * @vsize_stride: Vsize and Stride field for mcdma @0x14
 227  * @control: Control field @0x18
 228  * @status: Status field @0x1C
 229  * @app: APP Fields @0x20 - 0x30
 230  */
 231 struct xilinx_axidma_desc_hw {
 232         u32 next_desc;
 233         u32 next_desc_msb;
 234         u32 buf_addr;
 235         u32 buf_addr_msb;
 236         u32 mcdma_control;
 237         u32 vsize_stride;
 238         u32 control;
 239         u32 status;
 240         u32 app[XILINX_DMA_NUM_APP_WORDS];
 241 } __aligned(64);
 242
 243 /**
 244  * struct xilinx_cdma_desc_hw - Hardware Descriptor
 245  * @next_desc: Next Descriptor Pointer @0x00
 246  * @next_desc_msb: Next Descriptor Pointer MSB @0x04
 247  * @src_addr: Source address @0x08
 248  * @src_addr_msb: Source address MSB @0x0C
 249  * @dest_addr: Destination address @0x10
 250  * @dest_addr_msb: Destination address MSB @0x14
 251  * @control: Control field @0x18
 252  * @status: Status field @0x1C
 253  */
 254 struct xilinx_cdma_desc_hw {
 255         u32 next_desc;
 256         u32 next_desc_msb;
 257         u32 src_addr;
 258         u32 src_addr_msb;
 259         u32 dest_addr;
 260         u32 dest_addr_msb;
 261         u32 control;
 262         u32 status;
 263 } __aligned(64);
 264
 265 /**
 266  * struct xilinx_vdma_tx_segment - Descriptor segment
 267  * @hw: Hardware descriptor
 268  * @node: Node in the descriptor segments list
 269  * @phys: Physical address of segment
 270  */
 271 struct xilinx_vdma_tx_segment {
 272         struct xilinx_vdma_desc_hw hw;
 273         struct list_head node;
 274         dma_addr_t phys;
 275 } __aligned(64);
 276
 277 /**
 278  * struct xilinx_axidma_tx_segment - Descriptor segment
 279  * @hw: Hardware descriptor
 280  * @node: Node in the descriptor segments list
 281  * @phys: Physical address of segment
 282  */
 283 struct xilinx_axidma_tx_segment {
 284         struct xilinx_axidma_desc_hw hw;
 285         struct list_head node;
 286         dma_addr_t phys;
 287 } __aligned(64);
 288
 289 /**
 290  * struct xilinx_cdma_tx_segment - Descriptor segment
 291  * @hw: Hardware descriptor
 292  * @node: Node in the descriptor segments list
 293  * @phys: Physical address of segment
 294  */
 295 struct xilinx_cdma_tx_segment {
 296         struct xilinx_cdma_desc_hw hw;
 297         struct list_head node;
 298         dma_addr_t phys;
 299 } __aligned(64);
 300
 301 /**
 302  * struct xilinx_dma_tx_descriptor - Per Transaction structure
 303  * @async_tx: Async transaction descriptor
 304  * @segments: TX segments list
 305  * @node: Node in the channel descriptors list
 306  * @cyclic: Check for cyclic transfers.
 307  */
 308 struct xilinx_dma_tx_descriptor {
 309         struct dma_async_tx_descriptor async_tx;
 310         struct list_head segments;
 311         struct list_head node;
 312         bool cyclic;
 313 };
 314
 315 /**
 316  * struct xilinx_dma_chan - Driver specific DMA channel structure
 317  * @xdev: Driver specific device structure
 318  * @ctrl_offset: Control registers offset
 319  * @desc_offset: TX descriptor registers offset
 320  * @lock: Descriptor operation lock
 321  * @pending_list: Descriptors waiting
 322  * @active_list: Descriptors ready to submit
 323  * @done_list: Complete descriptors
 324  * @free_seg_list: Free descriptors
 325  * @common: DMA common channel
 326  * @desc_pool: Descriptors pool
 327  * @dev: The dma device
 328  * @irq: Channel IRQ
 329  * @id: Channel ID
 330  * @direction: Transfer direction
 331  * @num_frms: Number of frames
 332  * @has_sg: Support scatter transfers
 333  * @cyclic: Check for cyclic transfers.
 334  * @genlock: Support genlock mode
 335  * @err: Channel has errors
 336  * @idle: Check for channel idle
 337  * @terminating: Check for channel being synchronized by user
 338  * @tasklet: Cleanup work after irq
 339  * @config: Device configuration info
 340  * @flush_on_fsync: Flush on Frame sync
 341  * @desc_pendingcount: Descriptor pending count
 342  * @ext_addr: Indicates 64 bit addressing is supported by dma channel
 343  * @desc_submitcount: Descriptor h/w submitted count
 344  * @residue: Residue for AXI DMA
 345  * @seg_v: Statically allocated segments base
 346  * @seg_p: Physical allocated segments base
 347  * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
 348  * @cyclic_seg_p: Physical allocated segments base for cyclic dma
 349  * @start_transfer: Differentiate b/w DMA IP's transfer
 350  * @stop_transfer: Differentiate b/w DMA IP's quiesce
 351  * @tdest: TDEST value for mcdma
 352  * @has_vflip: S2MM vertical flip
 353  */
 354 struct xilinx_dma_chan {
 355         struct xilinx_dma_device *xdev;
 356         u32 ctrl_offset;
 357         u32 desc_offset;
 358         spinlock_t lock;
 359         struct list_head pending_list;
 360         struct list_head active_list;
 361         struct list_head done_list;
 362         struct list_head free_seg_list;
 363         struct dma_chan common;
 364         struct dma_pool *desc_pool;
 365         struct device *dev;
 366         int irq;
 367         int id;
 368         enum dma_transfer_direction direction;
 369         int num_frms;
 370         bool has_sg;
 371         bool cyclic;
 372         bool genlock;
 373         bool err;
 374         bool idle;
 375         bool terminating;
 376         struct tasklet_struct tasklet;
 377         struct xilinx_vdma_config config;
 378         bool flush_on_fsync;
 379         u32 desc_pendingcount;
 380         bool ext_addr;
 381         u32 desc_submitcount;
 382         u32 residue;
 383         struct xilinx_axidma_tx_segment *seg_v;
 384         dma_addr_t seg_p;
 385         struct xilinx_axidma_tx_segment *cyclic_seg_v;
 386         dma_addr_t cyclic_seg_p;
 387         void (*start_transfer)(struct xilinx_dma_chan *chan);
 388         int (*stop_transfer)(struct xilinx_dma_chan *chan);
 389         u16 tdest;
 390         bool has_vflip;
 391 };
 392
 393 /**
 394  * enum xdma_ip_type - DMA IP type.
 395  *
 396  * @XDMA_TYPE_AXIDMA: Axi dma ip.
 397  * @XDMA_TYPE_CDMA: Axi cdma ip.
 398  * @XDMA_TYPE_VDMA: Axi vdma ip.
 399  *
 400  */
 401 enum xdma_ip_type {
 402         XDMA_TYPE_AXIDMA = 0,
 403         XDMA_TYPE_CDMA,
 404         XDMA_TYPE_VDMA,
 405 };
 406
 407 struct xilinx_dma_config {
 408         enum xdma_ip_type dmatype;
 409         int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
 410                         struct clk **tx_clk, struct clk **txs_clk,
 411                         struct clk **rx_clk, struct clk **rxs_clk);
 412 };
 413
 414 /**
 415  * struct xilinx_dma_device - DMA device structure
 416  * @regs: I/O mapped base address
 417  * @dev: Device Structure
 418  * @common: DMA device structure
 419  * @chan: Driver specific DMA channel
 420  * @has_sg: Specifies whether Scatter-Gather is present or not
 421  * @mcdma: Specifies whether Multi-Channel is present or not
 422  * @flush_on_fsync: Flush on frame sync
 423  * @ext_addr: Indicates 64 bit addressing is supported by dma device
 424  * @pdev: Platform device structure pointer
 425  * @dma_config: DMA config structure
 426  * @axi_clk: DMA Axi4-lite interace clock
 427  * @tx_clk: DMA mm2s clock
 428  * @txs_clk: DMA mm2s stream clock
 429  * @rx_clk: DMA s2mm clock
 430  * @rxs_clk: DMA s2mm stream clock
 431  * @nr_channels: Number of channels DMA device supports
 432  * @chan_id: DMA channel identifier
 433  * @max_buffer_len: Max buffer length
 434  */
 435 struct xilinx_dma_device {
 436         void __iomem *regs;
 437         struct device *dev;
 438         struct dma_device common;
 439         struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
 440         bool has_sg;
 441         bool mcdma;
 442         u32 flush_on_fsync;
 443         bool ext_addr;
 444         struct platform_device  *pdev;
 445         const struct xilinx_dma_config *dma_config;
 446         struct clk *axi_clk;
 447         struct clk *tx_clk;
 448         struct clk *txs_clk;
 449         struct clk *rx_clk;
 450         struct clk *rxs_clk;
 451         u32 nr_channels;
 452         u32 chan_id;
 453         u32 max_buffer_len;
 454 };
 455
 456 /* Macros */
 457 #define to_xilinx_chan(chan) \
 458         container_of(chan, struct xilinx_dma_chan, common)
 459 #define to_dma_tx_descriptor(tx) \
 460         container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
 461 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
 462         readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
 463                                   val, cond, delay_us, timeout_us)
 464
 465 /* IO accessors */
 466 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
 467 {
 468         return ioread32(chan->xdev->regs + reg);
 469 }
 470
 471 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
 472 {
 473         iowrite32(value, chan->xdev->regs + reg);
 474 }
 475
 476 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
 477                                    u32 value)
 478 {
 479         dma_write(chan, chan->desc_offset + reg, value);
 480 }
 481
 482 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
 483 {
 484         return dma_read(chan, chan->ctrl_offset + reg);
 485 }
 486
 487 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
 488                                    u32 value)
 489 {
 490         dma_write(chan, chan->ctrl_offset + reg, value);
 491 }
 492
 493 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
 494                                  u32 clr)
 495 {
 496         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
 497 }
 498
 499 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
 500                                  u32 set)
 501 {
 502         dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
 503 }
 504
 505 /**
 506  * vdma_desc_write_64 - 64-bit descriptor write
 507  * @chan: Driver specific VDMA channel
 508  * @reg: Register to write
 509  * @value_lsb: lower address of the descriptor.
 510  * @value_msb: upper address of the descriptor.
 511  *
 512  * Since vdma driver is trying to write to a register offset which is not a
 513  * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
 514  * instead of a single 64 bit register write.
 515  */
 516 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
 517                                       u32 value_lsb, u32 value_msb)
 518 {
 519         /* Write the lsb 32 bits*/
 520         writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
 521
 522         /* Write the msb 32 bits */
 523         writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
 524 }
 525
 526 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
 527 {
 528         lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
 529 }
 530
 531 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
 532                                 dma_addr_t addr)
 533 {
 534         if (chan->ext_addr)
 535                 dma_writeq(chan, reg, addr);
 536         else
 537                 dma_ctrl_write(chan, reg, addr);
 538 }
 539
 540 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
 541                                      struct xilinx_axidma_desc_hw *hw,
 542                                      dma_addr_t buf_addr, size_t sg_used,
 543                                      size_t period_len)
 544 {
 545         if (chan->ext_addr) {
 546                 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
 547                 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
 548                                                  period_len);
 549         } else {
 550                 hw->buf_addr = buf_addr + sg_used + period_len;
 551         }
 552 }
 553
 554 /* -----------------------------------------------------------------------------
 555  * Descriptors and segments alloc and free
 556  */
 557
 558 /**
 559  * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
 560  * @chan: Driver specific DMA channel
 561  *
 562  * Return: The allocated segment on success and NULL on failure.
 563  */
 564 static struct xilinx_vdma_tx_segment *
 565 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 566 {
 567         struct xilinx_vdma_tx_segment *segment;
 568         dma_addr_t phys;
 569
 570         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 571         if (!segment)
 572                 return NULL;
 573
 574         segment->phys = phys;
 575
 576         return segment;
 577 }
 578
 579 /**
 580  * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
 581  * @chan: Driver specific DMA channel
 582  *
 583  * Return: The allocated segment on success and NULL on failure.
 584  */
 585 static struct xilinx_cdma_tx_segment *
 586 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 587 {
 588         struct xilinx_cdma_tx_segment *segment;
 589         dma_addr_t phys;
 590
 591         segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
 592         if (!segment)
 593                 return NULL;
 594
 595         segment->phys = phys;
 596
 597         return segment;
 598 }
 599
 600 /**
 601  * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
 602  * @chan: Driver specific DMA channel
 603  *
 604  * Return: The allocated segment on success and NULL on failure.
 605  */
 606 static struct xilinx_axidma_tx_segment *
 607 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
 608 {
 609         struct xilinx_axidma_tx_segment *segment = NULL;
 610         unsigned long flags;
 611
 612         spin_lock_irqsave(&chan->lock, flags);
 613         if (!list_empty(&chan->free_seg_list)) {
 614                 segment = list_first_entry(&chan->free_seg_list,
 615                                            struct xilinx_axidma_tx_segment,
 616                                            node);
 617                 list_del(&segment->node);
 618         }
 619         spin_unlock_irqrestore(&chan->lock, flags);
 620
 621         return segment;
 622 }
 623
 624 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
 625 {
 626         u32 next_desc = hw->next_desc;
 627         u32 next_desc_msb = hw->next_desc_msb;
 628
 629         memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
 630
 631         hw->next_desc = next_desc;
 632         hw->next_desc_msb = next_desc_msb;
 633 }
 634
 635 /**
 636  * xilinx_dma_free_tx_segment - Free transaction segment
 637  * @chan: Driver specific DMA channel
 638  * @segment: DMA transaction segment
 639  */
 640 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
 641                                 struct xilinx_axidma_tx_segment *segment)
 642 {
 643         xilinx_dma_clean_hw_desc(&segment->hw);
 644
 645         list_add_tail(&segment->node, &chan->free_seg_list);
 646 }
 647
 648 /**
 649  * xilinx_cdma_free_tx_segment - Free transaction segment
 650  * @chan: Driver specific DMA channel
 651  * @segment: DMA transaction segment
 652  */
 653 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
 654                                 struct xilinx_cdma_tx_segment *segment)
 655 {
 656         dma_pool_free(chan->desc_pool, segment, segment->phys);
 657 }
 658
 659 /**
 660  * xilinx_vdma_free_tx_segment - Free transaction segment
 661  * @chan: Driver specific DMA channel
 662  * @segment: DMA transaction segment
 663  */
 664 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
 665                                         struct xilinx_vdma_tx_segment *segment)
 666 {
 667         dma_pool_free(chan->desc_pool, segment, segment->phys);
 668 }
 669
 670 /**
 671  * xilinx_dma_tx_descriptor - Allocate transaction descriptor
 672  * @chan: Driver specific DMA channel
 673  *
 674  * Return: The allocated descriptor on success and NULL on failure.
 675  */
 676 static struct xilinx_dma_tx_descriptor *
 677 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
 678 {
 679         struct xilinx_dma_tx_descriptor *desc;
 680
 681         desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 682         if (!desc)
 683                 return NULL;
 684
 685         INIT_LIST_HEAD(&desc->segments);
 686
 687         return desc;
 688 }
 689
 690 /**
 691  * xilinx_dma_free_tx_descriptor - Free transaction descriptor
 692  * @chan: Driver specific DMA channel
 693  * @desc: DMA transaction descriptor
 694  */
 695 static void
 696 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
 697                                struct xilinx_dma_tx_descriptor *desc)
 698 {
 699         struct xilinx_vdma_tx_segment *segment, *next;
 700         struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
 701         struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
 702
 703         if (!desc)
 704                 return;
 705
 706         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
 707                 list_for_each_entry_safe(segment, next, &desc->segments, node) {
 708                         list_del(&segment->node);
 709                         xilinx_vdma_free_tx_segment(chan, segment);
 710                 }
 711         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 712                 list_for_each_entry_safe(cdma_segment, cdma_next,
 713                                          &desc->segments, node) {
 714                         list_del(&cdma_segment->node);
 715                         xilinx_cdma_free_tx_segment(chan, cdma_segment);
 716                 }
 717         } else {
 718                 list_for_each_entry_safe(axidma_segment, axidma_next,
 719                                          &desc->segments, node) {
 720                         list_del(&axidma_segment->node);
 721                         xilinx_dma_free_tx_segment(chan, axidma_segment);
 722                 }
 723         }
 724
 725         kfree(desc);
 726 }
 727
 728 /* Required functions */
 729
 730 /**
 731  * xilinx_dma_free_desc_list - Free descriptors list
 732  * @chan: Driver specific DMA channel
 733  * @list: List to parse and delete the descriptor
 734  */
 735 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
 736                                         struct list_head *list)
 737 {
 738         struct xilinx_dma_tx_descriptor *desc, *next;
 739
 740         list_for_each_entry_safe(desc, next, list, node) {
 741                 list_del(&desc->node);
 742                 xilinx_dma_free_tx_descriptor(chan, desc);
 743         }
 744 }
 745
 746 /**
 747  * xilinx_dma_free_descriptors - Free channel descriptors
 748  * @chan: Driver specific DMA channel
 749  */
 750 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
 751 {
 752         unsigned long flags;
 753
 754         spin_lock_irqsave(&chan->lock, flags);
 755
 756         xilinx_dma_free_desc_list(chan, &chan->pending_list);
 757         xilinx_dma_free_desc_list(chan, &chan->done_list);
 758         xilinx_dma_free_desc_list(chan, &chan->active_list);
 759
 760         spin_unlock_irqrestore(&chan->lock, flags);
 761 }
 762
 763 /**
 764  * xilinx_dma_free_chan_resources - Free channel resources
 765  * @dchan: DMA channel
 766  */
 767 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
 768 {
 769         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
 770         unsigned long flags;
 771
 772         dev_dbg(chan->dev, "Free all channel resources.\n");
 773
 774         xilinx_dma_free_descriptors(chan);
 775
 776         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 777                 spin_lock_irqsave(&chan->lock, flags);
 778                 INIT_LIST_HEAD(&chan->free_seg_list);
 779                 spin_unlock_irqrestore(&chan->lock, flags);
 780
 781                 /* Free memory that is allocated for BD */
 782                 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
 783                                   XILINX_DMA_NUM_DESCS, chan->seg_v,
 784                                   chan->seg_p);
 785
 786                 /* Free Memory that is allocated for cyclic DMA Mode */
 787                 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
 788                                   chan->cyclic_seg_v, chan->cyclic_seg_p);
 789         }
 790
 791         if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) {
 792                 dma_pool_destroy(chan->desc_pool);
 793                 chan->desc_pool = NULL;
 794         }
 795 }
 796
 797 /**
 798  * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
 799  * @chan: Driver specific dma channel
 800  * @desc: dma transaction descriptor
 801  * @flags: flags for spin lock
 802  */
 803 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
 804                                           struct xilinx_dma_tx_descriptor *desc,
 805                                           unsigned long *flags)
 806 {
 807         dma_async_tx_callback callback;
 808         void *callback_param;
 809
 810         callback = desc->async_tx.callback;
 811         callback_param = desc->async_tx.callback_param;
 812         if (callback) {
 813                 spin_unlock_irqrestore(&chan->lock, *flags);
 814                 callback(callback_param);
 815                 spin_lock_irqsave(&chan->lock, *flags);
 816         }
 817 }
 818
 819 /**
 820  * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
 821  * @chan: Driver specific DMA channel
 822  */
 823 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
 824 {
 825         struct xilinx_dma_tx_descriptor *desc, *next;
 826         unsigned long flags;
 827
 828         spin_lock_irqsave(&chan->lock, flags);
 829
 830         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
 831                 struct dmaengine_desc_callback cb;
 832
 833                 if (desc->cyclic) {
 834                         xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
 835                         break;
 836                 }
 837
 838                 /* Remove from the list of running transactions */
 839                 list_del(&desc->node);
 840
 841                 /* Run the link descriptor callback function */
 842                 dmaengine_desc_get_callback(&desc->async_tx, &cb);
 843                 if (dmaengine_desc_callback_valid(&cb)) {
 844                         spin_unlock_irqrestore(&chan->lock, flags);
 845                         dmaengine_desc_callback_invoke(&cb, NULL);
 846                         spin_lock_irqsave(&chan->lock, flags);
 847                 }
 848
 849                 /* Run any dependencies, then free the descriptor */
 850                 dma_run_dependencies(&desc->async_tx);
 851                 xilinx_dma_free_tx_descriptor(chan, desc);
 852
 853                 /*
 854                  * While we ran a callback the user called a terminate function,
 855                  * which takes care of cleaning up any remaining descriptors
 856                  */
 857                 if (chan->terminating)
 858                         break;
 859         }
 860
 861         spin_unlock_irqrestore(&chan->lock, flags);
 862 }
 863
 864 /**
 865  * xilinx_dma_do_tasklet - Schedule completion tasklet
 866  * @data: Pointer to the Xilinx DMA channel structure
 867  */
 868 static void xilinx_dma_do_tasklet(unsigned long data)
 869 {
 870         struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
 871
 872         xilinx_dma_chan_desc_cleanup(chan);
 873 }
 874
 875 /**
 876  * xilinx_dma_alloc_chan_resources - Allocate channel resources
 877  * @dchan: DMA channel
 878  *
 879  * Return: '0' on success and failure value on error
 880  */
 881 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
 882 {
 883         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
 884         int i;
 885
 886         /* Has this channel already been allocated? */
 887         if (chan->desc_pool)
 888                 return 0;
 889
 890         /*
 891          * We need the descriptor to be aligned to 64bytes
 892          * for meeting Xilinx VDMA specification requirement.
 893          */
 894         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 895                 /* Allocate the buffer descriptors. */
 896                 chan->seg_v = dma_zalloc_coherent(chan->dev,
 897                                                   sizeof(*chan->seg_v) *
 898                                                   XILINX_DMA_NUM_DESCS,
 899                                                   &chan->seg_p, GFP_KERNEL);
 900                 if (!chan->seg_v) {
 901                         dev_err(chan->dev,
 902                                 "unable to allocate channel %d descriptors\n",
 903                                 chan->id);
 904                         return -ENOMEM;
 905                 }
 906
 907                 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
 908                         chan->seg_v[i].hw.next_desc =
 909                         lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
 910                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
 911                         chan->seg_v[i].hw.next_desc_msb =
 912                         upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
 913                                 ((i + 1) % XILINX_DMA_NUM_DESCS));
 914                         chan->seg_v[i].phys = chan->seg_p +
 915                                 sizeof(*chan->seg_v) * i;
 916                         list_add_tail(&chan->seg_v[i].node,
 917                                       &chan->free_seg_list);
 918                 }
 919         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
 920                 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
 921                                    chan->dev,
 922                                    sizeof(struct xilinx_cdma_tx_segment),
 923                                    __alignof__(struct xilinx_cdma_tx_segment),
 924                                    0);
 925         } else {
 926                 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
 927                                      chan->dev,
 928                                      sizeof(struct xilinx_vdma_tx_segment),
 929                                      __alignof__(struct xilinx_vdma_tx_segment),
 930                                      0);
 931         }
 932
 933         if (!chan->desc_pool &&
 934             (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) {
 935                 dev_err(chan->dev,
 936                         "unable to allocate channel %d descriptor pool\n",
 937                         chan->id);
 938                 return -ENOMEM;
 939         }
 940
 941         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 942                 /*
 943                  * For cyclic DMA mode we need to program the tail Descriptor
 944                  * register with a value which is not a part of the BD chain
 945                  * so allocating a desc segment during channel allocation for
 946                  * programming tail descriptor.
 947                  */
 948                 chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
 949                                         sizeof(*chan->cyclic_seg_v),
 950                                         &chan->cyclic_seg_p, GFP_KERNEL);
 951                 if (!chan->cyclic_seg_v) {
 952                         dev_err(chan->dev,
 953                                 "unable to allocate desc segment for cyclic DMA\n");
 954                         return -ENOMEM;
 955                 }
 956                 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
 957         }
 958
 959         dma_cookie_init(dchan);
 960
 961         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 962                 /* For AXI DMA resetting once channel will reset the
 963                  * other channel as well so enable the interrupts here.
 964                  */
 965                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
 966                               XILINX_DMA_DMAXR_ALL_IRQ_MASK);
 967         }
 968
 969         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
 970                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
 971                              XILINX_CDMA_CR_SGMODE);
 972
 973         return 0;
 974 }
 975
 976 /**
 977  * xilinx_dma_calc_copysize - Calculate the amount of data to copy
 978  * @chan: Driver specific DMA channel
 979  * @size: Total data that needs to be copied
 980  * @done: Amount of data that has been already copied
 981  *
 982  * Return: Amount of data that has to be copied
 983  */
 984 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
 985                                     int size, int done)
 986 {
 987         size_t copy;
 988
 989         copy = min_t(size_t, size - done,
 990                      chan->xdev->max_buffer_len);
 991
 992         return copy;
 993 }
 994
 995 /**
 996  * xilinx_dma_tx_status - Get DMA transaction status
 997  * @dchan: DMA channel
 998  * @cookie: Transaction identifier
 999  * @txstate: Transaction state
1000  *
1001  * Return: DMA transaction status
1002  */
1003 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1004                                         dma_cookie_t cookie,
1005                                         struct dma_tx_state *txstate)
1006 {
1007         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1008         struct xilinx_dma_tx_descriptor *desc;
1009         struct xilinx_axidma_tx_segment *segment;
1010         struct xilinx_axidma_desc_hw *hw;
1011         enum dma_status ret;
1012         unsigned long flags;
1013         u32 residue = 0;
1014
1015         ret = dma_cookie_status(dchan, cookie, txstate);
1016         if (ret == DMA_COMPLETE || !txstate)
1017                 return ret;
1018
1019         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1020                 spin_lock_irqsave(&chan->lock, flags);
1021
1022                 desc = list_last_entry(&chan->active_list,
1023                                        struct xilinx_dma_tx_descriptor, node);
1024                 if (chan->has_sg) {
1025                         list_for_each_entry(segment, &desc->segments, node) {
1026                                 hw = &segment->hw;
1027                                 residue += (hw->control - hw->status) &
1028                                            chan->xdev->max_buffer_len;
1029                         }
1030                 }
1031                 spin_unlock_irqrestore(&chan->lock, flags);
1032
1033                 chan->residue = residue;
1034                 dma_set_residue(txstate, chan->residue);
1035         }
1036
1037         return ret;
1038 }
1039
1040 /**
1041  * xilinx_dma_stop_transfer - Halt DMA channel
1042  * @chan: Driver specific DMA channel
1043  *
1044  * Return: '0' on success and failure value on error
1045  */
1046 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1047 {
1048         u32 val;
1049
1050         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1051
1052         /* Wait for the hardware to halt */
1053         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1054                                        val & XILINX_DMA_DMASR_HALTED, 0,
1055                                        XILINX_DMA_LOOP_COUNT);
1056 }
1057
1058 /**
1059  * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1060  * @chan: Driver specific DMA channel
1061  *
1062  * Return: '0' on success and failure value on error
1063  */
1064 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1065 {
1066         u32 val;
1067
1068         return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1069                                        val & XILINX_DMA_DMASR_IDLE, 0,
1070                                        XILINX_DMA_LOOP_COUNT);
1071 }
1072
1073 /**
1074  * xilinx_dma_start - Start DMA channel
1075  * @chan: Driver specific DMA channel
1076  */
1077 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1078 {
1079         int err;
1080         u32 val;
1081
1082         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1083
1084         /* Wait for the hardware to start */
1085         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1086                                       !(val & XILINX_DMA_DMASR_HALTED), 0,
1087                                       XILINX_DMA_LOOP_COUNT);
1088
1089         if (err) {
1090                 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1091                         chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1092
1093                 chan->err = true;
1094         }
1095 }
1096
1097 /**
1098  * xilinx_vdma_start_transfer - Starts VDMA transfer
1099  * @chan: Driver specific channel struct pointer
1100  */
1101 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1102 {
1103         struct xilinx_vdma_config *config = &chan->config;
1104         struct xilinx_dma_tx_descriptor *desc, *tail_desc;
1105         u32 reg, j;
1106         struct xilinx_vdma_tx_segment *tail_segment;
1107
1108         /* This function was invoked with lock held */
1109         if (chan->err)
1110                 return;
1111
1112         if (!chan->idle)
1113                 return;
1114
1115         if (list_empty(&chan->pending_list))
1116                 return;
1117
1118         desc = list_first_entry(&chan->pending_list,
1119                                 struct xilinx_dma_tx_descriptor, node);
1120         tail_desc = list_last_entry(&chan->pending_list,
1121                                     struct xilinx_dma_tx_descriptor, node);
1122
1123         tail_segment = list_last_entry(&tail_desc->segments,
1124                                        struct xilinx_vdma_tx_segment, node);
1125
1126         /*
1127          * If hardware is idle, then all descriptors on the running lists are
1128          * done, start new transfers
1129          */
1130         if (chan->has_sg)
1131                 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1132                                 desc->async_tx.phys);
1133
1134         /* Configure the hardware using info in the config structure */
1135         if (chan->has_vflip) {
1136                 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1137                 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1138                 reg |= config->vflip_en;
1139                 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1140                           reg);
1141         }
1142
1143         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1144
1145         if (config->frm_cnt_en)
1146                 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1147         else
1148                 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1149
1150         /*
1151          * With SG, start with circular mode, so that BDs can be fetched.
1152          * In direct register mode, if not parking, enable circular mode
1153          */
1154         if (chan->has_sg || !config->park)
1155                 reg |= XILINX_DMA_DMACR_CIRC_EN;
1156
1157         if (config->park)
1158                 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1159
1160         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1161
1162         j = chan->desc_submitcount;
1163         reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1164         if (chan->direction == DMA_MEM_TO_DEV) {
1165                 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1166                 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1167         } else {
1168                 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1169                 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1170         }
1171         dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1172
1173         /* Start the hardware */
1174         xilinx_dma_start(chan);
1175
1176         if (chan->err)
1177                 return;
1178
1179         /* Start the transfer */
1180         if (chan->has_sg) {
1181                 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1182                                 tail_segment->phys);
1183                 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1184                 chan->desc_pendingcount = 0;
1185         } else {
1186                 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1187                 int i = 0;
1188
1189                 if (chan->desc_submitcount < chan->num_frms)
1190                         i = chan->desc_submitcount;
1191
1192                 list_for_each_entry(segment, &desc->segments, node) {
1193                         if (chan->ext_addr)
1194                                 vdma_desc_write_64(chan,
1195                                         XILINX_VDMA_REG_START_ADDRESS_64(i++),
1196                                         segment->hw.buf_addr,
1197                                         segment->hw.buf_addr_msb);
1198                         else
1199                                 vdma_desc_write(chan,
1200                                         XILINX_VDMA_REG_START_ADDRESS(i++),
1201                                         segment->hw.buf_addr);
1202
1203                         last = segment;
1204                 }
1205
1206                 if (!last)
1207                         return;
1208
1209                 /* HW expects these parameters to be same for one transaction */
1210                 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1211                 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1212                                 last->hw.stride);
1213                 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1214
1215                 chan->desc_submitcount++;
1216                 chan->desc_pendingcount--;
1217                 list_del(&desc->node);
1218                 list_add_tail(&desc->node, &chan->active_list);
1219                 if (chan->desc_submitcount == chan->num_frms)
1220                         chan->desc_submitcount = 0;
1221         }
1222
1223         chan->idle = false;
1224 }
1225
1226 /**
1227  * xilinx_cdma_start_transfer - Starts cdma transfer
1228  * @chan: Driver specific channel struct pointer
1229  */
1230 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1231 {
1232         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1233         struct xilinx_cdma_tx_segment *tail_segment;
1234         u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1235
1236         if (chan->err)
1237                 return;
1238
1239         if (!chan->idle)
1240                 return;
1241
1242         if (list_empty(&chan->pending_list))
1243                 return;
1244
1245         head_desc = list_first_entry(&chan->pending_list,
1246                                      struct xilinx_dma_tx_descriptor, node);
1247         tail_desc = list_last_entry(&chan->pending_list,
1248                                     struct xilinx_dma_tx_descriptor, node);
1249         tail_segment = list_last_entry(&tail_desc->segments,
1250                                        struct xilinx_cdma_tx_segment, node);
1251
1252         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1253                 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1254                 ctrl_reg |= chan->desc_pendingcount <<
1255                                 XILINX_DMA_CR_COALESCE_SHIFT;
1256                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1257         }
1258
1259         if (chan->has_sg) {
1260                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1261                              XILINX_CDMA_CR_SGMODE);
1262
1263                 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1264                              XILINX_CDMA_CR_SGMODE);
1265
1266                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1267                              head_desc->async_tx.phys);
1268
1269                 /* Update tail ptr register which will start the transfer */
1270                 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1271                              tail_segment->phys);
1272         } else {
1273                 /* In simple mode */
1274                 struct xilinx_cdma_tx_segment *segment;
1275                 struct xilinx_cdma_desc_hw *hw;
1276
1277                 segment = list_first_entry(&head_desc->segments,
1278                                            struct xilinx_cdma_tx_segment,
1279                                            node);
1280
1281                 hw = &segment->hw;
1282
1283                 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
1284                 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
1285
1286                 /* Start the transfer */
1287                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1288                                 hw->control & chan->xdev->max_buffer_len);
1289         }
1290
1291         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1292         chan->desc_pendingcount = 0;
1293         chan->idle = false;
1294 }
1295
1296 /**
1297  * xilinx_dma_start_transfer - Starts DMA transfer
1298  * @chan: Driver specific channel struct pointer
1299  */
1300 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1301 {
1302         struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1303         struct xilinx_axidma_tx_segment *tail_segment;
1304         u32 reg;
1305
1306         if (chan->err)
1307                 return;
1308
1309         if (list_empty(&chan->pending_list))
1310                 return;
1311
1312         if (!chan->idle)
1313                 return;
1314
1315         head_desc = list_first_entry(&chan->pending_list,
1316                                      struct xilinx_dma_tx_descriptor, node);
1317         tail_desc = list_last_entry(&chan->pending_list,
1318                                     struct xilinx_dma_tx_descriptor, node);
1319         tail_segment = list_last_entry(&tail_desc->segments,
1320                                        struct xilinx_axidma_tx_segment, node);
1321
1322         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1323
1324         if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1325                 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1326                 reg |= chan->desc_pendingcount <<
1327                                   XILINX_DMA_CR_COALESCE_SHIFT;
1328                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1329         }
1330
1331         if (chan->has_sg && !chan->xdev->mcdma)
1332                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1333                              head_desc->async_tx.phys);
1334
1335         if (chan->has_sg && chan->xdev->mcdma) {
1336                 if (chan->direction == DMA_MEM_TO_DEV) {
1337                         dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1338                                        head_desc->async_tx.phys);
1339                 } else {
1340                         if (!chan->tdest) {
1341                                 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1342                                        head_desc->async_tx.phys);
1343                         } else {
1344                                 dma_ctrl_write(chan,
1345                                         XILINX_DMA_MCRX_CDESC(chan->tdest),
1346                                        head_desc->async_tx.phys);
1347                         }
1348                 }
1349         }
1350
1351         xilinx_dma_start(chan);
1352
1353         if (chan->err)
1354                 return;
1355
1356         /* Start the transfer */
1357         if (chan->has_sg && !chan->xdev->mcdma) {
1358                 if (chan->cyclic)
1359                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1360                                      chan->cyclic_seg_v->phys);
1361                 else
1362                         xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1363                                      tail_segment->phys);
1364         } else if (chan->has_sg && chan->xdev->mcdma) {
1365                 if (chan->direction == DMA_MEM_TO_DEV) {
1366                         dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1367                                tail_segment->phys);
1368                 } else {
1369                         if (!chan->tdest) {
1370                                 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1371                                                tail_segment->phys);
1372                         } else {
1373                                 dma_ctrl_write(chan,
1374                                         XILINX_DMA_MCRX_TDESC(chan->tdest),
1375                                         tail_segment->phys);
1376                         }
1377                 }
1378         } else {
1379                 struct xilinx_axidma_tx_segment *segment;
1380                 struct xilinx_axidma_desc_hw *hw;
1381
1382                 segment = list_first_entry(&head_desc->segments,
1383                                            struct xilinx_axidma_tx_segment,
1384                                            node);
1385                 hw = &segment->hw;
1386
1387                 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
1388
1389                 /* Start the transfer */
1390                 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1391                                hw->control & chan->xdev->max_buffer_len);
1392         }
1393
1394         list_splice_tail_init(&chan->pending_list, &chan->active_list);
1395         chan->desc_pendingcount = 0;
1396         chan->idle = false;
1397 }
1398
1399 /**
1400  * xilinx_dma_issue_pending - Issue pending transactions
1401  * @dchan: DMA channel
1402  */
1403 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1404 {
1405         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1406         unsigned long flags;
1407
1408         spin_lock_irqsave(&chan->lock, flags);
1409         chan->start_transfer(chan);
1410         spin_unlock_irqrestore(&chan->lock, flags);
1411 }
1412
1413 /**
1414  * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1415  * @chan : xilinx DMA channel
1416  *
1417  * CONTEXT: hardirq
1418  */
1419 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1420 {
1421         struct xilinx_dma_tx_descriptor *desc, *next;
1422
1423         /* This function was invoked with lock held */
1424         if (list_empty(&chan->active_list))
1425                 return;
1426
1427         list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1428                 list_del(&desc->node);
1429                 if (!desc->cyclic)
1430                         dma_cookie_complete(&desc->async_tx);
1431                 list_add_tail(&desc->node, &chan->done_list);
1432         }
1433 }
1434
1435 /**
1436  * xilinx_dma_reset - Reset DMA channel
1437  * @chan: Driver specific DMA channel
1438  *
1439  * Return: '0' on success and failure value on error
1440  */
1441 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1442 {
1443         int err;
1444         u32 tmp;
1445
1446         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1447
1448         /* Wait for the hardware to finish reset */
1449         err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1450                                       !(tmp & XILINX_DMA_DMACR_RESET), 0,
1451                                       XILINX_DMA_LOOP_COUNT);
1452
1453         if (err) {
1454                 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1455                         dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1456                         dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1457                 return -ETIMEDOUT;
1458         }
1459
1460         chan->err = false;
1461         chan->idle = true;
1462         chan->desc_pendingcount = 0;
1463         chan->desc_submitcount = 0;
1464
1465         return err;
1466 }
1467
1468 /**
1469  * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1470  * @chan: Driver specific DMA channel
1471  *
1472  * Return: '0' on success and failure value on error
1473  */
1474 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1475 {
1476         int err;
1477
1478         /* Reset VDMA */
1479         err = xilinx_dma_reset(chan);
1480         if (err)
1481                 return err;
1482
1483         /* Enable interrupts */
1484         dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1485                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1486
1487         return 0;
1488 }
1489
1490 /**
1491  * xilinx_dma_irq_handler - DMA Interrupt handler
1492  * @irq: IRQ number
1493  * @data: Pointer to the Xilinx DMA channel structure
1494  *
1495  * Return: IRQ_HANDLED/IRQ_NONE
1496  */
1497 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1498 {
1499         struct xilinx_dma_chan *chan = data;
1500         u32 status;
1501
1502         /* Read the status and ack the interrupts. */
1503         status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1504         if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1505                 return IRQ_NONE;
1506
1507         dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1508                         status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1509
1510         if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1511                 /*
1512                  * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1513                  * error is recoverable, ignore it. Otherwise flag the error.
1514                  *
1515                  * Only recoverable errors can be cleared in the DMASR register,
1516                  * make sure not to write to other error bits to 1.
1517                  */
1518                 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1519
1520                 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1521                                 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1522
1523                 if (!chan->flush_on_fsync ||
1524                     (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1525                         dev_err(chan->dev,
1526                                 "Channel %p has errors %x, cdr %x tdr %x\n",
1527                                 chan, errors,
1528                                 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1529                                 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1530                         chan->err = true;
1531                 }
1532         }
1533
1534         if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1535                 /*
1536                  * Device takes too long to do the transfer when user requires
1537                  * responsiveness.
1538                  */
1539                 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1540         }
1541
1542         if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1543                 spin_lock(&chan->lock);
1544                 xilinx_dma_complete_descriptor(chan);
1545                 chan->idle = true;
1546                 chan->start_transfer(chan);
1547                 spin_unlock(&chan->lock);
1548         }
1549
1550         tasklet_schedule(&chan->tasklet);
1551         return IRQ_HANDLED;
1552 }
1553
1554 /**
1555  * append_desc_queue - Queuing descriptor
1556  * @chan: Driver specific dma channel
1557  * @desc: dma transaction descriptor
1558  */
1559 static void append_desc_queue(struct xilinx_dma_chan *chan,
1560                               struct xilinx_dma_tx_descriptor *desc)
1561 {
1562         struct xilinx_vdma_tx_segment *tail_segment;
1563         struct xilinx_dma_tx_descriptor *tail_desc;
1564         struct xilinx_axidma_tx_segment *axidma_tail_segment;
1565         struct xilinx_cdma_tx_segment *cdma_tail_segment;
1566
1567         if (list_empty(&chan->pending_list))
1568                 goto append;
1569
1570         /*
1571          * Add the hardware descriptor to the chain of hardware descriptors
1572          * that already exists in memory.
1573          */
1574         tail_desc = list_last_entry(&chan->pending_list,
1575                                     struct xilinx_dma_tx_descriptor, node);
1576         if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1577                 tail_segment = list_last_entry(&tail_desc->segments,
1578                                                struct xilinx_vdma_tx_segment,
1579                                                node);
1580                 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1581         } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1582                 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1583                                                 struct xilinx_cdma_tx_segment,
1584                                                 node);
1585                 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1586         } else {
1587                 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1588                                                struct xilinx_axidma_tx_segment,
1589                                                node);
1590                 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1591         }
1592
1593         /*
1594          * Add the software descriptor and all children to the list
1595          * of pending transactions
1596          */
1597 append:
1598         list_add_tail(&desc->node, &chan->pending_list);
1599         chan->desc_pendingcount++;
1600
1601         if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1602             && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1603                 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1604                 chan->desc_pendingcount = chan->num_frms;
1605         }
1606 }
1607
1608 /**
1609  * xilinx_dma_tx_submit - Submit DMA transaction
1610  * @tx: Async transaction descriptor
1611  *
1612  * Return: cookie value on success and failure value on error
1613  */
1614 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1615 {
1616         struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1617         struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1618         dma_cookie_t cookie;
1619         unsigned long flags;
1620         int err;
1621
1622         if (chan->cyclic) {
1623                 xilinx_dma_free_tx_descriptor(chan, desc);
1624                 return -EBUSY;
1625         }
1626
1627         if (chan->err) {
1628                 /*
1629                  * If reset fails, need to hard reset the system.
1630                  * Channel is no longer functional
1631                  */
1632                 err = xilinx_dma_chan_reset(chan);
1633                 if (err < 0)
1634                         return err;
1635         }
1636
1637         spin_lock_irqsave(&chan->lock, flags);
1638
1639         cookie = dma_cookie_assign(tx);
1640
1641         /* Put this transaction onto the tail of the pending queue */
1642         append_desc_queue(chan, desc);
1643
1644         if (desc->cyclic)
1645                 chan->cyclic = true;
1646
1647         chan->terminating = false;
1648
1649         spin_unlock_irqrestore(&chan->lock, flags);
1650
1651         return cookie;
1652 }
1653
1654 /**
1655  * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1656  *      DMA_SLAVE transaction
1657  * @dchan: DMA channel
1658  * @xt: Interleaved template pointer
1659  * @flags: transfer ack flags
1660  *
1661  * Return: Async transaction descriptor on success and NULL on failure
1662  */
1663 static struct dma_async_tx_descriptor *
1664 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1665                                  struct dma_interleaved_template *xt,
1666                                  unsigned long flags)
1667 {
1668         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1669         struct xilinx_dma_tx_descriptor *desc;
1670         struct xilinx_vdma_tx_segment *segment;
1671         struct xilinx_vdma_desc_hw *hw;
1672
1673         if (!is_slave_direction(xt->dir))
1674                 return NULL;
1675
1676         if (!xt->numf || !xt->sgl[0].size)
1677                 return NULL;
1678
1679         if (xt->frame_size != 1)
1680                 return NULL;
1681
1682         /* Allocate a transaction descriptor. */
1683         desc = xilinx_dma_alloc_tx_descriptor(chan);
1684         if (!desc)
1685                 return NULL;
1686
1687         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1688         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1689         async_tx_ack(&desc->async_tx);
1690
1691         /* Allocate the link descriptor from DMA pool */
1692         segment = xilinx_vdma_alloc_tx_segment(chan);
1693         if (!segment)
1694                 goto error;
1695
1696         /* Fill in the hardware descriptor */
1697         hw = &segment->hw;
1698         hw->vsize = xt->numf;
1699         hw->hsize = xt->sgl[0].size;
1700         hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
1701                         XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
1702         hw->stride |= chan->config.frm_dly <<
1703                         XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
1704
1705         if (xt->dir != DMA_MEM_TO_DEV) {
1706                 if (chan->ext_addr) {
1707                         hw->buf_addr = lower_32_bits(xt->dst_start);
1708                         hw->buf_addr_msb = upper_32_bits(xt->dst_start);
1709                 } else {
1710                         hw->buf_addr = xt->dst_start;
1711                 }
1712         } else {
1713                 if (chan->ext_addr) {
1714                         hw->buf_addr = lower_32_bits(xt->src_start);
1715                         hw->buf_addr_msb = upper_32_bits(xt->src_start);
1716                 } else {
1717                         hw->buf_addr = xt->src_start;
1718                 }
1719         }
1720
1721         /* Insert the segment into the descriptor segments list. */
1722         list_add_tail(&segment->node, &desc->segments);
1723
1724         /* Link the last hardware descriptor with the first. */
1725         segment = list_first_entry(&desc->segments,
1726                                    struct xilinx_vdma_tx_segment, node);
1727         desc->async_tx.phys = segment->phys;
1728
1729         return &desc->async_tx;
1730
1731 error:
1732         xilinx_dma_free_tx_descriptor(chan, desc);
1733         return NULL;
1734 }
1735
1736 /**
1737  * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
1738  * @dchan: DMA channel
1739  * @dma_dst: destination address
1740  * @dma_src: source address
1741  * @len: transfer length
1742  * @flags: transfer ack flags
1743  *
1744  * Return: Async transaction descriptor on success and NULL on failure
1745  */
1746 static struct dma_async_tx_descriptor *
1747 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
1748                         dma_addr_t dma_src, size_t len, unsigned long flags)
1749 {
1750         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1751         struct xilinx_dma_tx_descriptor *desc;
1752         struct xilinx_cdma_tx_segment *segment;
1753         struct xilinx_cdma_desc_hw *hw;
1754
1755         if (!len || len > chan->xdev->max_buffer_len)
1756                 return NULL;
1757
1758         desc = xilinx_dma_alloc_tx_descriptor(chan);
1759         if (!desc)
1760                 return NULL;
1761
1762         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1763         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1764
1765         /* Allocate the link descriptor from DMA pool */
1766         segment = xilinx_cdma_alloc_tx_segment(chan);
1767         if (!segment)
1768                 goto error;
1769
1770         hw = &segment->hw;
1771         hw->control = len;
1772         hw->src_addr = dma_src;
1773         hw->dest_addr = dma_dst;
1774         if (chan->ext_addr) {
1775                 hw->src_addr_msb = upper_32_bits(dma_src);
1776                 hw->dest_addr_msb = upper_32_bits(dma_dst);
1777         }
1778
1779         /* Insert the segment into the descriptor segments list. */
1780         list_add_tail(&segment->node, &desc->segments);
1781
1782         desc->async_tx.phys = segment->phys;
1783         hw->next_desc = segment->phys;
1784
1785         return &desc->async_tx;
1786
1787 error:
1788         xilinx_dma_free_tx_descriptor(chan, desc);
1789         return NULL;
1790 }
1791
1792 /**
1793  * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1794  * @dchan: DMA channel
1795  * @sgl: scatterlist to transfer to/from
1796  * @sg_len: number of entries in @scatterlist
1797  * @direction: DMA direction
1798  * @flags: transfer ack flags
1799  * @context: APP words of the descriptor
1800  *
1801  * Return: Async transaction descriptor on success and NULL on failure
1802  */
1803 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
1804         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
1805         enum dma_transfer_direction direction, unsigned long flags,
1806         void *context)
1807 {
1808         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1809         struct xilinx_dma_tx_descriptor *desc;
1810         struct xilinx_axidma_tx_segment *segment = NULL;
1811         u32 *app_w = (u32 *)context;
1812         struct scatterlist *sg;
1813         size_t copy;
1814         size_t sg_used;
1815         unsigned int i;
1816
1817         if (!is_slave_direction(direction))
1818                 return NULL;
1819
1820         /* Allocate a transaction descriptor. */
1821         desc = xilinx_dma_alloc_tx_descriptor(chan);
1822         if (!desc)
1823                 return NULL;
1824
1825         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1826         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1827
1828         /* Build transactions using information in the scatter gather list */
1829         for_each_sg(sgl, sg, sg_len, i) {
1830                 sg_used = 0;
1831
1832                 /* Loop until the entire scatterlist entry is used */
1833                 while (sg_used < sg_dma_len(sg)) {
1834                         struct xilinx_axidma_desc_hw *hw;
1835
1836                         /* Get a free segment */
1837                         segment = xilinx_axidma_alloc_tx_segment(chan);
1838                         if (!segment)
1839                                 goto error;
1840
1841                         /*
1842                          * Calculate the maximum number of bytes to transfer,
1843                          * making sure it is less than the hw limit
1844                          */
1845                         copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
1846                                                         sg_used);
1847                         hw = &segment->hw;
1848
1849                         /* Fill in the descriptor */
1850                         xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
1851                                           sg_used, 0);
1852
1853                         hw->control = copy;
1854
1855                         if (chan->direction == DMA_MEM_TO_DEV) {
1856                                 if (app_w)
1857                                         memcpy(hw->app, app_w, sizeof(u32) *
1858                                                XILINX_DMA_NUM_APP_WORDS);
1859                         }
1860
1861                         sg_used += copy;
1862
1863                         /*
1864                          * Insert the segment into the descriptor segments
1865                          * list.
1866                          */
1867                         list_add_tail(&segment->node, &desc->segments);
1868                 }
1869         }
1870
1871         segment = list_first_entry(&desc->segments,
1872                                    struct xilinx_axidma_tx_segment, node);
1873         desc->async_tx.phys = segment->phys;
1874
1875         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1876         if (chan->direction == DMA_MEM_TO_DEV) {
1877                 segment->hw.control |= XILINX_DMA_BD_SOP;
1878                 segment = list_last_entry(&desc->segments,
1879                                           struct xilinx_axidma_tx_segment,
1880                                           node);
1881                 segment->hw.control |= XILINX_DMA_BD_EOP;
1882         }
1883
1884         return &desc->async_tx;
1885
1886 error:
1887         xilinx_dma_free_tx_descriptor(chan, desc);
1888         return NULL;
1889 }
1890
1891 /**
1892  * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
1893  * @dchan: DMA channel
1894  * @buf_addr: Physical address of the buffer
1895  * @buf_len: Total length of the cyclic buffers
1896  * @period_len: length of individual cyclic buffer
1897  * @direction: DMA direction
1898  * @flags: transfer ack flags
1899  *
1900  * Return: Async transaction descriptor on success and NULL on failure
1901  */
1902 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
1903         struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
1904         size_t period_len, enum dma_transfer_direction direction,
1905         unsigned long flags)
1906 {
1907         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1908         struct xilinx_dma_tx_descriptor *desc;
1909         struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
1910         size_t copy, sg_used;
1911         unsigned int num_periods;
1912         int i;
1913         u32 reg;
1914
1915         if (!period_len)
1916                 return NULL;
1917
1918         num_periods = buf_len / period_len;
1919
1920         if (!num_periods)
1921                 return NULL;
1922
1923         if (!is_slave_direction(direction))
1924                 return NULL;
1925
1926         /* Allocate a transaction descriptor. */
1927         desc = xilinx_dma_alloc_tx_descriptor(chan);
1928         if (!desc)
1929                 return NULL;
1930
1931         chan->direction = direction;
1932         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1933         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1934
1935         for (i = 0; i < num_periods; ++i) {
1936                 sg_used = 0;
1937
1938                 while (sg_used < period_len) {
1939                         struct xilinx_axidma_desc_hw *hw;
1940
1941                         /* Get a free segment */
1942                         segment = xilinx_axidma_alloc_tx_segment(chan);
1943                         if (!segment)
1944                                 goto error;
1945
1946                         /*
1947                          * Calculate the maximum number of bytes to transfer,
1948                          * making sure it is less than the hw limit
1949                          */
1950                         copy = xilinx_dma_calc_copysize(chan, period_len,
1951                                                         sg_used);
1952                         hw = &segment->hw;
1953                         xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
1954                                           period_len * i);
1955                         hw->control = copy;
1956
1957                         if (prev)
1958                                 prev->hw.next_desc = segment->phys;
1959
1960                         prev = segment;
1961                         sg_used += copy;
1962
1963                         /*
1964                          * Insert the segment into the descriptor segments
1965                          * list.
1966                          */
1967                         list_add_tail(&segment->node, &desc->segments);
1968                 }
1969         }
1970
1971         head_segment = list_first_entry(&desc->segments,
1972                                    struct xilinx_axidma_tx_segment, node);
1973         desc->async_tx.phys = head_segment->phys;
1974
1975         desc->cyclic = true;
1976         reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1977         reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
1978         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1979
1980         segment = list_last_entry(&desc->segments,
1981                                   struct xilinx_axidma_tx_segment,
1982                                   node);
1983         segment->hw.next_desc = (u32) head_segment->phys;
1984
1985         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1986         if (direction == DMA_MEM_TO_DEV) {
1987                 head_segment->hw.control |= XILINX_DMA_BD_SOP;
1988                 segment->hw.control |= XILINX_DMA_BD_EOP;
1989         }
1990
1991         return &desc->async_tx;
1992
1993 error:
1994         xilinx_dma_free_tx_descriptor(chan, desc);
1995         return NULL;
1996 }
1997
1998 /**
1999  * xilinx_dma_prep_interleaved - prepare a descriptor for a
2000  *      DMA_SLAVE transaction
2001  * @dchan: DMA channel
2002  * @xt: Interleaved template pointer
2003  * @flags: transfer ack flags
2004  *
2005  * Return: Async transaction descriptor on success and NULL on failure
2006  */
2007 static struct dma_async_tx_descriptor *
2008 xilinx_dma_prep_interleaved(struct dma_chan *dchan,
2009                                  struct dma_interleaved_template *xt,
2010                                  unsigned long flags)
2011 {
2012         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2013         struct xilinx_dma_tx_descriptor *desc;
2014         struct xilinx_axidma_tx_segment *segment;
2015         struct xilinx_axidma_desc_hw *hw;
2016
2017         if (!is_slave_direction(xt->dir))
2018                 return NULL;
2019
2020         if (!xt->numf || !xt->sgl[0].size)
2021                 return NULL;
2022
2023         if (xt->frame_size != 1)
2024                 return NULL;
2025
2026         /* Allocate a transaction descriptor. */
2027         desc = xilinx_dma_alloc_tx_descriptor(chan);
2028         if (!desc)
2029                 return NULL;
2030
2031         chan->direction = xt->dir;
2032         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2033         desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2034
2035         /* Get a free segment */
2036         segment = xilinx_axidma_alloc_tx_segment(chan);
2037         if (!segment)
2038                 goto error;
2039
2040         hw = &segment->hw;
2041
2042         /* Fill in the descriptor */
2043         if (xt->dir != DMA_MEM_TO_DEV)
2044                 hw->buf_addr = xt->dst_start;
2045         else
2046                 hw->buf_addr = xt->src_start;
2047
2048         hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
2049         hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
2050                             XILINX_DMA_BD_VSIZE_MASK;
2051         hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
2052                             XILINX_DMA_BD_STRIDE_MASK;
2053         hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
2054
2055         /*
2056          * Insert the segment into the descriptor segments
2057          * list.
2058          */
2059         list_add_tail(&segment->node, &desc->segments);
2060
2061
2062         segment = list_first_entry(&desc->segments,
2063                                    struct xilinx_axidma_tx_segment, node);
2064         desc->async_tx.phys = segment->phys;
2065
2066         /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2067         if (xt->dir == DMA_MEM_TO_DEV) {
2068                 segment->hw.control |= XILINX_DMA_BD_SOP;
2069                 segment = list_last_entry(&desc->segments,
2070                                           struct xilinx_axidma_tx_segment,
2071                                           node);
2072                 segment->hw.control |= XILINX_DMA_BD_EOP;
2073         }
2074
2075         return &desc->async_tx;
2076
2077 error:
2078         xilinx_dma_free_tx_descriptor(chan, desc);
2079         return NULL;
2080 }
2081
2082 /**
2083  * xilinx_dma_terminate_all - Halt the channel and free descriptors
2084  * @dchan: Driver specific DMA Channel pointer
2085  *
2086  * Return: '0' always.
2087  */
2088 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2089 {
2090         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2091         u32 reg;
2092         int err;
2093
2094         if (chan->cyclic)
2095                 xilinx_dma_chan_reset(chan);
2096
2097         err = chan->stop_transfer(chan);
2098         if (err) {
2099                 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2100                         chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
2101                 chan->err = true;
2102         }
2103
2104         /* Remove and free all of the descriptors in the lists */
2105         chan->terminating = true;
2106         xilinx_dma_free_descriptors(chan);
2107         chan->idle = true;
2108
2109         if (chan->cyclic) {
2110                 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2111                 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2112                 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2113                 chan->cyclic = false;
2114         }
2115
2116         if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2117                 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2118                              XILINX_CDMA_CR_SGMODE);
2119
2120         return 0;
2121 }
2122
2123 /**
2124  * xilinx_dma_channel_set_config - Configure VDMA channel
2125  * Run-time configuration for Axi VDMA, supports:
2126  * . halt the channel
2127  * . configure interrupt coalescing and inter-packet delay threshold
2128  * . start/stop parking
2129  * . enable genlock
2130  *
2131  * @dchan: DMA channel
2132  * @cfg: VDMA device configuration pointer
2133  *
2134  * Return: '0' on success and failure value on error
2135  */
2136 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2137                                         struct xilinx_vdma_config *cfg)
2138 {
2139         struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2140         u32 dmacr;
2141
2142         if (cfg->reset)
2143                 return xilinx_dma_chan_reset(chan);
2144
2145         dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2146
2147         chan->config.frm_dly = cfg->frm_dly;
2148         chan->config.park = cfg->park;
2149
2150         /* genlock settings */
2151         chan->config.gen_lock = cfg->gen_lock;
2152         chan->config.master = cfg->master;
2153
2154         dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2155         if (cfg->gen_lock && chan->genlock) {
2156                 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2157                 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2158                 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2159         }
2160
2161         chan->config.frm_cnt_en = cfg->frm_cnt_en;
2162         chan->config.vflip_en = cfg->vflip_en;
2163
2164         if (cfg->park)
2165                 chan->config.park_frm = cfg->park_frm;
2166         else
2167                 chan->config.park_frm = -1;
2168
2169         chan->config.coalesc = cfg->coalesc;
2170         chan->config.delay = cfg->delay;
2171
2172         if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2173                 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2174                 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2175                 chan->config.coalesc = cfg->coalesc;
2176         }
2177
2178         if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2179                 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2180                 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2181                 chan->config.delay = cfg->delay;
2182         }
2183
2184         /* FSync Source selection */
2185         dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2186         dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2187
2188         dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2189
2190         return 0;
2191 }
2192 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2193
2194 /* -----------------------------------------------------------------------------
2195  * Probe and remove
2196  */
2197
2198 /**
2199  * xilinx_dma_chan_remove - Per Channel remove function
2200  * @chan: Driver specific DMA channel
2201  */
2202 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2203 {
2204         /* Disable all interrupts */
2205         dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2206                       XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2207
2208         if (chan->irq > 0)
2209                 free_irq(chan->irq, chan);
2210
2211         tasklet_kill(&chan->tasklet);
2212
2213         list_del(&chan->common.device_node);
2214 }
2215
2216 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2217                             struct clk **tx_clk, struct clk **rx_clk,
2218                             struct clk **sg_clk, struct clk **tmp_clk)
2219 {
2220         int err;
2221
2222         *tmp_clk = NULL;
2223
2224         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2225         if (IS_ERR(*axi_clk)) {
2226                 err = PTR_ERR(*axi_clk);
2227                 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2228                 return err;
2229         }
2230
2231         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2232         if (IS_ERR(*tx_clk))
2233                 *tx_clk = NULL;
2234
2235         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2236         if (IS_ERR(*rx_clk))
2237                 *rx_clk = NULL;
2238
2239         *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2240         if (IS_ERR(*sg_clk))
2241                 *sg_clk = NULL;
2242
2243         err = clk_prepare_enable(*axi_clk);
2244         if (err) {
2245                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2246                 return err;
2247         }
2248
2249         err = clk_prepare_enable(*tx_clk);
2250         if (err) {
2251                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2252                 goto err_disable_axiclk;
2253         }
2254
2255         err = clk_prepare_enable(*rx_clk);
2256         if (err) {
2257                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2258                 goto err_disable_txclk;
2259         }
2260
2261         err = clk_prepare_enable(*sg_clk);
2262         if (err) {
2263                 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2264                 goto err_disable_rxclk;
2265         }
2266
2267         return 0;
2268
2269 err_disable_rxclk:
2270         clk_disable_unprepare(*rx_clk);
2271 err_disable_txclk:
2272         clk_disable_unprepare(*tx_clk);
2273 err_disable_axiclk:
2274         clk_disable_unprepare(*axi_clk);
2275
2276         return err;
2277 }
2278
2279 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2280                             struct clk **dev_clk, struct clk **tmp_clk,
2281                             struct clk **tmp1_clk, struct clk **tmp2_clk)
2282 {
2283         int err;
2284
2285         *tmp_clk = NULL;
2286         *tmp1_clk = NULL;
2287         *tmp2_clk = NULL;
2288
2289         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2290         if (IS_ERR(*axi_clk)) {
2291                 err = PTR_ERR(*axi_clk);
2292                 dev_err(&pdev->dev, "failed to get axi_clk (%d)\n", err);
2293                 return err;
2294         }
2295
2296         *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2297         if (IS_ERR(*dev_clk)) {
2298                 err = PTR_ERR(*dev_clk);
2299                 dev_err(&pdev->dev, "failed to get dev_clk (%d)\n", err);
2300                 return err;
2301         }
2302
2303         err = clk_prepare_enable(*axi_clk);
2304         if (err) {
2305                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2306                 return err;
2307         }
2308
2309         err = clk_prepare_enable(*dev_clk);
2310         if (err) {
2311                 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2312                 goto err_disable_axiclk;
2313         }
2314
2315         return 0;
2316
2317 err_disable_axiclk:
2318         clk_disable_unprepare(*axi_clk);
2319
2320         return err;
2321 }
2322
2323 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2324                             struct clk **tx_clk, struct clk **txs_clk,
2325                             struct clk **rx_clk, struct clk **rxs_clk)
2326 {
2327         int err;
2328
2329         *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2330         if (IS_ERR(*axi_clk)) {
2331                 err = PTR_ERR(*axi_clk);
2332                 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2333                 return err;
2334         }
2335
2336         *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2337         if (IS_ERR(*tx_clk))
2338                 *tx_clk = NULL;
2339
2340         *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2341         if (IS_ERR(*txs_clk))
2342                 *txs_clk = NULL;
2343
2344         *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2345         if (IS_ERR(*rx_clk))
2346                 *rx_clk = NULL;
2347
2348         *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2349         if (IS_ERR(*rxs_clk))
2350                 *rxs_clk = NULL;
2351
2352         err = clk_prepare_enable(*axi_clk);
2353         if (err) {
2354                 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2355                 return err;
2356         }
2357
2358         err = clk_prepare_enable(*tx_clk);
2359         if (err) {
2360                 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2361                 goto err_disable_axiclk;
2362         }
2363
2364         err = clk_prepare_enable(*txs_clk);
2365         if (err) {
2366                 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2367                 goto err_disable_txclk;
2368         }
2369
2370         err = clk_prepare_enable(*rx_clk);
2371         if (err) {
2372                 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2373                 goto err_disable_txsclk;
2374         }
2375
2376         err = clk_prepare_enable(*rxs_clk);
2377         if (err) {
2378                 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2379                 goto err_disable_rxclk;
2380         }
2381
2382         return 0;
2383
2384 err_disable_rxclk:
2385         clk_disable_unprepare(*rx_clk);
2386 err_disable_txsclk:
2387         clk_disable_unprepare(*txs_clk);
2388 err_disable_txclk:
2389         clk_disable_unprepare(*tx_clk);
2390 err_disable_axiclk:
2391         clk_disable_unprepare(*axi_clk);
2392
2393         return err;
2394 }
2395
2396 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2397 {
2398         clk_disable_unprepare(xdev->rxs_clk);
2399         clk_disable_unprepare(xdev->rx_clk);
2400         clk_disable_unprepare(xdev->txs_clk);
2401         clk_disable_unprepare(xdev->tx_clk);
2402         clk_disable_unprepare(xdev->axi_clk);
2403 }
2404
2405 /**
2406  * xilinx_dma_chan_probe - Per Channel Probing
2407  * It get channel features from the device tree entry and
2408  * initialize special channel handling routines
2409  *
2410  * @xdev: Driver specific device structure
2411  * @node: Device node
2412  * @chan_id: DMA Channel id
2413  *
2414  * Return: '0' on success and failure value on error
2415  */
2416 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2417                                   struct device_node *node, int chan_id)
2418 {
2419         struct xilinx_dma_chan *chan;
2420         bool has_dre = false;
2421         u32 value, width;
2422         int err;
2423
2424         /* Allocate and initialize the channel structure */
2425         chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2426         if (!chan)
2427                 return -ENOMEM;
2428
2429         chan->dev = xdev->dev;
2430         chan->xdev = xdev;
2431         chan->has_sg = xdev->has_sg;
2432         chan->desc_pendingcount = 0x0;
2433         chan->ext_addr = xdev->ext_addr;
2434         /* This variable ensures that descriptors are not
2435          * Submitted when dma engine is in progress. This variable is
2436          * Added to avoid polling for a bit in the status register to
2437          * Know dma state in the driver hot path.
2438          */
2439         chan->idle = true;
2440
2441         spin_lock_init(&chan->lock);
2442         INIT_LIST_HEAD(&chan->pending_list);
2443         INIT_LIST_HEAD(&chan->done_list);
2444         INIT_LIST_HEAD(&chan->active_list);
2445         INIT_LIST_HEAD(&chan->free_seg_list);
2446
2447         /* Retrieve the channel properties from the device tree */
2448         has_dre = of_property_read_bool(node, "xlnx,include-dre");
2449
2450         chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2451
2452         err = of_property_read_u32(node, "xlnx,datawidth", &value);
2453         if (err) {
2454                 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2455                 return err;
2456         }
2457         width = value >> 3; /* Convert bits to bytes */
2458
2459         /* If data width is greater than 8 bytes, DRE is not in hw */
2460         if (width > 8)
2461                 has_dre = false;
2462
2463         if (!has_dre)
2464                 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2465
2466         if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2467             of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2468             of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2469                 chan->direction = DMA_MEM_TO_DEV;
2470                 chan->id = chan_id;
2471                 chan->tdest = chan_id;
2472
2473                 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2474                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2475                         chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2476                         chan->config.park = 1;
2477
2478                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2479                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2480                                 chan->flush_on_fsync = true;
2481                 }
2482         } else if (of_device_is_compatible(node,
2483                                            "xlnx,axi-vdma-s2mm-channel") ||
2484                    of_device_is_compatible(node,
2485                                            "xlnx,axi-dma-s2mm-channel")) {
2486                 chan->direction = DMA_DEV_TO_MEM;
2487                 chan->id = chan_id;
2488                 chan->tdest = chan_id - xdev->nr_channels;
2489                 chan->has_vflip = of_property_read_bool(node,
2490                                         "xlnx,enable-vert-flip");
2491                 if (chan->has_vflip) {
2492                         chan->config.vflip_en = dma_read(chan,
2493                                 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2494                                 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2495                 }
2496
2497                 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2498                 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2499                         chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2500                         chan->config.park = 1;
2501
2502                         if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2503                             xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2504                                 chan->flush_on_fsync = true;
2505                 }
2506         } else {
2507                 dev_err(xdev->dev, "Invalid channel compatible node\n");
2508                 return -EINVAL;
2509         }
2510
2511         /* Request the interrupt */
2512         chan->irq = irq_of_parse_and_map(node, 0);
2513         err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
2514                           "xilinx-dma-controller", chan);
2515         if (err) {
2516                 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2517                 return err;
2518         }
2519
2520         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2521                 chan->start_transfer = xilinx_dma_start_transfer;
2522                 chan->stop_transfer = xilinx_dma_stop_transfer;
2523         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2524                 chan->start_transfer = xilinx_cdma_start_transfer;
2525                 chan->stop_transfer = xilinx_cdma_stop_transfer;
2526         } else {
2527                 chan->start_transfer = xilinx_vdma_start_transfer;
2528                 chan->stop_transfer = xilinx_dma_stop_transfer;
2529         }
2530
2531         /* Initialize the tasklet */
2532         tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
2533                         (unsigned long)chan);
2534
2535         /*
2536          * Initialize the DMA channel and add it to the DMA engine channels
2537          * list.
2538          */
2539         chan->common.device = &xdev->common;
2540
2541         list_add_tail(&chan->common.device_node, &xdev->common.channels);
2542         xdev->chan[chan->id] = chan;
2543
2544         /* Reset the channel */
2545         err = xilinx_dma_chan_reset(chan);
2546         if (err < 0) {
2547                 dev_err(xdev->dev, "Reset channel failed\n");
2548                 return err;
2549         }
2550
2551         return 0;
2552 }
2553
2554 /**
2555  * xilinx_dma_child_probe - Per child node probe
2556  * It get number of dma-channels per child node from
2557  * device-tree and initializes all the channels.
2558  *
2559  * @xdev: Driver specific device structure
2560  * @node: Device node
2561  *
2562  * Return: 0 always.
2563  */
2564 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2565                                     struct device_node *node)
2566 {
2567         int ret, i;
2568         u32 nr_channels = 1;
2569
2570         ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2571         if ((ret < 0) && xdev->mcdma)
2572                 dev_warn(xdev->dev, "missing dma-channels property\n");
2573
2574         for (i = 0; i < nr_channels; i++)
2575                 xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
2576
2577         xdev->nr_channels += nr_channels;
2578
2579         return 0;
2580 }
2581
2582 /**
2583  * of_dma_xilinx_xlate - Translation function
2584  * @dma_spec: Pointer to DMA specifier as found in the device tree
2585  * @ofdma: Pointer to DMA controller data
2586  *
2587  * Return: DMA channel pointer on success and NULL on error
2588  */
2589 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2590                                                 struct of_dma *ofdma)
2591 {
2592         struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2593         int chan_id = dma_spec->args[0];
2594
2595         if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
2596                 return NULL;
2597
2598         return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2599 }
2600
2601 static const struct xilinx_dma_config axidma_config = {
2602         .dmatype = XDMA_TYPE_AXIDMA,
2603         .clk_init = axidma_clk_init,
2604 };
2605
2606 static const struct xilinx_dma_config axicdma_config = {
2607         .dmatype = XDMA_TYPE_CDMA,
2608         .clk_init = axicdma_clk_init,
2609 };
2610
2611 static const struct xilinx_dma_config axivdma_config = {
2612         .dmatype = XDMA_TYPE_VDMA,
2613         .clk_init = axivdma_clk_init,
2614 };
2615
2616 static const struct of_device_id xilinx_dma_of_ids[] = {
2617         { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2618         { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2619         { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2620         {}
2621 };
2622 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2623
2624 /**
2625  * xilinx_dma_probe - Driver probe function
2626  * @pdev: Pointer to the platform_device structure
2627  *
2628  * Return: '0' on success and failure value on error
2629  */
2630 static int xilinx_dma_probe(struct platform_device *pdev)
2631 {
2632         int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2633                         struct clk **, struct clk **, struct clk **)
2634                                         = axivdma_clk_init;
2635         struct device_node *node = pdev->dev.of_node;
2636         struct xilinx_dma_device *xdev;
2637         struct device_node *child, *np = pdev->dev.of_node;
2638         struct resource *io;
2639         u32 num_frames, addr_width, len_width;
2640         int i, err;
2641
2642         /* Allocate and initialize the DMA engine structure */
2643         xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
2644         if (!xdev)
2645                 return -ENOMEM;
2646
2647         xdev->dev = &pdev->dev;
2648         if (np) {
2649                 const struct of_device_id *match;
2650
2651                 match = of_match_node(xilinx_dma_of_ids, np);
2652                 if (match && match->data) {
2653                         xdev->dma_config = match->data;
2654                         clk_init = xdev->dma_config->clk_init;
2655                 }
2656         }
2657
2658         err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
2659                        &xdev->rx_clk, &xdev->rxs_clk);
2660         if (err)
2661                 return err;
2662
2663         /* Request and map I/O memory */
2664         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2665         xdev->regs = devm_ioremap_resource(&pdev->dev, io);
2666         if (IS_ERR(xdev->regs)) {
2667                 err = PTR_ERR(xdev->regs);
2668                 goto disable_clks;
2669         }
2670         /* Retrieve the DMA engine properties from the device tree */
2671         xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
2672         xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
2673
2674         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2675                 xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
2676                 if (!of_property_read_u32(node, "xlnx,sg-length-width",
2677                                           &len_width)) {
2678                         if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
2679                             len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
2680                                 dev_warn(xdev->dev,
2681                                          "invalid xlnx,sg-length-width property value. Using default width\n");
2682                         } else {
2683                                 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
2684                                         dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
2685                                 xdev->max_buffer_len =
2686                                         GENMASK(len_width - 1, 0);
2687                         }
2688                 }
2689         }
2690
2691         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2692                 err = of_property_read_u32(node, "xlnx,num-fstores",
2693                                            &num_frames);
2694                 if (err < 0) {
2695                         dev_err(xdev->dev,
2696                                 "missing xlnx,num-fstores property\n");
2697                         goto disable_clks;
2698                 }
2699
2700                 err = of_property_read_u32(node, "xlnx,flush-fsync",
2701                                            &xdev->flush_on_fsync);
2702                 if (err < 0)
2703                         dev_warn(xdev->dev,
2704                                  "missing xlnx,flush-fsync property\n");
2705         }
2706
2707         err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
2708         if (err < 0)
2709                 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
2710
2711         if (addr_width > 32)
2712                 xdev->ext_addr = true;
2713         else
2714                 xdev->ext_addr = false;
2715
2716         /* Set the dma mask bits */
2717         err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
2718         if (err < 0) {
2719                 dev_err(xdev->dev, "DMA mask error %d\n", err);
2720                 goto disable_clks;
2721         }
2722
2723         /* Initialize the DMA engine */
2724         xdev->common.dev = &pdev->dev;
2725
2726         INIT_LIST_HEAD(&xdev->common.channels);
2727         if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
2728                 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
2729                 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
2730         }
2731
2732         xdev->common.device_alloc_chan_resources =
2733                                 xilinx_dma_alloc_chan_resources;
2734         xdev->common.device_free_chan_resources =
2735                                 xilinx_dma_free_chan_resources;
2736         xdev->common.device_terminate_all = xilinx_dma_terminate_all;
2737         xdev->common.device_tx_status = xilinx_dma_tx_status;
2738         xdev->common.device_issue_pending = xilinx_dma_issue_pending;
2739         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2740                 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
2741                 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
2742                 xdev->common.device_prep_dma_cyclic =
2743                                           xilinx_dma_prep_dma_cyclic;
2744                 xdev->common.device_prep_interleaved_dma =
2745                                         xilinx_dma_prep_interleaved;
2746                 /* Residue calculation is supported by only AXI DMA */
2747                 xdev->common.residue_granularity =
2748                                           DMA_RESIDUE_GRANULARITY_SEGMENT;
2749         } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2750                 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
2751                 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
2752         } else {
2753                 xdev->common.device_prep_interleaved_dma =
2754                                 xilinx_vdma_dma_prep_interleaved;
2755         }
2756
2757         platform_set_drvdata(pdev, xdev);
2758
2759         /* Initialize the channels */
2760         for_each_child_of_node(node, child) {
2761                 err = xilinx_dma_child_probe(xdev, child);
2762                 if (err < 0) {
2763                         of_node_put(child);
2764                         goto error;
2765                 }
2766         }
2767
2768         if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2769                 for (i = 0; i < xdev->nr_channels; i++)
2770                         if (xdev->chan[i])
2771                                 xdev->chan[i]->num_frms = num_frames;
2772         }
2773
2774         /* Register the DMA engine with the core */
2775         err = dma_async_device_register(&xdev->common);
2776         if (err) {
2777                 dev_err(xdev->dev, "failed to register the dma device\n");
2778                 goto error;
2779         }
2780
2781         err = of_dma_controller_register(node, of_dma_xilinx_xlate,
2782                                          xdev);
2783         if (err < 0) {
2784                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
2785                 dma_async_device_unregister(&xdev->common);
2786                 goto error;
2787         }
2788
2789         if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
2790                 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
2791         else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
2792                 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
2793         else
2794                 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
2795
2796         return 0;
2797
2798 error:
2799         for (i = 0; i < xdev->nr_channels; i++)
2800                 if (xdev->chan[i])
2801                         xilinx_dma_chan_remove(xdev->chan[i]);
2802 disable_clks:
2803         xdma_disable_allclks(xdev);
2804
2805         return err;
2806 }
2807
2808 /**
2809  * xilinx_dma_remove - Driver remove function
2810  * @pdev: Pointer to the platform_device structure
2811  *
2812  * Return: Always '0'
2813  */
2814 static int xilinx_dma_remove(struct platform_device *pdev)
2815 {
2816         struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
2817         int i;
2818
2819         of_dma_controller_free(pdev->dev.of_node);
2820
2821         dma_async_device_unregister(&xdev->common);
2822
2823         for (i = 0; i < xdev->nr_channels; i++)
2824                 if (xdev->chan[i])
2825                         xilinx_dma_chan_remove(xdev->chan[i]);
2826
2827         xdma_disable_allclks(xdev);
2828
2829         return 0;
2830 }
2831
2832 static struct platform_driver xilinx_vdma_driver = {
2833         .driver = {
2834                 .name = "xilinx-vdma",
2835                 .of_match_table = xilinx_dma_of_ids,
2836         },
2837         .probe = xilinx_dma_probe,
2838         .remove = xilinx_dma_remove,
2839 };
2840
2841 module_platform_driver(xilinx_vdma_driver);
2842
2843 MODULE_AUTHOR("Xilinx, Inc.");
2844 MODULE_DESCRIPTION("Xilinx VDMA driver");
2845 MODULE_LICENSE("GPL v2");