2 * DMA driver for Xilinx Video DMA Engine
4 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
6 * Based on the Freescale DMA driver.
9 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
10 * core that provides high-bandwidth direct memory access between memory
11 * and AXI4-Stream type video target peripherals. The core provides efficient
12 * two dimensional DMA operations with independent asynchronous read (S2MM)
13 * and write (MM2S) channel operation. It can be configured to have either
14 * one channel or two channels. If configured as two channels, one is to
15 * transmit to the video device (MM2S) and another is to receive from the
16 * video device (S2MM). Initialization, status, interrupt and management
17 * registers are accessed through an AXI4-Lite slave interface.
19 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
20 * provides high-bandwidth one dimensional direct memory access between memory
21 * and AXI4-Stream target peripherals. It supports one receive and one
22 * transmit channel, both of them optional at synthesis time.
24 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
25 * Access (DMA) between a memory-mapped source address and a memory-mapped
26 * destination address.
28 * This program is free software: you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License as published by
30 * the Free Software Foundation, either version 2 of the License, or
31 * (at your option) any later version.
34 #include <linux/bitops.h>
35 #include <linux/dmapool.h>
36 #include <linux/dma/xilinx_dma.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
40 #include <linux/iopoll.h>
41 #include <linux/module.h>
42 #include <linux/of_address.h>
43 #include <linux/of_dma.h>
44 #include <linux/of_platform.h>
45 #include <linux/of_irq.h>
46 #include <linux/slab.h>
47 #include <linux/clk.h>
48 #include <linux/io-64-nonatomic-lo-hi.h>
50 #include "../dmaengine.h"
52 /* Register/Descriptor Offsets */
53 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
54 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
55 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
56 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
58 /* Control Registers */
59 #define XILINX_DMA_REG_DMACR 0x0000
60 #define XILINX_DMA_DMACR_DELAY_MAX 0xff
61 #define XILINX_DMA_DMACR_DELAY_SHIFT 24
62 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
63 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
64 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
65 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
66 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
67 #define XILINX_DMA_DMACR_MASTER_SHIFT 8
68 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
69 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
70 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
71 #define XILINX_DMA_DMACR_RESET BIT(2)
72 #define XILINX_DMA_DMACR_CIRC_EN BIT(1)
73 #define XILINX_DMA_DMACR_RUNSTOP BIT(0)
74 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
75 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
76 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
77 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
79 #define XILINX_DMA_REG_DMASR 0x0004
80 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
81 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
82 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
83 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
84 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
85 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
86 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
87 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
88 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
89 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
90 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
91 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
92 #define XILINX_DMA_DMASR_IDLE BIT(1)
93 #define XILINX_DMA_DMASR_HALTED BIT(0)
94 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
95 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
97 #define XILINX_DMA_REG_CURDESC 0x0008
98 #define XILINX_DMA_REG_TAILDESC 0x0010
99 #define XILINX_DMA_REG_REG_INDEX 0x0014
100 #define XILINX_DMA_REG_FRMSTORE 0x0018
101 #define XILINX_DMA_REG_THRESHOLD 0x001c
102 #define XILINX_DMA_REG_FRMPTR_STS 0x0024
103 #define XILINX_DMA_REG_PARK_PTR 0x0028
104 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
105 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
106 #define XILINX_DMA_REG_VDMA_VERSION 0x002c
108 /* Register Direct Mode Registers */
109 #define XILINX_DMA_REG_VSIZE 0x0000
110 #define XILINX_DMA_REG_HSIZE 0x0004
112 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
113 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
114 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
116 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
117 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
119 /* HW specific definitions */
120 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
122 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
123 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
124 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
125 XILINX_DMA_DMASR_ERR_IRQ)
127 #define XILINX_DMA_DMASR_ALL_ERR_MASK \
128 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
129 XILINX_DMA_DMASR_SOF_LATE_ERR | \
130 XILINX_DMA_DMASR_SG_DEC_ERR | \
131 XILINX_DMA_DMASR_SG_SLV_ERR | \
132 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
133 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
134 XILINX_DMA_DMASR_DMA_DEC_ERR | \
135 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
136 XILINX_DMA_DMASR_DMA_INT_ERR)
139 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
140 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
141 * is enabled in the h/w system.
143 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
144 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
145 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
146 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
147 XILINX_DMA_DMASR_DMA_INT_ERR)
149 /* Axi VDMA Flush on Fsync bits */
150 #define XILINX_DMA_FLUSH_S2MM 3
151 #define XILINX_DMA_FLUSH_MM2S 2
152 #define XILINX_DMA_FLUSH_BOTH 1
154 /* Delay loop counter to prevent hardware failure */
155 #define XILINX_DMA_LOOP_COUNT 1000000
157 /* AXI DMA Specific Registers/Offsets */
158 #define XILINX_DMA_REG_SRCDSTADDR 0x18
159 #define XILINX_DMA_REG_BTT 0x28
161 /* AXI DMA Specific Masks/Bit fields */
162 #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0)
163 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
164 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
165 #define XILINX_DMA_CR_COALESCE_SHIFT 16
166 #define XILINX_DMA_BD_SOP BIT(27)
167 #define XILINX_DMA_BD_EOP BIT(26)
168 #define XILINX_DMA_COALESCE_MAX 255
169 #define XILINX_DMA_NUM_APP_WORDS 5
171 /* Multi-Channel DMA Descriptor offsets*/
172 #define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20)
173 #define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20)
175 /* Multi-Channel DMA Masks/Shifts */
176 #define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0)
177 #define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0)
178 #define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19)
179 #define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0)
180 #define XILINX_DMA_BD_STRIDE_SHIFT 0
181 #define XILINX_DMA_BD_VSIZE_SHIFT 19
183 /* AXI CDMA Specific Registers/Offsets */
184 #define XILINX_CDMA_REG_SRCADDR 0x18
185 #define XILINX_CDMA_REG_DSTADDR 0x20
187 /* AXI CDMA Specific Masks */
188 #define XILINX_CDMA_CR_SGMODE BIT(3)
191 * struct xilinx_vdma_desc_hw - Hardware Descriptor
192 * @next_desc: Next Descriptor Pointer @0x00
193 * @pad1: Reserved @0x04
194 * @buf_addr: Buffer address @0x08
195 * @buf_addr_msb: MSB of Buffer address @0x0C
196 * @vsize: Vertical Size @0x10
197 * @hsize: Horizontal Size @0x14
198 * @stride: Number of bytes between the first
199 * pixels of each horizontal line @0x18
201 struct xilinx_vdma_desc_hw {
212 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
213 * @next_desc: Next Descriptor Pointer @0x00
214 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
215 * @buf_addr: Buffer address @0x08
216 * @buf_addr_msb: MSB of Buffer address @0x0C
217 * @pad1: Reserved @0x10
218 * @pad2: Reserved @0x14
219 * @control: Control field @0x18
220 * @status: Status field @0x1C
221 * @app: APP Fields @0x20 - 0x30
223 struct xilinx_axidma_desc_hw {
232 u32 app[XILINX_DMA_NUM_APP_WORDS];
236 * struct xilinx_cdma_desc_hw - Hardware Descriptor
237 * @next_desc: Next Descriptor Pointer @0x00
238 * @next_descmsb: Next Descriptor Pointer MSB @0x04
239 * @src_addr: Source address @0x08
240 * @src_addrmsb: Source address MSB @0x0C
241 * @dest_addr: Destination address @0x10
242 * @dest_addrmsb: Destination address MSB @0x14
243 * @control: Control field @0x18
244 * @status: Status field @0x1C
246 struct xilinx_cdma_desc_hw {
258 * struct xilinx_vdma_tx_segment - Descriptor segment
259 * @hw: Hardware descriptor
260 * @node: Node in the descriptor segments list
261 * @phys: Physical address of segment
263 struct xilinx_vdma_tx_segment {
264 struct xilinx_vdma_desc_hw hw;
265 struct list_head node;
270 * struct xilinx_axidma_tx_segment - Descriptor segment
271 * @hw: Hardware descriptor
272 * @node: Node in the descriptor segments list
273 * @phys: Physical address of segment
275 struct xilinx_axidma_tx_segment {
276 struct xilinx_axidma_desc_hw hw;
277 struct list_head node;
282 * struct xilinx_cdma_tx_segment - Descriptor segment
283 * @hw: Hardware descriptor
284 * @node: Node in the descriptor segments list
285 * @phys: Physical address of segment
287 struct xilinx_cdma_tx_segment {
288 struct xilinx_cdma_desc_hw hw;
289 struct list_head node;
294 * struct xilinx_dma_tx_descriptor - Per Transaction structure
295 * @async_tx: Async transaction descriptor
296 * @segments: TX segments list
297 * @node: Node in the channel descriptors list
298 * @cyclic: Check for cyclic transfers.
300 struct xilinx_dma_tx_descriptor {
301 struct dma_async_tx_descriptor async_tx;
302 struct list_head segments;
303 struct list_head node;
308 * struct xilinx_dma_chan - Driver specific DMA channel structure
309 * @xdev: Driver specific device structure
310 * @ctrl_offset: Control registers offset
311 * @desc_offset: TX descriptor registers offset
312 * @lock: Descriptor operation lock
313 * @pending_list: Descriptors waiting
314 * @active_list: Descriptors ready to submit
315 * @done_list: Complete descriptors
316 * @common: DMA common channel
317 * @desc_pool: Descriptors pool
318 * @dev: The dma device
321 * @direction: Transfer direction
322 * @num_frms: Number of frames
323 * @has_sg: Support scatter transfers
324 * @cyclic: Check for cyclic transfers.
325 * @genlock: Support genlock mode
326 * @err: Channel has errors
327 * @tasklet: Cleanup work after irq
328 * @config: Device configuration info
329 * @flush_on_fsync: Flush on Frame sync
330 * @desc_pendingcount: Descriptor pending count
331 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
332 * @desc_submitcount: Descriptor h/w submitted count
333 * @residue: Residue for AXI DMA
334 * @seg_v: Statically allocated segments base
335 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
336 * @start_transfer: Differentiate b/w DMA IP's transfer
337 * @stop_transfer: Differentiate b/w DMA IP's quiesce
339 struct xilinx_dma_chan {
340 struct xilinx_dma_device *xdev;
344 struct list_head pending_list;
345 struct list_head active_list;
346 struct list_head done_list;
347 struct dma_chan common;
348 struct dma_pool *desc_pool;
352 enum dma_transfer_direction direction;
358 struct tasklet_struct tasklet;
359 struct xilinx_vdma_config config;
361 u32 desc_pendingcount;
363 u32 desc_submitcount;
365 struct xilinx_axidma_tx_segment *seg_v;
366 struct xilinx_axidma_tx_segment *cyclic_seg_v;
367 void (*start_transfer)(struct xilinx_dma_chan *chan);
368 int (*stop_transfer)(struct xilinx_dma_chan *chan);
372 struct xilinx_dma_config {
373 enum xdma_ip_type dmatype;
374 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
375 struct clk **tx_clk, struct clk **txs_clk,
376 struct clk **rx_clk, struct clk **rxs_clk);
380 * struct xilinx_dma_device - DMA device structure
381 * @regs: I/O mapped base address
382 * @dev: Device Structure
383 * @common: DMA device structure
384 * @chan: Driver specific DMA channel
385 * @has_sg: Specifies whether Scatter-Gather is present or not
386 * @mcdma: Specifies whether Multi-Channel is present or not
387 * @flush_on_fsync: Flush on frame sync
388 * @ext_addr: Indicates 64 bit addressing is supported by dma device
389 * @pdev: Platform device structure pointer
390 * @dma_config: DMA config structure
391 * @axi_clk: DMA Axi4-lite interace clock
392 * @tx_clk: DMA mm2s clock
393 * @txs_clk: DMA mm2s stream clock
394 * @rx_clk: DMA s2mm clock
395 * @rxs_clk: DMA s2mm stream clock
396 * @nr_channels: Number of channels DMA device supports
397 * @chan_id: DMA channel identifier
399 struct xilinx_dma_device {
402 struct dma_device common;
403 struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
408 struct platform_device *pdev;
409 const struct xilinx_dma_config *dma_config;
420 #define to_xilinx_chan(chan) \
421 container_of(chan, struct xilinx_dma_chan, common)
422 #define to_dma_tx_descriptor(tx) \
423 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
424 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
425 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
426 val, cond, delay_us, timeout_us)
429 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
431 return ioread32(chan->xdev->regs + reg);
434 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
436 iowrite32(value, chan->xdev->regs + reg);
439 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
442 dma_write(chan, chan->desc_offset + reg, value);
445 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
447 return dma_read(chan, chan->ctrl_offset + reg);
450 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
453 dma_write(chan, chan->ctrl_offset + reg, value);
456 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
459 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
462 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
465 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
469 * vdma_desc_write_64 - 64-bit descriptor write
470 * @chan: Driver specific VDMA channel
471 * @reg: Register to write
472 * @value_lsb: lower address of the descriptor.
473 * @value_msb: upper address of the descriptor.
475 * Since vdma driver is trying to write to a register offset which is not a
476 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
477 * instead of a single 64 bit register write.
479 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
480 u32 value_lsb, u32 value_msb)
482 /* Write the lsb 32 bits*/
483 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
485 /* Write the msb 32 bits */
486 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
489 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
491 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
494 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
498 dma_writeq(chan, reg, addr);
500 dma_ctrl_write(chan, reg, addr);
503 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
504 struct xilinx_axidma_desc_hw *hw,
505 dma_addr_t buf_addr, size_t sg_used,
508 if (chan->ext_addr) {
509 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
510 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
513 hw->buf_addr = buf_addr + sg_used + period_len;
517 /* -----------------------------------------------------------------------------
518 * Descriptors and segments alloc and free
522 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
523 * @chan: Driver specific DMA channel
525 * Return: The allocated segment on success and NULL on failure.
527 static struct xilinx_vdma_tx_segment *
528 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
530 struct xilinx_vdma_tx_segment *segment;
533 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
537 segment->phys = phys;
543 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
544 * @chan: Driver specific DMA channel
546 * Return: The allocated segment on success and NULL on failure.
548 static struct xilinx_cdma_tx_segment *
549 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
551 struct xilinx_cdma_tx_segment *segment;
554 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
558 segment->phys = phys;
564 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
565 * @chan: Driver specific DMA channel
567 * Return: The allocated segment on success and NULL on failure.
569 static struct xilinx_axidma_tx_segment *
570 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
572 struct xilinx_axidma_tx_segment *segment;
575 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
579 segment->phys = phys;
585 * xilinx_dma_free_tx_segment - Free transaction segment
586 * @chan: Driver specific DMA channel
587 * @segment: DMA transaction segment
589 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
590 struct xilinx_axidma_tx_segment *segment)
592 dma_pool_free(chan->desc_pool, segment, segment->phys);
596 * xilinx_cdma_free_tx_segment - Free transaction segment
597 * @chan: Driver specific DMA channel
598 * @segment: DMA transaction segment
600 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
601 struct xilinx_cdma_tx_segment *segment)
603 dma_pool_free(chan->desc_pool, segment, segment->phys);
607 * xilinx_vdma_free_tx_segment - Free transaction segment
608 * @chan: Driver specific DMA channel
609 * @segment: DMA transaction segment
611 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
612 struct xilinx_vdma_tx_segment *segment)
614 dma_pool_free(chan->desc_pool, segment, segment->phys);
618 * xilinx_dma_tx_descriptor - Allocate transaction descriptor
619 * @chan: Driver specific DMA channel
621 * Return: The allocated descriptor on success and NULL on failure.
623 static struct xilinx_dma_tx_descriptor *
624 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
626 struct xilinx_dma_tx_descriptor *desc;
628 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
632 INIT_LIST_HEAD(&desc->segments);
638 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
639 * @chan: Driver specific DMA channel
640 * @desc: DMA transaction descriptor
643 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
644 struct xilinx_dma_tx_descriptor *desc)
646 struct xilinx_vdma_tx_segment *segment, *next;
647 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
648 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
653 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
654 list_for_each_entry_safe(segment, next, &desc->segments, node) {
655 list_del(&segment->node);
656 xilinx_vdma_free_tx_segment(chan, segment);
658 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
659 list_for_each_entry_safe(cdma_segment, cdma_next,
660 &desc->segments, node) {
661 list_del(&cdma_segment->node);
662 xilinx_cdma_free_tx_segment(chan, cdma_segment);
665 list_for_each_entry_safe(axidma_segment, axidma_next,
666 &desc->segments, node) {
667 list_del(&axidma_segment->node);
668 xilinx_dma_free_tx_segment(chan, axidma_segment);
675 /* Required functions */
678 * xilinx_dma_free_desc_list - Free descriptors list
679 * @chan: Driver specific DMA channel
680 * @list: List to parse and delete the descriptor
682 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
683 struct list_head *list)
685 struct xilinx_dma_tx_descriptor *desc, *next;
687 list_for_each_entry_safe(desc, next, list, node) {
688 list_del(&desc->node);
689 xilinx_dma_free_tx_descriptor(chan, desc);
694 * xilinx_dma_free_descriptors - Free channel descriptors
695 * @chan: Driver specific DMA channel
697 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
701 spin_lock_irqsave(&chan->lock, flags);
703 xilinx_dma_free_desc_list(chan, &chan->pending_list);
704 xilinx_dma_free_desc_list(chan, &chan->done_list);
705 xilinx_dma_free_desc_list(chan, &chan->active_list);
707 spin_unlock_irqrestore(&chan->lock, flags);
711 * xilinx_dma_free_chan_resources - Free channel resources
712 * @dchan: DMA channel
714 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
716 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
718 dev_dbg(chan->dev, "Free all channel resources.\n");
720 xilinx_dma_free_descriptors(chan);
721 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
722 xilinx_dma_free_tx_segment(chan, chan->cyclic_seg_v);
723 xilinx_dma_free_tx_segment(chan, chan->seg_v);
725 dma_pool_destroy(chan->desc_pool);
726 chan->desc_pool = NULL;
730 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
731 * @chan: Driver specific dma channel
732 * @desc: dma transaction descriptor
733 * @flags: flags for spin lock
735 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
736 struct xilinx_dma_tx_descriptor *desc,
737 unsigned long *flags)
739 dma_async_tx_callback callback;
740 void *callback_param;
742 callback = desc->async_tx.callback;
743 callback_param = desc->async_tx.callback_param;
745 spin_unlock_irqrestore(&chan->lock, *flags);
746 callback(callback_param);
747 spin_lock_irqsave(&chan->lock, *flags);
752 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
753 * @chan: Driver specific DMA channel
755 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
757 struct xilinx_dma_tx_descriptor *desc, *next;
760 spin_lock_irqsave(&chan->lock, flags);
762 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
763 struct dmaengine_desc_callback cb;
766 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
770 /* Remove from the list of running transactions */
771 list_del(&desc->node);
773 /* Run the link descriptor callback function */
774 dmaengine_desc_get_callback(&desc->async_tx, &cb);
775 if (dmaengine_desc_callback_valid(&cb)) {
776 spin_unlock_irqrestore(&chan->lock, flags);
777 dmaengine_desc_callback_invoke(&cb, NULL);
778 spin_lock_irqsave(&chan->lock, flags);
781 /* Run any dependencies, then free the descriptor */
782 dma_run_dependencies(&desc->async_tx);
783 xilinx_dma_free_tx_descriptor(chan, desc);
786 spin_unlock_irqrestore(&chan->lock, flags);
790 * xilinx_dma_do_tasklet - Schedule completion tasklet
791 * @data: Pointer to the Xilinx DMA channel structure
793 static void xilinx_dma_do_tasklet(unsigned long data)
795 struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
797 xilinx_dma_chan_desc_cleanup(chan);
801 * xilinx_dma_alloc_chan_resources - Allocate channel resources
802 * @dchan: DMA channel
804 * Return: '0' on success and failure value on error
806 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
808 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
810 /* Has this channel already been allocated? */
815 * We need the descriptor to be aligned to 64bytes
816 * for meeting Xilinx VDMA specification requirement.
818 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
819 chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool",
821 sizeof(struct xilinx_axidma_tx_segment),
822 __alignof__(struct xilinx_axidma_tx_segment),
824 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
825 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
827 sizeof(struct xilinx_cdma_tx_segment),
828 __alignof__(struct xilinx_cdma_tx_segment),
831 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
833 sizeof(struct xilinx_vdma_tx_segment),
834 __alignof__(struct xilinx_vdma_tx_segment),
838 if (!chan->desc_pool) {
840 "unable to allocate channel %d descriptor pool\n",
845 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
847 * For AXI DMA case after submitting a pending_list, keep
848 * an extra segment allocated so that the "next descriptor"
849 * pointer on the tail descriptor always points to a
850 * valid descriptor, even when paused after reaching taildesc.
851 * This way, it is possible to issue additional
852 * transfers without halting and restarting the channel.
854 chan->seg_v = xilinx_axidma_alloc_tx_segment(chan);
857 * For cyclic DMA mode we need to program the tail Descriptor
858 * register with a value which is not a part of the BD chain
859 * so allocating a desc segment during channel allocation for
860 * programming tail descriptor.
862 chan->cyclic_seg_v = xilinx_axidma_alloc_tx_segment(chan);
865 dma_cookie_init(dchan);
867 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
868 /* For AXI DMA resetting once channel will reset the
869 * other channel as well so enable the interrupts here.
871 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
872 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
875 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
876 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
877 XILINX_CDMA_CR_SGMODE);
883 * xilinx_dma_tx_status - Get DMA transaction status
884 * @dchan: DMA channel
885 * @cookie: Transaction identifier
886 * @txstate: Transaction state
888 * Return: DMA transaction status
890 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
892 struct dma_tx_state *txstate)
894 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
895 struct xilinx_dma_tx_descriptor *desc;
896 struct xilinx_axidma_tx_segment *segment;
897 struct xilinx_axidma_desc_hw *hw;
902 ret = dma_cookie_status(dchan, cookie, txstate);
903 if (ret == DMA_COMPLETE || !txstate)
906 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
907 spin_lock_irqsave(&chan->lock, flags);
909 desc = list_last_entry(&chan->active_list,
910 struct xilinx_dma_tx_descriptor, node);
912 list_for_each_entry(segment, &desc->segments, node) {
914 residue += (hw->control - hw->status) &
915 XILINX_DMA_MAX_TRANS_LEN;
918 spin_unlock_irqrestore(&chan->lock, flags);
920 chan->residue = residue;
921 dma_set_residue(txstate, chan->residue);
928 * xilinx_dma_is_running - Check if DMA channel is running
929 * @chan: Driver specific DMA channel
931 * Return: '1' if running, '0' if not.
933 static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan)
935 return !(dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
936 XILINX_DMA_DMASR_HALTED) &&
937 (dma_ctrl_read(chan, XILINX_DMA_REG_DMACR) &
938 XILINX_DMA_DMACR_RUNSTOP);
942 * xilinx_dma_is_idle - Check if DMA channel is idle
943 * @chan: Driver specific DMA channel
945 * Return: '1' if idle, '0' if not.
947 static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan)
949 return dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
950 XILINX_DMA_DMASR_IDLE;
954 * xilinx_dma_stop_transfer - Halt DMA channel
955 * @chan: Driver specific DMA channel
957 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
961 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
963 /* Wait for the hardware to halt */
964 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
965 val & XILINX_DMA_DMASR_HALTED, 0,
966 XILINX_DMA_LOOP_COUNT);
970 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
971 * @chan: Driver specific DMA channel
973 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
977 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
978 val & XILINX_DMA_DMASR_IDLE, 0,
979 XILINX_DMA_LOOP_COUNT);
983 * xilinx_dma_start - Start DMA channel
984 * @chan: Driver specific DMA channel
986 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
991 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
993 /* Wait for the hardware to start */
994 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
995 !(val & XILINX_DMA_DMASR_HALTED), 0,
996 XILINX_DMA_LOOP_COUNT);
999 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1000 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1007 * xilinx_vdma_start_transfer - Starts VDMA transfer
1008 * @chan: Driver specific channel struct pointer
1010 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1012 struct xilinx_vdma_config *config = &chan->config;
1013 struct xilinx_dma_tx_descriptor *desc, *tail_desc;
1015 struct xilinx_vdma_tx_segment *tail_segment;
1017 /* This function was invoked with lock held */
1021 if (list_empty(&chan->pending_list))
1024 desc = list_first_entry(&chan->pending_list,
1025 struct xilinx_dma_tx_descriptor, node);
1026 tail_desc = list_last_entry(&chan->pending_list,
1027 struct xilinx_dma_tx_descriptor, node);
1029 tail_segment = list_last_entry(&tail_desc->segments,
1030 struct xilinx_vdma_tx_segment, node);
1032 /* If it is SG mode and hardware is busy, cannot submit */
1033 if (chan->has_sg && xilinx_dma_is_running(chan) &&
1034 !xilinx_dma_is_idle(chan)) {
1035 dev_dbg(chan->dev, "DMA controller still busy\n");
1040 * If hardware is idle, then all descriptors on the running lists are
1041 * done, start new transfers
1044 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1045 desc->async_tx.phys);
1047 /* Configure the hardware using info in the config structure */
1048 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1050 if (config->frm_cnt_en)
1051 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1053 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1055 /* Configure channel to allow number frame buffers */
1056 dma_ctrl_write(chan, XILINX_DMA_REG_FRMSTORE,
1057 chan->desc_pendingcount);
1060 * With SG, start with circular mode, so that BDs can be fetched.
1061 * In direct register mode, if not parking, enable circular mode
1063 if (chan->has_sg || !config->park)
1064 reg |= XILINX_DMA_DMACR_CIRC_EN;
1067 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1069 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1071 if (config->park && (config->park_frm >= 0) &&
1072 (config->park_frm < chan->num_frms)) {
1073 if (chan->direction == DMA_MEM_TO_DEV)
1074 dma_write(chan, XILINX_DMA_REG_PARK_PTR,
1076 XILINX_DMA_PARK_PTR_RD_REF_SHIFT);
1078 dma_write(chan, XILINX_DMA_REG_PARK_PTR,
1080 XILINX_DMA_PARK_PTR_WR_REF_SHIFT);
1083 /* Start the hardware */
1084 xilinx_dma_start(chan);
1089 /* Start the transfer */
1091 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1092 tail_segment->phys);
1094 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1097 if (chan->desc_submitcount < chan->num_frms)
1098 i = chan->desc_submitcount;
1100 list_for_each_entry(segment, &desc->segments, node) {
1102 vdma_desc_write_64(chan,
1103 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1104 segment->hw.buf_addr,
1105 segment->hw.buf_addr_msb);
1107 vdma_desc_write(chan,
1108 XILINX_VDMA_REG_START_ADDRESS(i++),
1109 segment->hw.buf_addr);
1117 /* HW expects these parameters to be same for one transaction */
1118 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1119 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1121 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1124 if (!chan->has_sg) {
1125 list_del(&desc->node);
1126 list_add_tail(&desc->node, &chan->active_list);
1127 chan->desc_submitcount++;
1128 chan->desc_pendingcount--;
1129 if (chan->desc_submitcount == chan->num_frms)
1130 chan->desc_submitcount = 0;
1132 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1133 chan->desc_pendingcount = 0;
1138 * xilinx_cdma_start_transfer - Starts cdma transfer
1139 * @chan: Driver specific channel struct pointer
1141 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1143 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1144 struct xilinx_cdma_tx_segment *tail_segment;
1145 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1150 if (list_empty(&chan->pending_list))
1153 head_desc = list_first_entry(&chan->pending_list,
1154 struct xilinx_dma_tx_descriptor, node);
1155 tail_desc = list_last_entry(&chan->pending_list,
1156 struct xilinx_dma_tx_descriptor, node);
1157 tail_segment = list_last_entry(&tail_desc->segments,
1158 struct xilinx_cdma_tx_segment, node);
1160 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1161 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1162 ctrl_reg |= chan->desc_pendingcount <<
1163 XILINX_DMA_CR_COALESCE_SHIFT;
1164 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1168 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1169 head_desc->async_tx.phys);
1171 /* Update tail ptr register which will start the transfer */
1172 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1173 tail_segment->phys);
1175 /* In simple mode */
1176 struct xilinx_cdma_tx_segment *segment;
1177 struct xilinx_cdma_desc_hw *hw;
1179 segment = list_first_entry(&head_desc->segments,
1180 struct xilinx_cdma_tx_segment,
1185 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
1186 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
1188 /* Start the transfer */
1189 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1190 hw->control & XILINX_DMA_MAX_TRANS_LEN);
1193 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1194 chan->desc_pendingcount = 0;
1198 * xilinx_dma_start_transfer - Starts DMA transfer
1199 * @chan: Driver specific channel struct pointer
1201 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1203 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1204 struct xilinx_axidma_tx_segment *tail_segment, *old_head, *new_head;
1210 if (list_empty(&chan->pending_list))
1213 /* If it is SG mode and hardware is busy, cannot submit */
1214 if (chan->has_sg && xilinx_dma_is_running(chan) &&
1215 !xilinx_dma_is_idle(chan)) {
1216 dev_dbg(chan->dev, "DMA controller still busy\n");
1220 head_desc = list_first_entry(&chan->pending_list,
1221 struct xilinx_dma_tx_descriptor, node);
1222 tail_desc = list_last_entry(&chan->pending_list,
1223 struct xilinx_dma_tx_descriptor, node);
1224 tail_segment = list_last_entry(&tail_desc->segments,
1225 struct xilinx_axidma_tx_segment, node);
1227 if (chan->has_sg && !chan->xdev->mcdma) {
1228 old_head = list_first_entry(&head_desc->segments,
1229 struct xilinx_axidma_tx_segment, node);
1230 new_head = chan->seg_v;
1231 /* Copy Buffer Descriptor fields. */
1232 new_head->hw = old_head->hw;
1234 /* Swap and save new reserve */
1235 list_replace_init(&old_head->node, &new_head->node);
1236 chan->seg_v = old_head;
1238 tail_segment->hw.next_desc = chan->seg_v->phys;
1239 head_desc->async_tx.phys = new_head->phys;
1242 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1244 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1245 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1246 reg |= chan->desc_pendingcount <<
1247 XILINX_DMA_CR_COALESCE_SHIFT;
1248 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1251 if (chan->has_sg && !chan->xdev->mcdma)
1252 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1253 head_desc->async_tx.phys);
1255 if (chan->has_sg && chan->xdev->mcdma) {
1256 if (chan->direction == DMA_MEM_TO_DEV) {
1257 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1258 head_desc->async_tx.phys);
1261 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1262 head_desc->async_tx.phys);
1264 dma_ctrl_write(chan,
1265 XILINX_DMA_MCRX_CDESC(chan->tdest),
1266 head_desc->async_tx.phys);
1271 xilinx_dma_start(chan);
1276 /* Start the transfer */
1277 if (chan->has_sg && !chan->xdev->mcdma) {
1279 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1280 chan->cyclic_seg_v->phys);
1282 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1283 tail_segment->phys);
1284 } else if (chan->has_sg && chan->xdev->mcdma) {
1285 if (chan->direction == DMA_MEM_TO_DEV) {
1286 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1287 tail_segment->phys);
1290 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1291 tail_segment->phys);
1293 dma_ctrl_write(chan,
1294 XILINX_DMA_MCRX_TDESC(chan->tdest),
1295 tail_segment->phys);
1299 struct xilinx_axidma_tx_segment *segment;
1300 struct xilinx_axidma_desc_hw *hw;
1302 segment = list_first_entry(&head_desc->segments,
1303 struct xilinx_axidma_tx_segment,
1307 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
1309 /* Start the transfer */
1310 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1311 hw->control & XILINX_DMA_MAX_TRANS_LEN);
1314 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1315 chan->desc_pendingcount = 0;
1319 * xilinx_dma_issue_pending - Issue pending transactions
1320 * @dchan: DMA channel
1322 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1324 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1325 unsigned long flags;
1327 spin_lock_irqsave(&chan->lock, flags);
1328 chan->start_transfer(chan);
1329 spin_unlock_irqrestore(&chan->lock, flags);
1333 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1334 * @chan : xilinx DMA channel
1338 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1340 struct xilinx_dma_tx_descriptor *desc, *next;
1342 /* This function was invoked with lock held */
1343 if (list_empty(&chan->active_list))
1346 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1347 list_del(&desc->node);
1349 dma_cookie_complete(&desc->async_tx);
1350 list_add_tail(&desc->node, &chan->done_list);
1355 * xilinx_dma_reset - Reset DMA channel
1356 * @chan: Driver specific DMA channel
1358 * Return: '0' on success and failure value on error
1360 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1365 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1367 /* Wait for the hardware to finish reset */
1368 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1369 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1370 XILINX_DMA_LOOP_COUNT);
1373 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1374 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1375 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1385 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1386 * @chan: Driver specific DMA channel
1388 * Return: '0' on success and failure value on error
1390 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1395 err = xilinx_dma_reset(chan);
1399 /* Enable interrupts */
1400 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1401 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1407 * xilinx_dma_irq_handler - DMA Interrupt handler
1409 * @data: Pointer to the Xilinx DMA channel structure
1411 * Return: IRQ_HANDLED/IRQ_NONE
1413 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1415 struct xilinx_dma_chan *chan = data;
1418 /* Read the status and ack the interrupts. */
1419 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1420 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1423 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1424 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1426 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1428 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1429 * error is recoverable, ignore it. Otherwise flag the error.
1431 * Only recoverable errors can be cleared in the DMASR register,
1432 * make sure not to write to other error bits to 1.
1434 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1436 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1437 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1439 if (!chan->flush_on_fsync ||
1440 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1442 "Channel %p has errors %x, cdr %x tdr %x\n",
1444 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1445 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1450 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1452 * Device takes too long to do the transfer when user requires
1455 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1458 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1459 spin_lock(&chan->lock);
1460 xilinx_dma_complete_descriptor(chan);
1461 chan->start_transfer(chan);
1462 spin_unlock(&chan->lock);
1465 tasklet_schedule(&chan->tasklet);
1470 * append_desc_queue - Queuing descriptor
1471 * @chan: Driver specific dma channel
1472 * @desc: dma transaction descriptor
1474 static void append_desc_queue(struct xilinx_dma_chan *chan,
1475 struct xilinx_dma_tx_descriptor *desc)
1477 struct xilinx_vdma_tx_segment *tail_segment;
1478 struct xilinx_dma_tx_descriptor *tail_desc;
1479 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1480 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1482 if (list_empty(&chan->pending_list))
1486 * Add the hardware descriptor to the chain of hardware descriptors
1487 * that already exists in memory.
1489 tail_desc = list_last_entry(&chan->pending_list,
1490 struct xilinx_dma_tx_descriptor, node);
1491 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1492 tail_segment = list_last_entry(&tail_desc->segments,
1493 struct xilinx_vdma_tx_segment,
1495 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1496 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1497 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1498 struct xilinx_cdma_tx_segment,
1500 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1502 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1503 struct xilinx_axidma_tx_segment,
1505 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1509 * Add the software descriptor and all children to the list
1510 * of pending transactions
1513 list_add_tail(&desc->node, &chan->pending_list);
1514 chan->desc_pendingcount++;
1516 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1517 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1518 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1519 chan->desc_pendingcount = chan->num_frms;
1524 * xilinx_dma_tx_submit - Submit DMA transaction
1525 * @tx: Async transaction descriptor
1527 * Return: cookie value on success and failure value on error
1529 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1531 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1532 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1533 dma_cookie_t cookie;
1534 unsigned long flags;
1538 xilinx_dma_free_tx_descriptor(chan, desc);
1544 * If reset fails, need to hard reset the system.
1545 * Channel is no longer functional
1547 err = xilinx_dma_chan_reset(chan);
1552 spin_lock_irqsave(&chan->lock, flags);
1554 cookie = dma_cookie_assign(tx);
1556 /* Put this transaction onto the tail of the pending queue */
1557 append_desc_queue(chan, desc);
1560 chan->cyclic = true;
1562 spin_unlock_irqrestore(&chan->lock, flags);
1568 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1569 * DMA_SLAVE transaction
1570 * @dchan: DMA channel
1571 * @xt: Interleaved template pointer
1572 * @flags: transfer ack flags
1574 * Return: Async transaction descriptor on success and NULL on failure
1576 static struct dma_async_tx_descriptor *
1577 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1578 struct dma_interleaved_template *xt,
1579 unsigned long flags)
1581 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1582 struct xilinx_dma_tx_descriptor *desc;
1583 struct xilinx_vdma_tx_segment *segment, *prev = NULL;
1584 struct xilinx_vdma_desc_hw *hw;
1586 if (!is_slave_direction(xt->dir))
1589 if (!xt->numf || !xt->sgl[0].size)
1592 if (xt->frame_size != 1)
1595 /* Allocate a transaction descriptor. */
1596 desc = xilinx_dma_alloc_tx_descriptor(chan);
1600 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1601 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1602 async_tx_ack(&desc->async_tx);
1604 /* Allocate the link descriptor from DMA pool */
1605 segment = xilinx_vdma_alloc_tx_segment(chan);
1609 /* Fill in the hardware descriptor */
1611 hw->vsize = xt->numf;
1612 hw->hsize = xt->sgl[0].size;
1613 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
1614 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
1615 hw->stride |= chan->config.frm_dly <<
1616 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
1618 if (xt->dir != DMA_MEM_TO_DEV) {
1619 if (chan->ext_addr) {
1620 hw->buf_addr = lower_32_bits(xt->dst_start);
1621 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
1623 hw->buf_addr = xt->dst_start;
1626 if (chan->ext_addr) {
1627 hw->buf_addr = lower_32_bits(xt->src_start);
1628 hw->buf_addr_msb = upper_32_bits(xt->src_start);
1630 hw->buf_addr = xt->src_start;
1634 /* Insert the segment into the descriptor segments list. */
1635 list_add_tail(&segment->node, &desc->segments);
1639 /* Link the last hardware descriptor with the first. */
1640 segment = list_first_entry(&desc->segments,
1641 struct xilinx_vdma_tx_segment, node);
1642 desc->async_tx.phys = segment->phys;
1644 return &desc->async_tx;
1647 xilinx_dma_free_tx_descriptor(chan, desc);
1652 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
1653 * @dchan: DMA channel
1654 * @dma_dst: destination address
1655 * @dma_src: source address
1656 * @len: transfer length
1657 * @flags: transfer ack flags
1659 * Return: Async transaction descriptor on success and NULL on failure
1661 static struct dma_async_tx_descriptor *
1662 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
1663 dma_addr_t dma_src, size_t len, unsigned long flags)
1665 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1666 struct xilinx_dma_tx_descriptor *desc;
1667 struct xilinx_cdma_tx_segment *segment;
1668 struct xilinx_cdma_desc_hw *hw;
1670 if (!len || len > XILINX_DMA_MAX_TRANS_LEN)
1673 desc = xilinx_dma_alloc_tx_descriptor(chan);
1677 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1678 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1680 /* Allocate the link descriptor from DMA pool */
1681 segment = xilinx_cdma_alloc_tx_segment(chan);
1687 hw->src_addr = dma_src;
1688 hw->dest_addr = dma_dst;
1689 if (chan->ext_addr) {
1690 hw->src_addr_msb = upper_32_bits(dma_src);
1691 hw->dest_addr_msb = upper_32_bits(dma_dst);
1694 /* Insert the segment into the descriptor segments list. */
1695 list_add_tail(&segment->node, &desc->segments);
1697 desc->async_tx.phys = segment->phys;
1698 hw->next_desc = segment->phys;
1700 return &desc->async_tx;
1703 xilinx_dma_free_tx_descriptor(chan, desc);
1708 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1709 * @dchan: DMA channel
1710 * @sgl: scatterlist to transfer to/from
1711 * @sg_len: number of entries in @scatterlist
1712 * @direction: DMA direction
1713 * @flags: transfer ack flags
1714 * @context: APP words of the descriptor
1716 * Return: Async transaction descriptor on success and NULL on failure
1718 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
1719 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
1720 enum dma_transfer_direction direction, unsigned long flags,
1723 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1724 struct xilinx_dma_tx_descriptor *desc;
1725 struct xilinx_axidma_tx_segment *segment = NULL, *prev = NULL;
1726 u32 *app_w = (u32 *)context;
1727 struct scatterlist *sg;
1732 if (!is_slave_direction(direction))
1735 /* Allocate a transaction descriptor. */
1736 desc = xilinx_dma_alloc_tx_descriptor(chan);
1740 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1741 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1743 /* Build transactions using information in the scatter gather list */
1744 for_each_sg(sgl, sg, sg_len, i) {
1747 /* Loop until the entire scatterlist entry is used */
1748 while (sg_used < sg_dma_len(sg)) {
1749 struct xilinx_axidma_desc_hw *hw;
1751 /* Get a free segment */
1752 segment = xilinx_axidma_alloc_tx_segment(chan);
1757 * Calculate the maximum number of bytes to transfer,
1758 * making sure it is less than the hw limit
1760 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
1761 XILINX_DMA_MAX_TRANS_LEN);
1764 /* Fill in the descriptor */
1765 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
1770 if (chan->direction == DMA_MEM_TO_DEV) {
1772 memcpy(hw->app, app_w, sizeof(u32) *
1773 XILINX_DMA_NUM_APP_WORDS);
1777 prev->hw.next_desc = segment->phys;
1783 * Insert the segment into the descriptor segments
1786 list_add_tail(&segment->node, &desc->segments);
1790 segment = list_first_entry(&desc->segments,
1791 struct xilinx_axidma_tx_segment, node);
1792 desc->async_tx.phys = segment->phys;
1793 prev->hw.next_desc = segment->phys;
1795 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1796 if (chan->direction == DMA_MEM_TO_DEV) {
1797 segment->hw.control |= XILINX_DMA_BD_SOP;
1798 segment = list_last_entry(&desc->segments,
1799 struct xilinx_axidma_tx_segment,
1801 segment->hw.control |= XILINX_DMA_BD_EOP;
1804 return &desc->async_tx;
1807 xilinx_dma_free_tx_descriptor(chan, desc);
1812 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
1813 * @chan: DMA channel
1814 * @sgl: scatterlist to transfer to/from
1815 * @sg_len: number of entries in @scatterlist
1816 * @direction: DMA direction
1817 * @flags: transfer ack flags
1819 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
1820 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
1821 size_t period_len, enum dma_transfer_direction direction,
1822 unsigned long flags)
1824 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1825 struct xilinx_dma_tx_descriptor *desc;
1826 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
1827 size_t copy, sg_used;
1828 unsigned int num_periods;
1835 num_periods = buf_len / period_len;
1840 if (!is_slave_direction(direction))
1843 /* Allocate a transaction descriptor. */
1844 desc = xilinx_dma_alloc_tx_descriptor(chan);
1848 chan->direction = direction;
1849 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1850 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1852 for (i = 0; i < num_periods; ++i) {
1855 while (sg_used < period_len) {
1856 struct xilinx_axidma_desc_hw *hw;
1858 /* Get a free segment */
1859 segment = xilinx_axidma_alloc_tx_segment(chan);
1864 * Calculate the maximum number of bytes to transfer,
1865 * making sure it is less than the hw limit
1867 copy = min_t(size_t, period_len - sg_used,
1868 XILINX_DMA_MAX_TRANS_LEN);
1870 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
1875 prev->hw.next_desc = segment->phys;
1881 * Insert the segment into the descriptor segments
1884 list_add_tail(&segment->node, &desc->segments);
1888 head_segment = list_first_entry(&desc->segments,
1889 struct xilinx_axidma_tx_segment, node);
1890 desc->async_tx.phys = head_segment->phys;
1892 desc->cyclic = true;
1893 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1894 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
1895 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1897 segment = list_last_entry(&desc->segments,
1898 struct xilinx_axidma_tx_segment,
1900 segment->hw.next_desc = (u32) head_segment->phys;
1902 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1903 if (direction == DMA_MEM_TO_DEV) {
1904 head_segment->hw.control |= XILINX_DMA_BD_SOP;
1905 segment->hw.control |= XILINX_DMA_BD_EOP;
1908 return &desc->async_tx;
1911 xilinx_dma_free_tx_descriptor(chan, desc);
1916 * xilinx_dma_prep_interleaved - prepare a descriptor for a
1917 * DMA_SLAVE transaction
1918 * @dchan: DMA channel
1919 * @xt: Interleaved template pointer
1920 * @flags: transfer ack flags
1922 * Return: Async transaction descriptor on success and NULL on failure
1924 static struct dma_async_tx_descriptor *
1925 xilinx_dma_prep_interleaved(struct dma_chan *dchan,
1926 struct dma_interleaved_template *xt,
1927 unsigned long flags)
1929 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1930 struct xilinx_dma_tx_descriptor *desc;
1931 struct xilinx_axidma_tx_segment *segment;
1932 struct xilinx_axidma_desc_hw *hw;
1934 if (!is_slave_direction(xt->dir))
1937 if (!xt->numf || !xt->sgl[0].size)
1940 if (xt->frame_size != 1)
1943 /* Allocate a transaction descriptor. */
1944 desc = xilinx_dma_alloc_tx_descriptor(chan);
1948 chan->direction = xt->dir;
1949 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1950 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1952 /* Get a free segment */
1953 segment = xilinx_axidma_alloc_tx_segment(chan);
1959 /* Fill in the descriptor */
1960 if (xt->dir != DMA_MEM_TO_DEV)
1961 hw->buf_addr = xt->dst_start;
1963 hw->buf_addr = xt->src_start;
1965 hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
1966 hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
1967 XILINX_DMA_BD_VSIZE_MASK;
1968 hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
1969 XILINX_DMA_BD_STRIDE_MASK;
1970 hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
1973 * Insert the segment into the descriptor segments
1976 list_add_tail(&segment->node, &desc->segments);
1979 segment = list_first_entry(&desc->segments,
1980 struct xilinx_axidma_tx_segment, node);
1981 desc->async_tx.phys = segment->phys;
1983 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1984 if (xt->dir == DMA_MEM_TO_DEV) {
1985 segment->hw.control |= XILINX_DMA_BD_SOP;
1986 segment = list_last_entry(&desc->segments,
1987 struct xilinx_axidma_tx_segment,
1989 segment->hw.control |= XILINX_DMA_BD_EOP;
1992 return &desc->async_tx;
1995 xilinx_dma_free_tx_descriptor(chan, desc);
2000 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2001 * @chan: Driver specific DMA Channel pointer
2003 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2005 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2010 xilinx_dma_chan_reset(chan);
2012 err = chan->stop_transfer(chan);
2014 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2015 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
2019 /* Remove and free all of the descriptors in the lists */
2020 xilinx_dma_free_descriptors(chan);
2023 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2024 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2025 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2026 chan->cyclic = false;
2033 * xilinx_dma_channel_set_config - Configure VDMA channel
2034 * Run-time configuration for Axi VDMA, supports:
2035 * . halt the channel
2036 * . configure interrupt coalescing and inter-packet delay threshold
2037 * . start/stop parking
2040 * @dchan: DMA channel
2041 * @cfg: VDMA device configuration pointer
2043 * Return: '0' on success and failure value on error
2045 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2046 struct xilinx_vdma_config *cfg)
2048 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2052 return xilinx_dma_chan_reset(chan);
2054 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2056 chan->config.frm_dly = cfg->frm_dly;
2057 chan->config.park = cfg->park;
2059 /* genlock settings */
2060 chan->config.gen_lock = cfg->gen_lock;
2061 chan->config.master = cfg->master;
2063 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2064 if (cfg->gen_lock && chan->genlock) {
2065 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2066 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2067 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2070 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2072 chan->config.park_frm = cfg->park_frm;
2074 chan->config.park_frm = -1;
2076 chan->config.coalesc = cfg->coalesc;
2077 chan->config.delay = cfg->delay;
2079 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2080 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2081 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2082 chan->config.coalesc = cfg->coalesc;
2085 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2086 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2087 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2088 chan->config.delay = cfg->delay;
2091 /* FSync Source selection */
2092 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2093 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2095 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2099 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2101 /* -----------------------------------------------------------------------------
2106 * xilinx_dma_chan_remove - Per Channel remove function
2107 * @chan: Driver specific DMA channel
2109 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2111 /* Disable all interrupts */
2112 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2113 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2116 free_irq(chan->irq, chan);
2118 tasklet_kill(&chan->tasklet);
2120 list_del(&chan->common.device_node);
2123 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2124 struct clk **tx_clk, struct clk **rx_clk,
2125 struct clk **sg_clk, struct clk **tmp_clk)
2131 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2132 if (IS_ERR(*axi_clk)) {
2133 err = PTR_ERR(*axi_clk);
2134 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2138 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2139 if (IS_ERR(*tx_clk))
2142 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2143 if (IS_ERR(*rx_clk))
2146 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2147 if (IS_ERR(*sg_clk))
2150 err = clk_prepare_enable(*axi_clk);
2152 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2156 err = clk_prepare_enable(*tx_clk);
2158 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2159 goto err_disable_axiclk;
2162 err = clk_prepare_enable(*rx_clk);
2164 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2165 goto err_disable_txclk;
2168 err = clk_prepare_enable(*sg_clk);
2170 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2171 goto err_disable_rxclk;
2177 clk_disable_unprepare(*rx_clk);
2179 clk_disable_unprepare(*tx_clk);
2181 clk_disable_unprepare(*axi_clk);
2186 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2187 struct clk **dev_clk, struct clk **tmp_clk,
2188 struct clk **tmp1_clk, struct clk **tmp2_clk)
2196 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2197 if (IS_ERR(*axi_clk)) {
2198 err = PTR_ERR(*axi_clk);
2199 dev_err(&pdev->dev, "failed to get axi_clk (%d)\n", err);
2203 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2204 if (IS_ERR(*dev_clk)) {
2205 err = PTR_ERR(*dev_clk);
2206 dev_err(&pdev->dev, "failed to get dev_clk (%d)\n", err);
2210 err = clk_prepare_enable(*axi_clk);
2212 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2216 err = clk_prepare_enable(*dev_clk);
2218 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2219 goto err_disable_axiclk;
2225 clk_disable_unprepare(*axi_clk);
2230 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2231 struct clk **tx_clk, struct clk **txs_clk,
2232 struct clk **rx_clk, struct clk **rxs_clk)
2236 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2237 if (IS_ERR(*axi_clk)) {
2238 err = PTR_ERR(*axi_clk);
2239 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2243 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2244 if (IS_ERR(*tx_clk))
2247 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2248 if (IS_ERR(*txs_clk))
2251 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2252 if (IS_ERR(*rx_clk))
2255 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2256 if (IS_ERR(*rxs_clk))
2259 err = clk_prepare_enable(*axi_clk);
2261 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2265 err = clk_prepare_enable(*tx_clk);
2267 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2268 goto err_disable_axiclk;
2271 err = clk_prepare_enable(*txs_clk);
2273 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2274 goto err_disable_txclk;
2277 err = clk_prepare_enable(*rx_clk);
2279 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2280 goto err_disable_txsclk;
2283 err = clk_prepare_enable(*rxs_clk);
2285 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2286 goto err_disable_rxclk;
2292 clk_disable_unprepare(*rx_clk);
2294 clk_disable_unprepare(*txs_clk);
2296 clk_disable_unprepare(*tx_clk);
2298 clk_disable_unprepare(*axi_clk);
2303 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2305 clk_disable_unprepare(xdev->rxs_clk);
2306 clk_disable_unprepare(xdev->rx_clk);
2307 clk_disable_unprepare(xdev->txs_clk);
2308 clk_disable_unprepare(xdev->tx_clk);
2309 clk_disable_unprepare(xdev->axi_clk);
2313 * xilinx_dma_chan_probe - Per Channel Probing
2314 * It get channel features from the device tree entry and
2315 * initialize special channel handling routines
2317 * @xdev: Driver specific device structure
2318 * @node: Device node
2320 * Return: '0' on success and failure value on error
2322 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2323 struct device_node *node, int chan_id)
2325 struct xilinx_dma_chan *chan;
2326 bool has_dre = false;
2330 /* Allocate and initialize the channel structure */
2331 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2335 chan->dev = xdev->dev;
2337 chan->has_sg = xdev->has_sg;
2338 chan->desc_pendingcount = 0x0;
2339 chan->ext_addr = xdev->ext_addr;
2341 spin_lock_init(&chan->lock);
2342 INIT_LIST_HEAD(&chan->pending_list);
2343 INIT_LIST_HEAD(&chan->done_list);
2344 INIT_LIST_HEAD(&chan->active_list);
2346 /* Retrieve the channel properties from the device tree */
2347 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2349 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2351 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2353 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2356 width = value >> 3; /* Convert bits to bytes */
2358 /* If data width is greater than 8 bytes, DRE is not in hw */
2363 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2365 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2366 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2367 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2368 chan->direction = DMA_MEM_TO_DEV;
2370 chan->tdest = chan_id;
2372 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2373 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2374 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2376 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2377 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2378 chan->flush_on_fsync = true;
2380 } else if (of_device_is_compatible(node,
2381 "xlnx,axi-vdma-s2mm-channel") ||
2382 of_device_is_compatible(node,
2383 "xlnx,axi-dma-s2mm-channel")) {
2384 chan->direction = DMA_DEV_TO_MEM;
2386 chan->tdest = chan_id - xdev->nr_channels;
2388 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2389 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2390 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2392 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2393 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2394 chan->flush_on_fsync = true;
2397 dev_err(xdev->dev, "Invalid channel compatible node\n");
2401 /* Request the interrupt */
2402 chan->irq = irq_of_parse_and_map(node, 0);
2403 err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
2404 "xilinx-dma-controller", chan);
2406 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2410 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2411 chan->start_transfer = xilinx_dma_start_transfer;
2412 chan->stop_transfer = xilinx_dma_stop_transfer;
2413 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2414 chan->start_transfer = xilinx_cdma_start_transfer;
2415 chan->stop_transfer = xilinx_cdma_stop_transfer;
2417 chan->start_transfer = xilinx_vdma_start_transfer;
2418 chan->stop_transfer = xilinx_dma_stop_transfer;
2421 /* Initialize the tasklet */
2422 tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
2423 (unsigned long)chan);
2426 * Initialize the DMA channel and add it to the DMA engine channels
2429 chan->common.device = &xdev->common;
2431 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2432 xdev->chan[chan->id] = chan;
2434 /* Reset the channel */
2435 err = xilinx_dma_chan_reset(chan);
2437 dev_err(xdev->dev, "Reset channel failed\n");
2445 * xilinx_dma_child_probe - Per child node probe
2446 * It get number of dma-channels per child node from
2447 * device-tree and initializes all the channels.
2449 * @xdev: Driver specific device structure
2450 * @node: Device node
2454 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2455 struct device_node *node) {
2456 int ret, i, nr_channels = 1;
2458 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2459 if ((ret < 0) && xdev->mcdma)
2460 dev_warn(xdev->dev, "missing dma-channels property\n");
2462 for (i = 0; i < nr_channels; i++)
2463 xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
2465 xdev->nr_channels += nr_channels;
2471 * of_dma_xilinx_xlate - Translation function
2472 * @dma_spec: Pointer to DMA specifier as found in the device tree
2473 * @ofdma: Pointer to DMA controller data
2475 * Return: DMA channel pointer on success and NULL on error
2477 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2478 struct of_dma *ofdma)
2480 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2481 int chan_id = dma_spec->args[0];
2483 if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
2486 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2489 static const struct xilinx_dma_config axidma_config = {
2490 .dmatype = XDMA_TYPE_AXIDMA,
2491 .clk_init = axidma_clk_init,
2494 static const struct xilinx_dma_config axicdma_config = {
2495 .dmatype = XDMA_TYPE_CDMA,
2496 .clk_init = axicdma_clk_init,
2499 static const struct xilinx_dma_config axivdma_config = {
2500 .dmatype = XDMA_TYPE_VDMA,
2501 .clk_init = axivdma_clk_init,
2504 static const struct of_device_id xilinx_dma_of_ids[] = {
2505 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2506 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2507 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2510 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2513 * xilinx_dma_probe - Driver probe function
2514 * @pdev: Pointer to the platform_device structure
2516 * Return: '0' on success and failure value on error
2518 static int xilinx_dma_probe(struct platform_device *pdev)
2520 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2521 struct clk **, struct clk **, struct clk **)
2523 struct device_node *node = pdev->dev.of_node;
2524 struct xilinx_dma_device *xdev;
2525 struct device_node *child, *np = pdev->dev.of_node;
2526 struct resource *io;
2527 u32 num_frames, addr_width;
2530 /* Allocate and initialize the DMA engine structure */
2531 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
2535 xdev->dev = &pdev->dev;
2537 const struct of_device_id *match;
2539 match = of_match_node(xilinx_dma_of_ids, np);
2540 if (match && match->data) {
2541 xdev->dma_config = match->data;
2542 clk_init = xdev->dma_config->clk_init;
2546 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
2547 &xdev->rx_clk, &xdev->rxs_clk);
2551 /* Request and map I/O memory */
2552 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2553 xdev->regs = devm_ioremap_resource(&pdev->dev, io);
2554 if (IS_ERR(xdev->regs))
2555 return PTR_ERR(xdev->regs);
2557 /* Retrieve the DMA engine properties from the device tree */
2558 xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
2559 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
2560 xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
2562 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2563 err = of_property_read_u32(node, "xlnx,num-fstores",
2567 "missing xlnx,num-fstores property\n");
2571 err = of_property_read_u32(node, "xlnx,flush-fsync",
2572 &xdev->flush_on_fsync);
2575 "missing xlnx,flush-fsync property\n");
2578 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
2580 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
2582 if (addr_width > 32)
2583 xdev->ext_addr = true;
2585 xdev->ext_addr = false;
2587 /* Set the dma mask bits */
2588 dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
2590 /* Initialize the DMA engine */
2591 xdev->common.dev = &pdev->dev;
2593 INIT_LIST_HEAD(&xdev->common.channels);
2594 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
2595 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
2596 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
2599 xdev->common.device_alloc_chan_resources =
2600 xilinx_dma_alloc_chan_resources;
2601 xdev->common.device_free_chan_resources =
2602 xilinx_dma_free_chan_resources;
2603 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
2604 xdev->common.device_tx_status = xilinx_dma_tx_status;
2605 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
2606 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2607 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
2608 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
2609 xdev->common.device_prep_dma_cyclic =
2610 xilinx_dma_prep_dma_cyclic;
2611 xdev->common.device_prep_interleaved_dma =
2612 xilinx_dma_prep_interleaved;
2613 /* Residue calculation is supported by only AXI DMA */
2614 xdev->common.residue_granularity =
2615 DMA_RESIDUE_GRANULARITY_SEGMENT;
2616 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2617 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
2618 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
2620 xdev->common.device_prep_interleaved_dma =
2621 xilinx_vdma_dma_prep_interleaved;
2624 platform_set_drvdata(pdev, xdev);
2626 /* Initialize the channels */
2627 for_each_child_of_node(node, child) {
2628 err = xilinx_dma_child_probe(xdev, child);
2633 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2634 for (i = 0; i < xdev->nr_channels; i++)
2636 xdev->chan[i]->num_frms = num_frames;
2639 /* Register the DMA engine with the core */
2640 err = dma_async_device_register(&xdev->common);
2642 dev_err(xdev->dev, "failed to register the dma device\n");
2646 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
2649 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
2650 dma_async_device_unregister(&xdev->common);
2654 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
2659 xdma_disable_allclks(xdev);
2661 for (i = 0; i < xdev->nr_channels; i++)
2663 xilinx_dma_chan_remove(xdev->chan[i]);
2669 * xilinx_dma_remove - Driver remove function
2670 * @pdev: Pointer to the platform_device structure
2672 * Return: Always '0'
2674 static int xilinx_dma_remove(struct platform_device *pdev)
2676 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
2679 of_dma_controller_free(pdev->dev.of_node);
2681 dma_async_device_unregister(&xdev->common);
2683 for (i = 0; i < xdev->nr_channels; i++)
2685 xilinx_dma_chan_remove(xdev->chan[i]);
2687 xdma_disable_allclks(xdev);
2692 static struct platform_driver xilinx_vdma_driver = {
2694 .name = "xilinx-vdma",
2695 .of_match_table = xilinx_dma_of_ids,
2697 .probe = xilinx_dma_probe,
2698 .remove = xilinx_dma_remove,
2701 module_platform_driver(xilinx_vdma_driver);
2703 MODULE_AUTHOR("Xilinx, Inc.");
2704 MODULE_DESCRIPTION("Xilinx VDMA driver");
2705 MODULE_LICENSE("GPL v2");