1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx Video DMA Engine
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
7 * Based on the Freescale DMA driver.
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
13 * two dimensional DMA operations with independent asynchronous read (S2MM)
14 * and write (MM2S) channel operation. It can be configured to have either
15 * one channel or two channels. If configured as two channels, one is to
16 * transmit to the video device (MM2S) and another is to receive from the
17 * video device (S2MM). Initialization, status, interrupt and management
18 * registers are accessed through an AXI4-Lite slave interface.
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
23 * transmit channel, both of them optional at synthesis time.
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
27 * destination address.
29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
30 * Xilinx IP that provides high-bandwidth direct memory access between
31 * memory and AXI4-Stream target peripherals. It provides scatter gather
32 * (SG) interface with multiple channels independent configuration support.
36 #include <linux/bitops.h>
37 #include <linux/dmapool.h>
38 #include <linux/dma/xilinx_dma.h>
39 #include <linux/init.h>
40 #include <linux/interrupt.h>
42 #include <linux/iopoll.h>
43 #include <linux/module.h>
44 #include <linux/of_address.h>
45 #include <linux/of_dma.h>
46 #include <linux/of_platform.h>
47 #include <linux/of_irq.h>
48 #include <linux/slab.h>
49 #include <linux/clk.h>
50 #include <linux/io-64-nonatomic-lo-hi.h>
52 #include "../dmaengine.h"
54 /* Register/Descriptor Offsets */
55 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
56 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
57 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
58 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
60 /* Control Registers */
61 #define XILINX_DMA_REG_DMACR 0x0000
62 #define XILINX_DMA_DMACR_DELAY_MAX 0xff
63 #define XILINX_DMA_DMACR_DELAY_SHIFT 24
64 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
65 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
66 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
67 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
68 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
69 #define XILINX_DMA_DMACR_MASTER_SHIFT 8
70 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
71 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
72 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
73 #define XILINX_DMA_DMACR_RESET BIT(2)
74 #define XILINX_DMA_DMACR_CIRC_EN BIT(1)
75 #define XILINX_DMA_DMACR_RUNSTOP BIT(0)
76 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
77 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
78 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
79 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
81 #define XILINX_DMA_REG_DMASR 0x0004
82 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
83 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
84 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
85 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
86 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
87 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
88 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
89 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
90 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
91 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
92 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
93 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
94 #define XILINX_DMA_DMASR_SG_MASK BIT(3)
95 #define XILINX_DMA_DMASR_IDLE BIT(1)
96 #define XILINX_DMA_DMASR_HALTED BIT(0)
97 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
98 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
100 #define XILINX_DMA_REG_CURDESC 0x0008
101 #define XILINX_DMA_REG_TAILDESC 0x0010
102 #define XILINX_DMA_REG_REG_INDEX 0x0014
103 #define XILINX_DMA_REG_FRMSTORE 0x0018
104 #define XILINX_DMA_REG_THRESHOLD 0x001c
105 #define XILINX_DMA_REG_FRMPTR_STS 0x0024
106 #define XILINX_DMA_REG_PARK_PTR 0x0028
107 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
108 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)
109 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
110 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)
111 #define XILINX_DMA_REG_VDMA_VERSION 0x002c
113 /* Register Direct Mode Registers */
114 #define XILINX_DMA_REG_VSIZE 0x0000
115 #define XILINX_DMA_REG_HSIZE 0x0004
117 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
118 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
119 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
121 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
122 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
124 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec
125 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0)
127 /* HW specific definitions */
128 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20
129 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2
130 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1
132 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
133 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
134 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
135 XILINX_DMA_DMASR_ERR_IRQ)
137 #define XILINX_DMA_DMASR_ALL_ERR_MASK \
138 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
139 XILINX_DMA_DMASR_SOF_LATE_ERR | \
140 XILINX_DMA_DMASR_SG_DEC_ERR | \
141 XILINX_DMA_DMASR_SG_SLV_ERR | \
142 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
143 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
144 XILINX_DMA_DMASR_DMA_DEC_ERR | \
145 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
146 XILINX_DMA_DMASR_DMA_INT_ERR)
149 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
150 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
151 * is enabled in the h/w system.
153 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
154 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
155 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
156 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
157 XILINX_DMA_DMASR_DMA_INT_ERR)
159 /* Axi VDMA Flush on Fsync bits */
160 #define XILINX_DMA_FLUSH_S2MM 3
161 #define XILINX_DMA_FLUSH_MM2S 2
162 #define XILINX_DMA_FLUSH_BOTH 1
164 /* Delay loop counter to prevent hardware failure */
165 #define XILINX_DMA_LOOP_COUNT 1000000
167 /* AXI DMA Specific Registers/Offsets */
168 #define XILINX_DMA_REG_SRCDSTADDR 0x18
169 #define XILINX_DMA_REG_BTT 0x28
171 /* AXI DMA Specific Masks/Bit fields */
172 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8
173 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23
174 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
175 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
176 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
177 #define XILINX_DMA_CR_COALESCE_SHIFT 16
178 #define XILINX_DMA_BD_SOP BIT(27)
179 #define XILINX_DMA_BD_EOP BIT(26)
180 #define XILINX_DMA_COALESCE_MAX 255
181 #define XILINX_DMA_NUM_DESCS 255
182 #define XILINX_DMA_NUM_APP_WORDS 5
184 /* AXI CDMA Specific Registers/Offsets */
185 #define XILINX_CDMA_REG_SRCADDR 0x18
186 #define XILINX_CDMA_REG_DSTADDR 0x20
188 /* AXI CDMA Specific Masks */
189 #define XILINX_CDMA_CR_SGMODE BIT(3)
191 #define xilinx_prep_dma_addr_t(addr) \
192 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
194 /* AXI MCDMA Specific Registers/Offsets */
195 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000
196 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500
197 #define XILINX_MCDMA_CHEN_OFFSET 0x0008
198 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010
199 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020
200 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028
201 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40)
202 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40)
203 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40)
204 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40)
206 /* AXI MCDMA Specific Masks/Shifts */
207 #define XILINX_MCDMA_COALESCE_SHIFT 16
208 #define XILINX_MCDMA_COALESCE_MAX 24
209 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5)
210 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16)
211 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0)
212 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5)
213 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6)
214 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7)
215 #define XILINX_MCDMA_BD_EOP BIT(30)
216 #define XILINX_MCDMA_BD_SOP BIT(31)
219 * struct xilinx_vdma_desc_hw - Hardware Descriptor
220 * @next_desc: Next Descriptor Pointer @0x00
221 * @pad1: Reserved @0x04
222 * @buf_addr: Buffer address @0x08
223 * @buf_addr_msb: MSB of Buffer address @0x0C
224 * @vsize: Vertical Size @0x10
225 * @hsize: Horizontal Size @0x14
226 * @stride: Number of bytes between the first
227 * pixels of each horizontal line @0x18
229 struct xilinx_vdma_desc_hw {
240 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
241 * @next_desc: Next Descriptor Pointer @0x00
242 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
243 * @buf_addr: Buffer address @0x08
244 * @buf_addr_msb: MSB of Buffer address @0x0C
245 * @reserved1: Reserved @0x10
246 * @reserved2: Reserved @0x14
247 * @control: Control field @0x18
248 * @status: Status field @0x1C
249 * @app: APP Fields @0x20 - 0x30
251 struct xilinx_axidma_desc_hw {
260 u32 app[XILINX_DMA_NUM_APP_WORDS];
264 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
265 * @next_desc: Next Descriptor Pointer @0x00
266 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
267 * @buf_addr: Buffer address @0x08
268 * @buf_addr_msb: MSB of Buffer address @0x0C
269 * @rsvd: Reserved field @0x10
270 * @control: Control Information field @0x14
271 * @status: Status field @0x18
272 * @sideband_status: Status of sideband signals @0x1C
273 * @app: APP Fields @0x20 - 0x30
275 struct xilinx_aximcdma_desc_hw {
284 u32 app[XILINX_DMA_NUM_APP_WORDS];
288 * struct xilinx_cdma_desc_hw - Hardware Descriptor
289 * @next_desc: Next Descriptor Pointer @0x00
290 * @next_desc_msb: Next Descriptor Pointer MSB @0x04
291 * @src_addr: Source address @0x08
292 * @src_addr_msb: Source address MSB @0x0C
293 * @dest_addr: Destination address @0x10
294 * @dest_addr_msb: Destination address MSB @0x14
295 * @control: Control field @0x18
296 * @status: Status field @0x1C
298 struct xilinx_cdma_desc_hw {
310 * struct xilinx_vdma_tx_segment - Descriptor segment
311 * @hw: Hardware descriptor
312 * @node: Node in the descriptor segments list
313 * @phys: Physical address of segment
315 struct xilinx_vdma_tx_segment {
316 struct xilinx_vdma_desc_hw hw;
317 struct list_head node;
322 * struct xilinx_axidma_tx_segment - Descriptor segment
323 * @hw: Hardware descriptor
324 * @node: Node in the descriptor segments list
325 * @phys: Physical address of segment
327 struct xilinx_axidma_tx_segment {
328 struct xilinx_axidma_desc_hw hw;
329 struct list_head node;
334 * struct xilinx_aximcdma_tx_segment - Descriptor segment
335 * @hw: Hardware descriptor
336 * @node: Node in the descriptor segments list
337 * @phys: Physical address of segment
339 struct xilinx_aximcdma_tx_segment {
340 struct xilinx_aximcdma_desc_hw hw;
341 struct list_head node;
346 * struct xilinx_cdma_tx_segment - Descriptor segment
347 * @hw: Hardware descriptor
348 * @node: Node in the descriptor segments list
349 * @phys: Physical address of segment
351 struct xilinx_cdma_tx_segment {
352 struct xilinx_cdma_desc_hw hw;
353 struct list_head node;
358 * struct xilinx_dma_tx_descriptor - Per Transaction structure
359 * @async_tx: Async transaction descriptor
360 * @segments: TX segments list
361 * @node: Node in the channel descriptors list
362 * @cyclic: Check for cyclic transfers.
363 * @err: Whether the descriptor has an error.
364 * @residue: Residue of the completed descriptor
366 struct xilinx_dma_tx_descriptor {
367 struct dma_async_tx_descriptor async_tx;
368 struct list_head segments;
369 struct list_head node;
376 * struct xilinx_dma_chan - Driver specific DMA channel structure
377 * @xdev: Driver specific device structure
378 * @ctrl_offset: Control registers offset
379 * @desc_offset: TX descriptor registers offset
380 * @lock: Descriptor operation lock
381 * @pending_list: Descriptors waiting
382 * @active_list: Descriptors ready to submit
383 * @done_list: Complete descriptors
384 * @free_seg_list: Free descriptors
385 * @common: DMA common channel
386 * @desc_pool: Descriptors pool
387 * @dev: The dma device
390 * @direction: Transfer direction
391 * @num_frms: Number of frames
392 * @has_sg: Support scatter transfers
393 * @cyclic: Check for cyclic transfers.
394 * @genlock: Support genlock mode
395 * @err: Channel has errors
396 * @idle: Check for channel idle
397 * @terminating: Check for channel being synchronized by user
398 * @tasklet: Cleanup work after irq
399 * @config: Device configuration info
400 * @flush_on_fsync: Flush on Frame sync
401 * @desc_pendingcount: Descriptor pending count
402 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
403 * @desc_submitcount: Descriptor h/w submitted count
404 * @seg_v: Statically allocated segments base
405 * @seg_mv: Statically allocated segments base for MCDMA
406 * @seg_p: Physical allocated segments base
407 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
408 * @cyclic_seg_p: Physical allocated segments base for cyclic dma
409 * @start_transfer: Differentiate b/w DMA IP's transfer
410 * @stop_transfer: Differentiate b/w DMA IP's quiesce
411 * @tdest: TDEST value for mcdma
412 * @has_vflip: S2MM vertical flip
414 struct xilinx_dma_chan {
415 struct xilinx_dma_device *xdev;
419 struct list_head pending_list;
420 struct list_head active_list;
421 struct list_head done_list;
422 struct list_head free_seg_list;
423 struct dma_chan common;
424 struct dma_pool *desc_pool;
428 enum dma_transfer_direction direction;
436 struct tasklet_struct tasklet;
437 struct xilinx_vdma_config config;
439 u32 desc_pendingcount;
441 u32 desc_submitcount;
442 struct xilinx_axidma_tx_segment *seg_v;
443 struct xilinx_aximcdma_tx_segment *seg_mv;
445 struct xilinx_axidma_tx_segment *cyclic_seg_v;
446 dma_addr_t cyclic_seg_p;
447 void (*start_transfer)(struct xilinx_dma_chan *chan);
448 int (*stop_transfer)(struct xilinx_dma_chan *chan);
454 * enum xdma_ip_type - DMA IP type.
456 * @XDMA_TYPE_AXIDMA: Axi dma ip.
457 * @XDMA_TYPE_CDMA: Axi cdma ip.
458 * @XDMA_TYPE_VDMA: Axi vdma ip.
459 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
463 XDMA_TYPE_AXIDMA = 0,
469 struct xilinx_dma_config {
470 enum xdma_ip_type dmatype;
471 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
472 struct clk **tx_clk, struct clk **txs_clk,
473 struct clk **rx_clk, struct clk **rxs_clk);
474 irqreturn_t (*irq_handler)(int irq, void *data);
475 const int max_channels;
479 * struct xilinx_dma_device - DMA device structure
480 * @regs: I/O mapped base address
481 * @dev: Device Structure
482 * @common: DMA device structure
483 * @chan: Driver specific DMA channel
484 * @flush_on_fsync: Flush on frame sync
485 * @ext_addr: Indicates 64 bit addressing is supported by dma device
486 * @pdev: Platform device structure pointer
487 * @dma_config: DMA config structure
488 * @axi_clk: DMA Axi4-lite interace clock
489 * @tx_clk: DMA mm2s clock
490 * @txs_clk: DMA mm2s stream clock
491 * @rx_clk: DMA s2mm clock
492 * @rxs_clk: DMA s2mm stream clock
493 * @s2mm_chan_id: DMA s2mm channel identifier
494 * @mm2s_chan_id: DMA mm2s channel identifier
495 * @max_buffer_len: Max buffer length
497 struct xilinx_dma_device {
500 struct dma_device common;
501 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
504 struct platform_device *pdev;
505 const struct xilinx_dma_config *dma_config;
517 #define to_xilinx_chan(chan) \
518 container_of(chan, struct xilinx_dma_chan, common)
519 #define to_dma_tx_descriptor(tx) \
520 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
521 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
522 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
523 val, cond, delay_us, timeout_us)
526 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
528 return ioread32(chan->xdev->regs + reg);
531 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
533 iowrite32(value, chan->xdev->regs + reg);
536 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
539 dma_write(chan, chan->desc_offset + reg, value);
542 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
544 return dma_read(chan, chan->ctrl_offset + reg);
547 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
550 dma_write(chan, chan->ctrl_offset + reg, value);
553 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
556 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
559 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
562 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
566 * vdma_desc_write_64 - 64-bit descriptor write
567 * @chan: Driver specific VDMA channel
568 * @reg: Register to write
569 * @value_lsb: lower address of the descriptor.
570 * @value_msb: upper address of the descriptor.
572 * Since vdma driver is trying to write to a register offset which is not a
573 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
574 * instead of a single 64 bit register write.
576 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
577 u32 value_lsb, u32 value_msb)
579 /* Write the lsb 32 bits*/
580 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
582 /* Write the msb 32 bits */
583 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
586 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
588 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
591 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
595 dma_writeq(chan, reg, addr);
597 dma_ctrl_write(chan, reg, addr);
600 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
601 struct xilinx_axidma_desc_hw *hw,
602 dma_addr_t buf_addr, size_t sg_used,
605 if (chan->ext_addr) {
606 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
607 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
610 hw->buf_addr = buf_addr + sg_used + period_len;
614 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
615 struct xilinx_aximcdma_desc_hw *hw,
616 dma_addr_t buf_addr, size_t sg_used)
618 if (chan->ext_addr) {
619 hw->buf_addr = lower_32_bits(buf_addr + sg_used);
620 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used);
622 hw->buf_addr = buf_addr + sg_used;
626 /* -----------------------------------------------------------------------------
627 * Descriptors and segments alloc and free
631 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
632 * @chan: Driver specific DMA channel
634 * Return: The allocated segment on success and NULL on failure.
636 static struct xilinx_vdma_tx_segment *
637 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
639 struct xilinx_vdma_tx_segment *segment;
642 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
646 segment->phys = phys;
652 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
653 * @chan: Driver specific DMA channel
655 * Return: The allocated segment on success and NULL on failure.
657 static struct xilinx_cdma_tx_segment *
658 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
660 struct xilinx_cdma_tx_segment *segment;
663 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
667 segment->phys = phys;
673 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
674 * @chan: Driver specific DMA channel
676 * Return: The allocated segment on success and NULL on failure.
678 static struct xilinx_axidma_tx_segment *
679 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
681 struct xilinx_axidma_tx_segment *segment = NULL;
684 spin_lock_irqsave(&chan->lock, flags);
685 if (!list_empty(&chan->free_seg_list)) {
686 segment = list_first_entry(&chan->free_seg_list,
687 struct xilinx_axidma_tx_segment,
689 list_del(&segment->node);
691 spin_unlock_irqrestore(&chan->lock, flags);
694 dev_dbg(chan->dev, "Could not find free tx segment\n");
700 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
701 * @chan: Driver specific DMA channel
703 * Return: The allocated segment on success and NULL on failure.
705 static struct xilinx_aximcdma_tx_segment *
706 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
708 struct xilinx_aximcdma_tx_segment *segment = NULL;
711 spin_lock_irqsave(&chan->lock, flags);
712 if (!list_empty(&chan->free_seg_list)) {
713 segment = list_first_entry(&chan->free_seg_list,
714 struct xilinx_aximcdma_tx_segment,
716 list_del(&segment->node);
718 spin_unlock_irqrestore(&chan->lock, flags);
723 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
725 u32 next_desc = hw->next_desc;
726 u32 next_desc_msb = hw->next_desc_msb;
728 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
730 hw->next_desc = next_desc;
731 hw->next_desc_msb = next_desc_msb;
734 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
736 u32 next_desc = hw->next_desc;
737 u32 next_desc_msb = hw->next_desc_msb;
739 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw));
741 hw->next_desc = next_desc;
742 hw->next_desc_msb = next_desc_msb;
746 * xilinx_dma_free_tx_segment - Free transaction segment
747 * @chan: Driver specific DMA channel
748 * @segment: DMA transaction segment
750 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
751 struct xilinx_axidma_tx_segment *segment)
753 xilinx_dma_clean_hw_desc(&segment->hw);
755 list_add_tail(&segment->node, &chan->free_seg_list);
759 * xilinx_mcdma_free_tx_segment - Free transaction segment
760 * @chan: Driver specific DMA channel
761 * @segment: DMA transaction segment
763 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
764 struct xilinx_aximcdma_tx_segment *
767 xilinx_mcdma_clean_hw_desc(&segment->hw);
769 list_add_tail(&segment->node, &chan->free_seg_list);
773 * xilinx_cdma_free_tx_segment - Free transaction segment
774 * @chan: Driver specific DMA channel
775 * @segment: DMA transaction segment
777 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
778 struct xilinx_cdma_tx_segment *segment)
780 dma_pool_free(chan->desc_pool, segment, segment->phys);
784 * xilinx_vdma_free_tx_segment - Free transaction segment
785 * @chan: Driver specific DMA channel
786 * @segment: DMA transaction segment
788 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
789 struct xilinx_vdma_tx_segment *segment)
791 dma_pool_free(chan->desc_pool, segment, segment->phys);
795 * xilinx_dma_tx_descriptor - Allocate transaction descriptor
796 * @chan: Driver specific DMA channel
798 * Return: The allocated descriptor on success and NULL on failure.
800 static struct xilinx_dma_tx_descriptor *
801 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
803 struct xilinx_dma_tx_descriptor *desc;
805 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
809 INIT_LIST_HEAD(&desc->segments);
815 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
816 * @chan: Driver specific DMA channel
817 * @desc: DMA transaction descriptor
820 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
821 struct xilinx_dma_tx_descriptor *desc)
823 struct xilinx_vdma_tx_segment *segment, *next;
824 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
825 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
826 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next;
831 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
832 list_for_each_entry_safe(segment, next, &desc->segments, node) {
833 list_del(&segment->node);
834 xilinx_vdma_free_tx_segment(chan, segment);
836 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
837 list_for_each_entry_safe(cdma_segment, cdma_next,
838 &desc->segments, node) {
839 list_del(&cdma_segment->node);
840 xilinx_cdma_free_tx_segment(chan, cdma_segment);
842 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
843 list_for_each_entry_safe(axidma_segment, axidma_next,
844 &desc->segments, node) {
845 list_del(&axidma_segment->node);
846 xilinx_dma_free_tx_segment(chan, axidma_segment);
849 list_for_each_entry_safe(aximcdma_segment, aximcdma_next,
850 &desc->segments, node) {
851 list_del(&aximcdma_segment->node);
852 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
859 /* Required functions */
862 * xilinx_dma_free_desc_list - Free descriptors list
863 * @chan: Driver specific DMA channel
864 * @list: List to parse and delete the descriptor
866 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
867 struct list_head *list)
869 struct xilinx_dma_tx_descriptor *desc, *next;
871 list_for_each_entry_safe(desc, next, list, node) {
872 list_del(&desc->node);
873 xilinx_dma_free_tx_descriptor(chan, desc);
878 * xilinx_dma_free_descriptors - Free channel descriptors
879 * @chan: Driver specific DMA channel
881 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
885 spin_lock_irqsave(&chan->lock, flags);
887 xilinx_dma_free_desc_list(chan, &chan->pending_list);
888 xilinx_dma_free_desc_list(chan, &chan->done_list);
889 xilinx_dma_free_desc_list(chan, &chan->active_list);
891 spin_unlock_irqrestore(&chan->lock, flags);
895 * xilinx_dma_free_chan_resources - Free channel resources
896 * @dchan: DMA channel
898 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
900 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
903 dev_dbg(chan->dev, "Free all channel resources.\n");
905 xilinx_dma_free_descriptors(chan);
907 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
908 spin_lock_irqsave(&chan->lock, flags);
909 INIT_LIST_HEAD(&chan->free_seg_list);
910 spin_unlock_irqrestore(&chan->lock, flags);
912 /* Free memory that is allocated for BD */
913 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
914 XILINX_DMA_NUM_DESCS, chan->seg_v,
917 /* Free Memory that is allocated for cyclic DMA Mode */
918 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
919 chan->cyclic_seg_v, chan->cyclic_seg_p);
922 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
923 spin_lock_irqsave(&chan->lock, flags);
924 INIT_LIST_HEAD(&chan->free_seg_list);
925 spin_unlock_irqrestore(&chan->lock, flags);
927 /* Free memory that is allocated for BD */
928 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
929 XILINX_DMA_NUM_DESCS, chan->seg_mv,
933 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
934 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
935 dma_pool_destroy(chan->desc_pool);
936 chan->desc_pool = NULL;
942 * xilinx_dma_get_residue - Compute residue for a given descriptor
943 * @chan: Driver specific dma channel
944 * @desc: dma transaction descriptor
946 * Return: The number of residue bytes for the descriptor.
948 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
949 struct xilinx_dma_tx_descriptor *desc)
951 struct xilinx_cdma_tx_segment *cdma_seg;
952 struct xilinx_axidma_tx_segment *axidma_seg;
953 struct xilinx_aximcdma_tx_segment *aximcdma_seg;
954 struct xilinx_cdma_desc_hw *cdma_hw;
955 struct xilinx_axidma_desc_hw *axidma_hw;
956 struct xilinx_aximcdma_desc_hw *aximcdma_hw;
957 struct list_head *entry;
960 list_for_each(entry, &desc->segments) {
961 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
962 cdma_seg = list_entry(entry,
963 struct xilinx_cdma_tx_segment,
965 cdma_hw = &cdma_seg->hw;
966 residue += (cdma_hw->control - cdma_hw->status) &
967 chan->xdev->max_buffer_len;
968 } else if (chan->xdev->dma_config->dmatype ==
970 axidma_seg = list_entry(entry,
971 struct xilinx_axidma_tx_segment,
973 axidma_hw = &axidma_seg->hw;
974 residue += (axidma_hw->control - axidma_hw->status) &
975 chan->xdev->max_buffer_len;
979 struct xilinx_aximcdma_tx_segment,
981 aximcdma_hw = &aximcdma_seg->hw;
983 (aximcdma_hw->control - aximcdma_hw->status) &
984 chan->xdev->max_buffer_len;
992 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
993 * @chan: Driver specific dma channel
994 * @desc: dma transaction descriptor
995 * @flags: flags for spin lock
997 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
998 struct xilinx_dma_tx_descriptor *desc,
999 unsigned long *flags)
1001 dma_async_tx_callback callback;
1002 void *callback_param;
1004 callback = desc->async_tx.callback;
1005 callback_param = desc->async_tx.callback_param;
1007 spin_unlock_irqrestore(&chan->lock, *flags);
1008 callback(callback_param);
1009 spin_lock_irqsave(&chan->lock, *flags);
1014 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1015 * @chan: Driver specific DMA channel
1017 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1019 struct xilinx_dma_tx_descriptor *desc, *next;
1020 unsigned long flags;
1022 spin_lock_irqsave(&chan->lock, flags);
1024 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1025 struct dmaengine_result result;
1028 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1032 /* Remove from the list of running transactions */
1033 list_del(&desc->node);
1035 if (unlikely(desc->err)) {
1036 if (chan->direction == DMA_DEV_TO_MEM)
1037 result.result = DMA_TRANS_READ_FAILED;
1039 result.result = DMA_TRANS_WRITE_FAILED;
1041 result.result = DMA_TRANS_NOERROR;
1044 result.residue = desc->residue;
1046 /* Run the link descriptor callback function */
1047 spin_unlock_irqrestore(&chan->lock, flags);
1048 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
1049 spin_lock_irqsave(&chan->lock, flags);
1051 /* Run any dependencies, then free the descriptor */
1052 dma_run_dependencies(&desc->async_tx);
1053 xilinx_dma_free_tx_descriptor(chan, desc);
1056 * While we ran a callback the user called a terminate function,
1057 * which takes care of cleaning up any remaining descriptors
1059 if (chan->terminating)
1063 spin_unlock_irqrestore(&chan->lock, flags);
1067 * xilinx_dma_do_tasklet - Schedule completion tasklet
1068 * @t: Pointer to the Xilinx DMA channel structure
1070 static void xilinx_dma_do_tasklet(struct tasklet_struct *t)
1072 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1074 xilinx_dma_chan_desc_cleanup(chan);
1078 * xilinx_dma_alloc_chan_resources - Allocate channel resources
1079 * @dchan: DMA channel
1081 * Return: '0' on success and failure value on error
1083 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
1085 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1088 /* Has this channel already been allocated? */
1089 if (chan->desc_pool)
1093 * We need the descriptor to be aligned to 64bytes
1094 * for meeting Xilinx VDMA specification requirement.
1096 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1097 /* Allocate the buffer descriptors. */
1098 chan->seg_v = dma_alloc_coherent(chan->dev,
1099 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1100 &chan->seg_p, GFP_KERNEL);
1103 "unable to allocate channel %d descriptors\n",
1108 * For cyclic DMA mode we need to program the tail Descriptor
1109 * register with a value which is not a part of the BD chain
1110 * so allocating a desc segment during channel allocation for
1111 * programming tail descriptor.
1113 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1114 sizeof(*chan->cyclic_seg_v),
1115 &chan->cyclic_seg_p,
1117 if (!chan->cyclic_seg_v) {
1119 "unable to allocate desc segment for cyclic DMA\n");
1120 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1121 XILINX_DMA_NUM_DESCS, chan->seg_v,
1125 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1127 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1128 chan->seg_v[i].hw.next_desc =
1129 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1130 ((i + 1) % XILINX_DMA_NUM_DESCS));
1131 chan->seg_v[i].hw.next_desc_msb =
1132 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1133 ((i + 1) % XILINX_DMA_NUM_DESCS));
1134 chan->seg_v[i].phys = chan->seg_p +
1135 sizeof(*chan->seg_v) * i;
1136 list_add_tail(&chan->seg_v[i].node,
1137 &chan->free_seg_list);
1139 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1140 /* Allocate the buffer descriptors. */
1141 chan->seg_mv = dma_alloc_coherent(chan->dev,
1142 sizeof(*chan->seg_mv) *
1143 XILINX_DMA_NUM_DESCS,
1144 &chan->seg_p, GFP_KERNEL);
1145 if (!chan->seg_mv) {
1147 "unable to allocate channel %d descriptors\n",
1151 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1152 chan->seg_mv[i].hw.next_desc =
1153 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1154 ((i + 1) % XILINX_DMA_NUM_DESCS));
1155 chan->seg_mv[i].hw.next_desc_msb =
1156 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1157 ((i + 1) % XILINX_DMA_NUM_DESCS));
1158 chan->seg_mv[i].phys = chan->seg_p +
1159 sizeof(*chan->seg_mv) * i;
1160 list_add_tail(&chan->seg_mv[i].node,
1161 &chan->free_seg_list);
1163 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1164 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1166 sizeof(struct xilinx_cdma_tx_segment),
1167 __alignof__(struct xilinx_cdma_tx_segment),
1170 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1172 sizeof(struct xilinx_vdma_tx_segment),
1173 __alignof__(struct xilinx_vdma_tx_segment),
1177 if (!chan->desc_pool &&
1178 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1179 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1181 "unable to allocate channel %d descriptor pool\n",
1186 dma_cookie_init(dchan);
1188 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1189 /* For AXI DMA resetting once channel will reset the
1190 * other channel as well so enable the interrupts here.
1192 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1193 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1196 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1197 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1198 XILINX_CDMA_CR_SGMODE);
1204 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1205 * @chan: Driver specific DMA channel
1206 * @size: Total data that needs to be copied
1207 * @done: Amount of data that has been already copied
1209 * Return: Amount of data that has to be copied
1211 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1216 copy = min_t(size_t, size - done,
1217 chan->xdev->max_buffer_len);
1219 if ((copy + done < size) &&
1220 chan->xdev->common.copy_align) {
1222 * If this is not the last descriptor, make sure
1223 * the next one will be properly aligned
1225 copy = rounddown(copy,
1226 (1 << chan->xdev->common.copy_align));
1232 * xilinx_dma_tx_status - Get DMA transaction status
1233 * @dchan: DMA channel
1234 * @cookie: Transaction identifier
1235 * @txstate: Transaction state
1237 * Return: DMA transaction status
1239 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1240 dma_cookie_t cookie,
1241 struct dma_tx_state *txstate)
1243 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1244 struct xilinx_dma_tx_descriptor *desc;
1245 enum dma_status ret;
1246 unsigned long flags;
1249 ret = dma_cookie_status(dchan, cookie, txstate);
1250 if (ret == DMA_COMPLETE || !txstate)
1253 spin_lock_irqsave(&chan->lock, flags);
1254 if (!list_empty(&chan->active_list)) {
1255 desc = list_last_entry(&chan->active_list,
1256 struct xilinx_dma_tx_descriptor, node);
1258 * VDMA and simple mode do not support residue reporting, so the
1259 * residue field will always be 0.
1261 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1262 residue = xilinx_dma_get_residue(chan, desc);
1264 spin_unlock_irqrestore(&chan->lock, flags);
1266 dma_set_residue(txstate, residue);
1272 * xilinx_dma_stop_transfer - Halt DMA channel
1273 * @chan: Driver specific DMA channel
1275 * Return: '0' on success and failure value on error
1277 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1281 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1283 /* Wait for the hardware to halt */
1284 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1285 val & XILINX_DMA_DMASR_HALTED, 0,
1286 XILINX_DMA_LOOP_COUNT);
1290 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1291 * @chan: Driver specific DMA channel
1293 * Return: '0' on success and failure value on error
1295 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1299 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1300 val & XILINX_DMA_DMASR_IDLE, 0,
1301 XILINX_DMA_LOOP_COUNT);
1305 * xilinx_dma_start - Start DMA channel
1306 * @chan: Driver specific DMA channel
1308 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1313 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1315 /* Wait for the hardware to start */
1316 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1317 !(val & XILINX_DMA_DMASR_HALTED), 0,
1318 XILINX_DMA_LOOP_COUNT);
1321 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1322 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1329 * xilinx_vdma_start_transfer - Starts VDMA transfer
1330 * @chan: Driver specific channel struct pointer
1332 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1334 struct xilinx_vdma_config *config = &chan->config;
1335 struct xilinx_dma_tx_descriptor *desc;
1337 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1340 /* This function was invoked with lock held */
1347 if (list_empty(&chan->pending_list))
1350 desc = list_first_entry(&chan->pending_list,
1351 struct xilinx_dma_tx_descriptor, node);
1353 /* Configure the hardware using info in the config structure */
1354 if (chan->has_vflip) {
1355 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1356 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1357 reg |= config->vflip_en;
1358 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1362 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1364 if (config->frm_cnt_en)
1365 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1367 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1369 /* If not parking, enable circular mode */
1371 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1373 reg |= XILINX_DMA_DMACR_CIRC_EN;
1375 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1377 j = chan->desc_submitcount;
1378 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1379 if (chan->direction == DMA_MEM_TO_DEV) {
1380 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1381 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1383 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1384 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1386 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1388 /* Start the hardware */
1389 xilinx_dma_start(chan);
1394 /* Start the transfer */
1395 if (chan->desc_submitcount < chan->num_frms)
1396 i = chan->desc_submitcount;
1398 list_for_each_entry(segment, &desc->segments, node) {
1400 vdma_desc_write_64(chan,
1401 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1402 segment->hw.buf_addr,
1403 segment->hw.buf_addr_msb);
1405 vdma_desc_write(chan,
1406 XILINX_VDMA_REG_START_ADDRESS(i++),
1407 segment->hw.buf_addr);
1415 /* HW expects these parameters to be same for one transaction */
1416 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1417 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1419 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1421 chan->desc_submitcount++;
1422 chan->desc_pendingcount--;
1423 list_del(&desc->node);
1424 list_add_tail(&desc->node, &chan->active_list);
1425 if (chan->desc_submitcount == chan->num_frms)
1426 chan->desc_submitcount = 0;
1432 * xilinx_cdma_start_transfer - Starts cdma transfer
1433 * @chan: Driver specific channel struct pointer
1435 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1437 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1438 struct xilinx_cdma_tx_segment *tail_segment;
1439 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1447 if (list_empty(&chan->pending_list))
1450 head_desc = list_first_entry(&chan->pending_list,
1451 struct xilinx_dma_tx_descriptor, node);
1452 tail_desc = list_last_entry(&chan->pending_list,
1453 struct xilinx_dma_tx_descriptor, node);
1454 tail_segment = list_last_entry(&tail_desc->segments,
1455 struct xilinx_cdma_tx_segment, node);
1457 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1458 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1459 ctrl_reg |= chan->desc_pendingcount <<
1460 XILINX_DMA_CR_COALESCE_SHIFT;
1461 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1465 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1466 XILINX_CDMA_CR_SGMODE);
1468 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1469 XILINX_CDMA_CR_SGMODE);
1471 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1472 head_desc->async_tx.phys);
1474 /* Update tail ptr register which will start the transfer */
1475 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1476 tail_segment->phys);
1478 /* In simple mode */
1479 struct xilinx_cdma_tx_segment *segment;
1480 struct xilinx_cdma_desc_hw *hw;
1482 segment = list_first_entry(&head_desc->segments,
1483 struct xilinx_cdma_tx_segment,
1488 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1489 xilinx_prep_dma_addr_t(hw->src_addr));
1490 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1491 xilinx_prep_dma_addr_t(hw->dest_addr));
1493 /* Start the transfer */
1494 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1495 hw->control & chan->xdev->max_buffer_len);
1498 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1499 chan->desc_pendingcount = 0;
1504 * xilinx_dma_start_transfer - Starts DMA transfer
1505 * @chan: Driver specific channel struct pointer
1507 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1509 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1510 struct xilinx_axidma_tx_segment *tail_segment;
1516 if (list_empty(&chan->pending_list))
1522 head_desc = list_first_entry(&chan->pending_list,
1523 struct xilinx_dma_tx_descriptor, node);
1524 tail_desc = list_last_entry(&chan->pending_list,
1525 struct xilinx_dma_tx_descriptor, node);
1526 tail_segment = list_last_entry(&tail_desc->segments,
1527 struct xilinx_axidma_tx_segment, node);
1529 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1531 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1532 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1533 reg |= chan->desc_pendingcount <<
1534 XILINX_DMA_CR_COALESCE_SHIFT;
1535 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1539 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1540 head_desc->async_tx.phys);
1542 xilinx_dma_start(chan);
1547 /* Start the transfer */
1550 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1551 chan->cyclic_seg_v->phys);
1553 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1554 tail_segment->phys);
1556 struct xilinx_axidma_tx_segment *segment;
1557 struct xilinx_axidma_desc_hw *hw;
1559 segment = list_first_entry(&head_desc->segments,
1560 struct xilinx_axidma_tx_segment,
1564 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1565 xilinx_prep_dma_addr_t(hw->buf_addr));
1567 /* Start the transfer */
1568 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1569 hw->control & chan->xdev->max_buffer_len);
1572 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1573 chan->desc_pendingcount = 0;
1578 * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1579 * @chan: Driver specific channel struct pointer
1581 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1583 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1584 struct xilinx_aximcdma_tx_segment *tail_segment;
1588 * lock has been held by calling functions, so we don't need it
1589 * to take it here again.
1598 if (list_empty(&chan->pending_list))
1601 head_desc = list_first_entry(&chan->pending_list,
1602 struct xilinx_dma_tx_descriptor, node);
1603 tail_desc = list_last_entry(&chan->pending_list,
1604 struct xilinx_dma_tx_descriptor, node);
1605 tail_segment = list_last_entry(&tail_desc->segments,
1606 struct xilinx_aximcdma_tx_segment, node);
1608 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1610 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1611 reg &= ~XILINX_MCDMA_COALESCE_MASK;
1612 reg |= chan->desc_pendingcount <<
1613 XILINX_MCDMA_COALESCE_SHIFT;
1616 reg |= XILINX_MCDMA_IRQ_ALL_MASK;
1617 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1619 /* Program current descriptor */
1620 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1621 head_desc->async_tx.phys);
1623 /* Program channel enable register */
1624 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1625 reg |= BIT(chan->tdest);
1626 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1628 /* Start the fetch of BDs for the channel */
1629 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1630 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
1631 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1633 xilinx_dma_start(chan);
1638 /* Start the transfer */
1639 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1640 tail_segment->phys);
1642 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1643 chan->desc_pendingcount = 0;
1648 * xilinx_dma_issue_pending - Issue pending transactions
1649 * @dchan: DMA channel
1651 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1653 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1654 unsigned long flags;
1656 spin_lock_irqsave(&chan->lock, flags);
1657 chan->start_transfer(chan);
1658 spin_unlock_irqrestore(&chan->lock, flags);
1662 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1663 * @chan : xilinx DMA channel
1667 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1669 struct xilinx_dma_tx_descriptor *desc, *next;
1671 /* This function was invoked with lock held */
1672 if (list_empty(&chan->active_list))
1675 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1676 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1678 desc->residue = xilinx_dma_get_residue(chan, desc);
1681 desc->err = chan->err;
1683 list_del(&desc->node);
1685 dma_cookie_complete(&desc->async_tx);
1686 list_add_tail(&desc->node, &chan->done_list);
1691 * xilinx_dma_reset - Reset DMA channel
1692 * @chan: Driver specific DMA channel
1694 * Return: '0' on success and failure value on error
1696 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1701 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1703 /* Wait for the hardware to finish reset */
1704 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1705 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1706 XILINX_DMA_LOOP_COUNT);
1709 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1710 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1711 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1717 chan->desc_pendingcount = 0;
1718 chan->desc_submitcount = 0;
1724 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1725 * @chan: Driver specific DMA channel
1727 * Return: '0' on success and failure value on error
1729 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1734 err = xilinx_dma_reset(chan);
1738 /* Enable interrupts */
1739 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1740 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1746 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1748 * @data: Pointer to the Xilinx MCDMA channel structure
1750 * Return: IRQ_HANDLED/IRQ_NONE
1752 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
1754 struct xilinx_dma_chan *chan = data;
1755 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id;
1757 if (chan->direction == DMA_DEV_TO_MEM)
1758 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET;
1760 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET;
1762 /* Read the channel id raising the interrupt*/
1763 chan_sermask = dma_ctrl_read(chan, ser_offset);
1764 chan_id = ffs(chan_sermask);
1769 if (chan->direction == DMA_DEV_TO_MEM)
1770 chan_offset = chan->xdev->dma_config->max_channels / 2;
1772 chan_offset = chan_offset + (chan_id - 1);
1773 chan = chan->xdev->chan[chan_offset];
1774 /* Read the status and ack the interrupts. */
1775 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1776 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK))
1779 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1780 status & XILINX_MCDMA_IRQ_ALL_MASK);
1782 if (status & XILINX_MCDMA_IRQ_ERR_MASK) {
1783 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1785 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1786 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1788 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1793 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) {
1795 * Device takes too long to do the transfer when user requires
1798 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1801 if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
1802 spin_lock(&chan->lock);
1803 xilinx_dma_complete_descriptor(chan);
1805 chan->start_transfer(chan);
1806 spin_unlock(&chan->lock);
1809 tasklet_schedule(&chan->tasklet);
1814 * xilinx_dma_irq_handler - DMA Interrupt handler
1816 * @data: Pointer to the Xilinx DMA channel structure
1818 * Return: IRQ_HANDLED/IRQ_NONE
1820 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1822 struct xilinx_dma_chan *chan = data;
1825 /* Read the status and ack the interrupts. */
1826 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1827 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1830 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1831 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1833 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1835 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1836 * error is recoverable, ignore it. Otherwise flag the error.
1838 * Only recoverable errors can be cleared in the DMASR register,
1839 * make sure not to write to other error bits to 1.
1841 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1843 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1844 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1846 if (!chan->flush_on_fsync ||
1847 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1849 "Channel %p has errors %x, cdr %x tdr %x\n",
1851 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1852 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1857 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1859 * Device takes too long to do the transfer when user requires
1862 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1865 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1866 spin_lock(&chan->lock);
1867 xilinx_dma_complete_descriptor(chan);
1869 chan->start_transfer(chan);
1870 spin_unlock(&chan->lock);
1873 tasklet_schedule(&chan->tasklet);
1878 * append_desc_queue - Queuing descriptor
1879 * @chan: Driver specific dma channel
1880 * @desc: dma transaction descriptor
1882 static void append_desc_queue(struct xilinx_dma_chan *chan,
1883 struct xilinx_dma_tx_descriptor *desc)
1885 struct xilinx_vdma_tx_segment *tail_segment;
1886 struct xilinx_dma_tx_descriptor *tail_desc;
1887 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1888 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment;
1889 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1891 if (list_empty(&chan->pending_list))
1895 * Add the hardware descriptor to the chain of hardware descriptors
1896 * that already exists in memory.
1898 tail_desc = list_last_entry(&chan->pending_list,
1899 struct xilinx_dma_tx_descriptor, node);
1900 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1901 tail_segment = list_last_entry(&tail_desc->segments,
1902 struct xilinx_vdma_tx_segment,
1904 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1905 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1906 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1907 struct xilinx_cdma_tx_segment,
1909 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1910 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1911 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1912 struct xilinx_axidma_tx_segment,
1914 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1916 aximcdma_tail_segment =
1917 list_last_entry(&tail_desc->segments,
1918 struct xilinx_aximcdma_tx_segment,
1920 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1924 * Add the software descriptor and all children to the list
1925 * of pending transactions
1928 list_add_tail(&desc->node, &chan->pending_list);
1929 chan->desc_pendingcount++;
1931 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1932 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1933 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1934 chan->desc_pendingcount = chan->num_frms;
1939 * xilinx_dma_tx_submit - Submit DMA transaction
1940 * @tx: Async transaction descriptor
1942 * Return: cookie value on success and failure value on error
1944 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1946 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1947 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1948 dma_cookie_t cookie;
1949 unsigned long flags;
1953 xilinx_dma_free_tx_descriptor(chan, desc);
1959 * If reset fails, need to hard reset the system.
1960 * Channel is no longer functional
1962 err = xilinx_dma_chan_reset(chan);
1967 spin_lock_irqsave(&chan->lock, flags);
1969 cookie = dma_cookie_assign(tx);
1971 /* Put this transaction onto the tail of the pending queue */
1972 append_desc_queue(chan, desc);
1975 chan->cyclic = true;
1977 chan->terminating = false;
1979 spin_unlock_irqrestore(&chan->lock, flags);
1985 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1986 * DMA_SLAVE transaction
1987 * @dchan: DMA channel
1988 * @xt: Interleaved template pointer
1989 * @flags: transfer ack flags
1991 * Return: Async transaction descriptor on success and NULL on failure
1993 static struct dma_async_tx_descriptor *
1994 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1995 struct dma_interleaved_template *xt,
1996 unsigned long flags)
1998 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1999 struct xilinx_dma_tx_descriptor *desc;
2000 struct xilinx_vdma_tx_segment *segment;
2001 struct xilinx_vdma_desc_hw *hw;
2003 if (!is_slave_direction(xt->dir))
2006 if (!xt->numf || !xt->sgl[0].size)
2009 if (xt->frame_size != 1)
2012 /* Allocate a transaction descriptor. */
2013 desc = xilinx_dma_alloc_tx_descriptor(chan);
2017 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2018 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2019 async_tx_ack(&desc->async_tx);
2021 /* Allocate the link descriptor from DMA pool */
2022 segment = xilinx_vdma_alloc_tx_segment(chan);
2026 /* Fill in the hardware descriptor */
2028 hw->vsize = xt->numf;
2029 hw->hsize = xt->sgl[0].size;
2030 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
2031 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
2032 hw->stride |= chan->config.frm_dly <<
2033 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
2035 if (xt->dir != DMA_MEM_TO_DEV) {
2036 if (chan->ext_addr) {
2037 hw->buf_addr = lower_32_bits(xt->dst_start);
2038 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
2040 hw->buf_addr = xt->dst_start;
2043 if (chan->ext_addr) {
2044 hw->buf_addr = lower_32_bits(xt->src_start);
2045 hw->buf_addr_msb = upper_32_bits(xt->src_start);
2047 hw->buf_addr = xt->src_start;
2051 /* Insert the segment into the descriptor segments list. */
2052 list_add_tail(&segment->node, &desc->segments);
2054 /* Link the last hardware descriptor with the first. */
2055 segment = list_first_entry(&desc->segments,
2056 struct xilinx_vdma_tx_segment, node);
2057 desc->async_tx.phys = segment->phys;
2059 return &desc->async_tx;
2062 xilinx_dma_free_tx_descriptor(chan, desc);
2067 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2068 * @dchan: DMA channel
2069 * @dma_dst: destination address
2070 * @dma_src: source address
2071 * @len: transfer length
2072 * @flags: transfer ack flags
2074 * Return: Async transaction descriptor on success and NULL on failure
2076 static struct dma_async_tx_descriptor *
2077 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
2078 dma_addr_t dma_src, size_t len, unsigned long flags)
2080 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2081 struct xilinx_dma_tx_descriptor *desc;
2082 struct xilinx_cdma_tx_segment *segment;
2083 struct xilinx_cdma_desc_hw *hw;
2085 if (!len || len > chan->xdev->max_buffer_len)
2088 desc = xilinx_dma_alloc_tx_descriptor(chan);
2092 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2093 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2095 /* Allocate the link descriptor from DMA pool */
2096 segment = xilinx_cdma_alloc_tx_segment(chan);
2102 hw->src_addr = dma_src;
2103 hw->dest_addr = dma_dst;
2104 if (chan->ext_addr) {
2105 hw->src_addr_msb = upper_32_bits(dma_src);
2106 hw->dest_addr_msb = upper_32_bits(dma_dst);
2109 /* Insert the segment into the descriptor segments list. */
2110 list_add_tail(&segment->node, &desc->segments);
2112 desc->async_tx.phys = segment->phys;
2113 hw->next_desc = segment->phys;
2115 return &desc->async_tx;
2118 xilinx_dma_free_tx_descriptor(chan, desc);
2123 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2124 * @dchan: DMA channel
2125 * @sgl: scatterlist to transfer to/from
2126 * @sg_len: number of entries in @scatterlist
2127 * @direction: DMA direction
2128 * @flags: transfer ack flags
2129 * @context: APP words of the descriptor
2131 * Return: Async transaction descriptor on success and NULL on failure
2133 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
2134 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
2135 enum dma_transfer_direction direction, unsigned long flags,
2138 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2139 struct xilinx_dma_tx_descriptor *desc;
2140 struct xilinx_axidma_tx_segment *segment = NULL;
2141 u32 *app_w = (u32 *)context;
2142 struct scatterlist *sg;
2147 if (!is_slave_direction(direction))
2150 /* Allocate a transaction descriptor. */
2151 desc = xilinx_dma_alloc_tx_descriptor(chan);
2155 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2156 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2158 /* Build transactions using information in the scatter gather list */
2159 for_each_sg(sgl, sg, sg_len, i) {
2162 /* Loop until the entire scatterlist entry is used */
2163 while (sg_used < sg_dma_len(sg)) {
2164 struct xilinx_axidma_desc_hw *hw;
2166 /* Get a free segment */
2167 segment = xilinx_axidma_alloc_tx_segment(chan);
2172 * Calculate the maximum number of bytes to transfer,
2173 * making sure it is less than the hw limit
2175 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2179 /* Fill in the descriptor */
2180 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2185 if (chan->direction == DMA_MEM_TO_DEV) {
2187 memcpy(hw->app, app_w, sizeof(u32) *
2188 XILINX_DMA_NUM_APP_WORDS);
2194 * Insert the segment into the descriptor segments
2197 list_add_tail(&segment->node, &desc->segments);
2201 segment = list_first_entry(&desc->segments,
2202 struct xilinx_axidma_tx_segment, node);
2203 desc->async_tx.phys = segment->phys;
2205 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2206 if (chan->direction == DMA_MEM_TO_DEV) {
2207 segment->hw.control |= XILINX_DMA_BD_SOP;
2208 segment = list_last_entry(&desc->segments,
2209 struct xilinx_axidma_tx_segment,
2211 segment->hw.control |= XILINX_DMA_BD_EOP;
2214 return &desc->async_tx;
2217 xilinx_dma_free_tx_descriptor(chan, desc);
2222 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2223 * @dchan: DMA channel
2224 * @buf_addr: Physical address of the buffer
2225 * @buf_len: Total length of the cyclic buffers
2226 * @period_len: length of individual cyclic buffer
2227 * @direction: DMA direction
2228 * @flags: transfer ack flags
2230 * Return: Async transaction descriptor on success and NULL on failure
2232 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
2233 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
2234 size_t period_len, enum dma_transfer_direction direction,
2235 unsigned long flags)
2237 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2238 struct xilinx_dma_tx_descriptor *desc;
2239 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
2240 size_t copy, sg_used;
2241 unsigned int num_periods;
2248 num_periods = buf_len / period_len;
2253 if (!is_slave_direction(direction))
2256 /* Allocate a transaction descriptor. */
2257 desc = xilinx_dma_alloc_tx_descriptor(chan);
2261 chan->direction = direction;
2262 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2263 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2265 for (i = 0; i < num_periods; ++i) {
2268 while (sg_used < period_len) {
2269 struct xilinx_axidma_desc_hw *hw;
2271 /* Get a free segment */
2272 segment = xilinx_axidma_alloc_tx_segment(chan);
2277 * Calculate the maximum number of bytes to transfer,
2278 * making sure it is less than the hw limit
2280 copy = xilinx_dma_calc_copysize(chan, period_len,
2283 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2288 prev->hw.next_desc = segment->phys;
2294 * Insert the segment into the descriptor segments
2297 list_add_tail(&segment->node, &desc->segments);
2301 head_segment = list_first_entry(&desc->segments,
2302 struct xilinx_axidma_tx_segment, node);
2303 desc->async_tx.phys = head_segment->phys;
2305 desc->cyclic = true;
2306 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2307 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2308 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2310 segment = list_last_entry(&desc->segments,
2311 struct xilinx_axidma_tx_segment,
2313 segment->hw.next_desc = (u32) head_segment->phys;
2315 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2316 if (direction == DMA_MEM_TO_DEV) {
2317 head_segment->hw.control |= XILINX_DMA_BD_SOP;
2318 segment->hw.control |= XILINX_DMA_BD_EOP;
2321 return &desc->async_tx;
2324 xilinx_dma_free_tx_descriptor(chan, desc);
2329 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2330 * @dchan: DMA channel
2331 * @sgl: scatterlist to transfer to/from
2332 * @sg_len: number of entries in @scatterlist
2333 * @direction: DMA direction
2334 * @flags: transfer ack flags
2335 * @context: APP words of the descriptor
2337 * Return: Async transaction descriptor on success and NULL on failure
2339 static struct dma_async_tx_descriptor *
2340 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
2341 unsigned int sg_len,
2342 enum dma_transfer_direction direction,
2343 unsigned long flags, void *context)
2345 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2346 struct xilinx_dma_tx_descriptor *desc;
2347 struct xilinx_aximcdma_tx_segment *segment = NULL;
2348 u32 *app_w = (u32 *)context;
2349 struct scatterlist *sg;
2354 if (!is_slave_direction(direction))
2357 /* Allocate a transaction descriptor. */
2358 desc = xilinx_dma_alloc_tx_descriptor(chan);
2362 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2363 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2365 /* Build transactions using information in the scatter gather list */
2366 for_each_sg(sgl, sg, sg_len, i) {
2369 /* Loop until the entire scatterlist entry is used */
2370 while (sg_used < sg_dma_len(sg)) {
2371 struct xilinx_aximcdma_desc_hw *hw;
2373 /* Get a free segment */
2374 segment = xilinx_aximcdma_alloc_tx_segment(chan);
2379 * Calculate the maximum number of bytes to transfer,
2380 * making sure it is less than the hw limit
2382 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
2383 chan->xdev->max_buffer_len);
2386 /* Fill in the descriptor */
2387 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2391 if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2392 memcpy(hw->app, app_w, sizeof(u32) *
2393 XILINX_DMA_NUM_APP_WORDS);
2398 * Insert the segment into the descriptor segments
2401 list_add_tail(&segment->node, &desc->segments);
2405 segment = list_first_entry(&desc->segments,
2406 struct xilinx_aximcdma_tx_segment, node);
2407 desc->async_tx.phys = segment->phys;
2409 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2410 if (chan->direction == DMA_MEM_TO_DEV) {
2411 segment->hw.control |= XILINX_MCDMA_BD_SOP;
2412 segment = list_last_entry(&desc->segments,
2413 struct xilinx_aximcdma_tx_segment,
2415 segment->hw.control |= XILINX_MCDMA_BD_EOP;
2418 return &desc->async_tx;
2421 xilinx_dma_free_tx_descriptor(chan, desc);
2427 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2428 * @dchan: Driver specific DMA Channel pointer
2430 * Return: '0' always.
2432 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2434 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2438 if (!chan->cyclic) {
2439 err = chan->stop_transfer(chan);
2441 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2442 chan, dma_ctrl_read(chan,
2443 XILINX_DMA_REG_DMASR));
2448 xilinx_dma_chan_reset(chan);
2449 /* Remove and free all of the descriptors in the lists */
2450 chan->terminating = true;
2451 xilinx_dma_free_descriptors(chan);
2455 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2456 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2457 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2458 chan->cyclic = false;
2461 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2462 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2463 XILINX_CDMA_CR_SGMODE);
2469 * xilinx_dma_channel_set_config - Configure VDMA channel
2470 * Run-time configuration for Axi VDMA, supports:
2471 * . halt the channel
2472 * . configure interrupt coalescing and inter-packet delay threshold
2473 * . start/stop parking
2476 * @dchan: DMA channel
2477 * @cfg: VDMA device configuration pointer
2479 * Return: '0' on success and failure value on error
2481 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2482 struct xilinx_vdma_config *cfg)
2484 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2488 return xilinx_dma_chan_reset(chan);
2490 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2492 chan->config.frm_dly = cfg->frm_dly;
2493 chan->config.park = cfg->park;
2495 /* genlock settings */
2496 chan->config.gen_lock = cfg->gen_lock;
2497 chan->config.master = cfg->master;
2499 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2500 if (cfg->gen_lock && chan->genlock) {
2501 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2502 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2503 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2506 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2507 chan->config.vflip_en = cfg->vflip_en;
2510 chan->config.park_frm = cfg->park_frm;
2512 chan->config.park_frm = -1;
2514 chan->config.coalesc = cfg->coalesc;
2515 chan->config.delay = cfg->delay;
2517 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2518 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2519 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2520 chan->config.coalesc = cfg->coalesc;
2523 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2524 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2525 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2526 chan->config.delay = cfg->delay;
2529 /* FSync Source selection */
2530 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2531 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2533 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2537 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2539 /* -----------------------------------------------------------------------------
2544 * xilinx_dma_chan_remove - Per Channel remove function
2545 * @chan: Driver specific DMA channel
2547 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2549 /* Disable all interrupts */
2550 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2551 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2554 free_irq(chan->irq, chan);
2556 tasklet_kill(&chan->tasklet);
2558 list_del(&chan->common.device_node);
2561 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2562 struct clk **tx_clk, struct clk **rx_clk,
2563 struct clk **sg_clk, struct clk **tmp_clk)
2569 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2570 if (IS_ERR(*axi_clk))
2571 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2573 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2574 if (IS_ERR(*tx_clk))
2577 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2578 if (IS_ERR(*rx_clk))
2581 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2582 if (IS_ERR(*sg_clk))
2585 err = clk_prepare_enable(*axi_clk);
2587 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2591 err = clk_prepare_enable(*tx_clk);
2593 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2594 goto err_disable_axiclk;
2597 err = clk_prepare_enable(*rx_clk);
2599 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2600 goto err_disable_txclk;
2603 err = clk_prepare_enable(*sg_clk);
2605 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2606 goto err_disable_rxclk;
2612 clk_disable_unprepare(*rx_clk);
2614 clk_disable_unprepare(*tx_clk);
2616 clk_disable_unprepare(*axi_clk);
2621 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2622 struct clk **dev_clk, struct clk **tmp_clk,
2623 struct clk **tmp1_clk, struct clk **tmp2_clk)
2631 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2632 if (IS_ERR(*axi_clk))
2633 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2635 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2636 if (IS_ERR(*dev_clk))
2637 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n");
2639 err = clk_prepare_enable(*axi_clk);
2641 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2645 err = clk_prepare_enable(*dev_clk);
2647 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2648 goto err_disable_axiclk;
2654 clk_disable_unprepare(*axi_clk);
2659 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2660 struct clk **tx_clk, struct clk **txs_clk,
2661 struct clk **rx_clk, struct clk **rxs_clk)
2665 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2666 if (IS_ERR(*axi_clk))
2667 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2669 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2670 if (IS_ERR(*tx_clk))
2673 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2674 if (IS_ERR(*txs_clk))
2677 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2678 if (IS_ERR(*rx_clk))
2681 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2682 if (IS_ERR(*rxs_clk))
2685 err = clk_prepare_enable(*axi_clk);
2687 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n",
2692 err = clk_prepare_enable(*tx_clk);
2694 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2695 goto err_disable_axiclk;
2698 err = clk_prepare_enable(*txs_clk);
2700 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2701 goto err_disable_txclk;
2704 err = clk_prepare_enable(*rx_clk);
2706 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2707 goto err_disable_txsclk;
2710 err = clk_prepare_enable(*rxs_clk);
2712 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2713 goto err_disable_rxclk;
2719 clk_disable_unprepare(*rx_clk);
2721 clk_disable_unprepare(*txs_clk);
2723 clk_disable_unprepare(*tx_clk);
2725 clk_disable_unprepare(*axi_clk);
2730 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2732 clk_disable_unprepare(xdev->rxs_clk);
2733 clk_disable_unprepare(xdev->rx_clk);
2734 clk_disable_unprepare(xdev->txs_clk);
2735 clk_disable_unprepare(xdev->tx_clk);
2736 clk_disable_unprepare(xdev->axi_clk);
2740 * xilinx_dma_chan_probe - Per Channel Probing
2741 * It get channel features from the device tree entry and
2742 * initialize special channel handling routines
2744 * @xdev: Driver specific device structure
2745 * @node: Device node
2747 * Return: '0' on success and failure value on error
2749 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2750 struct device_node *node)
2752 struct xilinx_dma_chan *chan;
2753 bool has_dre = false;
2757 /* Allocate and initialize the channel structure */
2758 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2762 chan->dev = xdev->dev;
2764 chan->desc_pendingcount = 0x0;
2765 chan->ext_addr = xdev->ext_addr;
2766 /* This variable ensures that descriptors are not
2767 * Submitted when dma engine is in progress. This variable is
2768 * Added to avoid polling for a bit in the status register to
2769 * Know dma state in the driver hot path.
2773 spin_lock_init(&chan->lock);
2774 INIT_LIST_HEAD(&chan->pending_list);
2775 INIT_LIST_HEAD(&chan->done_list);
2776 INIT_LIST_HEAD(&chan->active_list);
2777 INIT_LIST_HEAD(&chan->free_seg_list);
2779 /* Retrieve the channel properties from the device tree */
2780 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2782 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2784 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2786 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2789 width = value >> 3; /* Convert bits to bytes */
2791 /* If data width is greater than 8 bytes, DRE is not in hw */
2796 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2798 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2799 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2800 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2801 chan->direction = DMA_MEM_TO_DEV;
2802 chan->id = xdev->mm2s_chan_id++;
2803 chan->tdest = chan->id;
2805 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2806 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2807 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2808 chan->config.park = 1;
2810 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2811 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2812 chan->flush_on_fsync = true;
2814 } else if (of_device_is_compatible(node,
2815 "xlnx,axi-vdma-s2mm-channel") ||
2816 of_device_is_compatible(node,
2817 "xlnx,axi-dma-s2mm-channel")) {
2818 chan->direction = DMA_DEV_TO_MEM;
2819 chan->id = xdev->s2mm_chan_id++;
2820 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2821 chan->has_vflip = of_property_read_bool(node,
2822 "xlnx,enable-vert-flip");
2823 if (chan->has_vflip) {
2824 chan->config.vflip_en = dma_read(chan,
2825 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2826 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2829 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
2830 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2832 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2834 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2835 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2836 chan->config.park = 1;
2838 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2839 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2840 chan->flush_on_fsync = true;
2843 dev_err(xdev->dev, "Invalid channel compatible node\n");
2847 /* Request the interrupt */
2848 chan->irq = irq_of_parse_and_map(node, chan->tdest);
2849 err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2850 IRQF_SHARED, "xilinx-dma-controller", chan);
2852 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2856 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2857 chan->start_transfer = xilinx_dma_start_transfer;
2858 chan->stop_transfer = xilinx_dma_stop_transfer;
2859 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
2860 chan->start_transfer = xilinx_mcdma_start_transfer;
2861 chan->stop_transfer = xilinx_dma_stop_transfer;
2862 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2863 chan->start_transfer = xilinx_cdma_start_transfer;
2864 chan->stop_transfer = xilinx_cdma_stop_transfer;
2866 chan->start_transfer = xilinx_vdma_start_transfer;
2867 chan->stop_transfer = xilinx_dma_stop_transfer;
2870 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */
2871 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
2872 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA ||
2873 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2874 XILINX_DMA_DMASR_SG_MASK)
2875 chan->has_sg = true;
2876 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2877 chan->has_sg ? "enabled" : "disabled");
2880 /* Initialize the tasklet */
2881 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
2884 * Initialize the DMA channel and add it to the DMA engine channels
2887 chan->common.device = &xdev->common;
2889 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2890 xdev->chan[chan->id] = chan;
2892 /* Reset the channel */
2893 err = xilinx_dma_chan_reset(chan);
2895 dev_err(xdev->dev, "Reset channel failed\n");
2903 * xilinx_dma_child_probe - Per child node probe
2904 * It get number of dma-channels per child node from
2905 * device-tree and initializes all the channels.
2907 * @xdev: Driver specific device structure
2908 * @node: Device node
2912 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2913 struct device_node *node)
2916 u32 nr_channels = 1;
2918 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2919 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
2920 dev_warn(xdev->dev, "missing dma-channels property\n");
2922 for (i = 0; i < nr_channels; i++)
2923 xilinx_dma_chan_probe(xdev, node);
2929 * of_dma_xilinx_xlate - Translation function
2930 * @dma_spec: Pointer to DMA specifier as found in the device tree
2931 * @ofdma: Pointer to DMA controller data
2933 * Return: DMA channel pointer on success and NULL on error
2935 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2936 struct of_dma *ofdma)
2938 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2939 int chan_id = dma_spec->args[0];
2941 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
2944 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2947 static const struct xilinx_dma_config axidma_config = {
2948 .dmatype = XDMA_TYPE_AXIDMA,
2949 .clk_init = axidma_clk_init,
2950 .irq_handler = xilinx_dma_irq_handler,
2951 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2954 static const struct xilinx_dma_config aximcdma_config = {
2955 .dmatype = XDMA_TYPE_AXIMCDMA,
2956 .clk_init = axidma_clk_init,
2957 .irq_handler = xilinx_mcdma_irq_handler,
2958 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE,
2960 static const struct xilinx_dma_config axicdma_config = {
2961 .dmatype = XDMA_TYPE_CDMA,
2962 .clk_init = axicdma_clk_init,
2963 .irq_handler = xilinx_dma_irq_handler,
2964 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE,
2967 static const struct xilinx_dma_config axivdma_config = {
2968 .dmatype = XDMA_TYPE_VDMA,
2969 .clk_init = axivdma_clk_init,
2970 .irq_handler = xilinx_dma_irq_handler,
2971 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2974 static const struct of_device_id xilinx_dma_of_ids[] = {
2975 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2976 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2977 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2978 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
2981 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2984 * xilinx_dma_probe - Driver probe function
2985 * @pdev: Pointer to the platform_device structure
2987 * Return: '0' on success and failure value on error
2989 static int xilinx_dma_probe(struct platform_device *pdev)
2991 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2992 struct clk **, struct clk **, struct clk **)
2994 struct device_node *node = pdev->dev.of_node;
2995 struct xilinx_dma_device *xdev;
2996 struct device_node *child, *np = pdev->dev.of_node;
2997 u32 num_frames, addr_width, len_width;
3000 /* Allocate and initialize the DMA engine structure */
3001 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
3005 xdev->dev = &pdev->dev;
3007 const struct of_device_id *match;
3009 match = of_match_node(xilinx_dma_of_ids, np);
3010 if (match && match->data) {
3011 xdev->dma_config = match->data;
3012 clk_init = xdev->dma_config->clk_init;
3016 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
3017 &xdev->rx_clk, &xdev->rxs_clk);
3021 /* Request and map I/O memory */
3022 xdev->regs = devm_platform_ioremap_resource(pdev, 0);
3023 if (IS_ERR(xdev->regs)) {
3024 err = PTR_ERR(xdev->regs);
3027 /* Retrieve the DMA engine properties from the device tree */
3028 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
3029 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
3031 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
3032 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3033 if (!of_property_read_u32(node, "xlnx,sg-length-width",
3035 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
3036 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
3038 "invalid xlnx,sg-length-width property value. Using default width\n");
3040 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
3041 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
3042 xdev->max_buffer_len =
3043 GENMASK(len_width - 1, 0);
3048 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3049 err = of_property_read_u32(node, "xlnx,num-fstores",
3053 "missing xlnx,num-fstores property\n");
3057 err = of_property_read_u32(node, "xlnx,flush-fsync",
3058 &xdev->flush_on_fsync);
3061 "missing xlnx,flush-fsync property\n");
3064 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
3066 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
3068 if (addr_width > 32)
3069 xdev->ext_addr = true;
3071 xdev->ext_addr = false;
3073 /* Set the dma mask bits */
3074 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
3076 dev_err(xdev->dev, "DMA mask error %d\n", err);
3080 /* Initialize the DMA engine */
3081 xdev->common.dev = &pdev->dev;
3083 INIT_LIST_HEAD(&xdev->common.channels);
3084 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
3085 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
3086 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
3089 xdev->common.device_alloc_chan_resources =
3090 xilinx_dma_alloc_chan_resources;
3091 xdev->common.device_free_chan_resources =
3092 xilinx_dma_free_chan_resources;
3093 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
3094 xdev->common.device_tx_status = xilinx_dma_tx_status;
3095 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
3096 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3097 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
3098 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
3099 xdev->common.device_prep_dma_cyclic =
3100 xilinx_dma_prep_dma_cyclic;
3101 /* Residue calculation is supported by only AXI DMA and CDMA */
3102 xdev->common.residue_granularity =
3103 DMA_RESIDUE_GRANULARITY_SEGMENT;
3104 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3105 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
3106 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
3107 /* Residue calculation is supported by only AXI DMA and CDMA */
3108 xdev->common.residue_granularity =
3109 DMA_RESIDUE_GRANULARITY_SEGMENT;
3110 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3111 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg;
3113 xdev->common.device_prep_interleaved_dma =
3114 xilinx_vdma_dma_prep_interleaved;
3117 platform_set_drvdata(pdev, xdev);
3119 /* Initialize the channels */
3120 for_each_child_of_node(node, child) {
3121 err = xilinx_dma_child_probe(xdev, child);
3128 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3129 for (i = 0; i < xdev->dma_config->max_channels; i++)
3131 xdev->chan[i]->num_frms = num_frames;
3134 /* Register the DMA engine with the core */
3135 err = dma_async_device_register(&xdev->common);
3137 dev_err(xdev->dev, "failed to register the dma device\n");
3141 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
3144 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
3145 dma_async_device_unregister(&xdev->common);
3149 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
3150 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
3151 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
3152 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
3153 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
3154 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n");
3156 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
3161 for (i = 0; i < xdev->dma_config->max_channels; i++)
3163 xilinx_dma_chan_remove(xdev->chan[i]);
3165 xdma_disable_allclks(xdev);
3171 * xilinx_dma_remove - Driver remove function
3172 * @pdev: Pointer to the platform_device structure
3174 * Return: Always '0'
3176 static int xilinx_dma_remove(struct platform_device *pdev)
3178 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
3181 of_dma_controller_free(pdev->dev.of_node);
3183 dma_async_device_unregister(&xdev->common);
3185 for (i = 0; i < xdev->dma_config->max_channels; i++)
3187 xilinx_dma_chan_remove(xdev->chan[i]);
3189 xdma_disable_allclks(xdev);
3194 static struct platform_driver xilinx_vdma_driver = {
3196 .name = "xilinx-vdma",
3197 .of_match_table = xilinx_dma_of_ids,
3199 .probe = xilinx_dma_probe,
3200 .remove = xilinx_dma_remove,
3203 module_platform_driver(xilinx_vdma_driver);
3205 MODULE_AUTHOR("Xilinx, Inc.");
3206 MODULE_DESCRIPTION("Xilinx VDMA driver");
3207 MODULE_LICENSE("GPL v2");