1 // SPDX-License-Identifier: GPL-2.0
3 * K3 NAVSS DMA glue interface
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/atomic.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
13 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/soc/ti/k3-ringacc.h>
17 #include <linux/dma/ti-cppi5.h>
18 #include <linux/dma/k3-udma-glue.h>
21 #include "k3-psil-priv.h"
23 struct k3_udma_glue_common {
25 struct udma_dev *udmax;
26 const struct udma_tisci_rm *tisci_rm;
27 struct k3_ringacc *ringacc;
38 struct k3_udma_glue_tx_channel {
39 struct k3_udma_glue_common common;
41 struct udma_tchan *udma_tchanx;
44 struct k3_ring *ringtx;
45 struct k3_ring *ringtxcq;
58 struct k3_udma_glue_rx_flow {
59 struct udma_rflow *udma_rflow;
61 struct k3_ring *ringrx;
62 struct k3_ring *ringrxfdq;
67 struct k3_udma_glue_rx_channel {
68 struct k3_udma_glue_common common;
70 struct udma_rchan *udma_rchanx;
79 struct k3_udma_glue_rx_flow *flows;
84 #define K3_UDMAX_TDOWN_TIMEOUT_US 1000
86 static int of_k3_udma_glue_parse(struct device_node *udmax_np,
87 struct k3_udma_glue_common *common)
89 common->ringacc = of_k3_ringacc_get_by_phandle(udmax_np,
91 if (IS_ERR(common->ringacc))
92 return PTR_ERR(common->ringacc);
94 common->udmax = of_xudma_dev_get(udmax_np, NULL);
95 if (IS_ERR(common->udmax))
96 return PTR_ERR(common->udmax);
98 common->tisci_rm = xudma_dev_get_tisci_rm(common->udmax);
103 static int of_k3_udma_glue_parse_chn(struct device_node *chn_np,
104 const char *name, struct k3_udma_glue_common *common,
107 struct psil_endpoint_config *ep_config;
108 struct of_phandle_args dma_spec;
116 index = of_property_match_string(chn_np, "dma-names", name);
120 if (of_parse_phandle_with_args(chn_np, "dmas", "#dma-cells", index,
124 thread_id = dma_spec.args[0];
125 if (dma_spec.args_count == 2) {
126 if (dma_spec.args[1] > 2) {
127 dev_err(common->dev, "Invalid channel atype: %u\n",
132 common->atype = dma_spec.args[1];
135 if (tx_chn && !(thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) {
140 if (!tx_chn && (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) {
145 /* get psil endpoint config */
146 ep_config = psil_get_ep_config(thread_id);
147 if (IS_ERR(ep_config)) {
149 "No configuration for psi-l thread 0x%04x\n",
151 ret = PTR_ERR(ep_config);
155 common->epib = ep_config->needs_epib;
156 common->psdata_size = ep_config->psd_size;
159 common->dst_thread = thread_id;
161 common->src_thread = thread_id;
163 ret = of_k3_udma_glue_parse(dma_spec.np, common);
166 of_node_put(dma_spec.np);
170 static void k3_udma_glue_dump_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
172 struct device *dev = tx_chn->common.dev;
174 dev_dbg(dev, "dump_tx_chn:\n"
175 "udma_tchan_id: %d\n"
177 "dst_thread: %08x\n",
178 tx_chn->udma_tchan_id,
179 tx_chn->common.src_thread,
180 tx_chn->common.dst_thread);
183 static void k3_udma_glue_dump_tx_rt_chn(struct k3_udma_glue_tx_channel *chn,
186 struct device *dev = chn->common.dev;
188 dev_dbg(dev, "=== dump ===> %s\n", mark);
189 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_CTL_REG,
190 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG));
191 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PEER_RT_EN_REG,
192 xudma_tchanrt_read(chn->udma_tchanx,
193 UDMA_CHAN_RT_PEER_RT_EN_REG));
194 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PCNT_REG,
195 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_PCNT_REG));
196 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_BCNT_REG,
197 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_BCNT_REG));
198 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_SBCNT_REG,
199 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_SBCNT_REG));
202 static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
204 const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm;
205 struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
207 memset(&req, 0, sizeof(req));
209 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
210 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID |
211 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID |
212 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
213 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID |
214 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
215 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
216 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
217 req.nav_id = tisci_rm->tisci_dev_id;
218 req.index = tx_chn->udma_tchan_id;
219 if (tx_chn->tx_pause_on_err)
220 req.tx_pause_on_err = 1;
221 if (tx_chn->tx_filt_einfo)
222 req.tx_filt_einfo = 1;
223 if (tx_chn->tx_filt_pswords)
224 req.tx_filt_pswords = 1;
225 req.tx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
226 if (tx_chn->tx_supr_tdpkt)
227 req.tx_supr_tdpkt = 1;
228 req.tx_fetch_size = tx_chn->common.hdesc_size >> 2;
229 req.txcq_qnum = k3_ringacc_get_ring_id(tx_chn->ringtxcq);
230 req.tx_atype = tx_chn->common.atype;
232 return tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
235 struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev,
236 const char *name, struct k3_udma_glue_tx_channel_cfg *cfg)
238 struct k3_udma_glue_tx_channel *tx_chn;
241 tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), GFP_KERNEL);
243 return ERR_PTR(-ENOMEM);
245 tx_chn->common.dev = dev;
246 tx_chn->common.swdata_size = cfg->swdata_size;
247 tx_chn->tx_pause_on_err = cfg->tx_pause_on_err;
248 tx_chn->tx_filt_einfo = cfg->tx_filt_einfo;
249 tx_chn->tx_filt_pswords = cfg->tx_filt_pswords;
250 tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt;
252 /* parse of udmap channel */
253 ret = of_k3_udma_glue_parse_chn(dev->of_node, name,
254 &tx_chn->common, true);
258 tx_chn->common.hdesc_size = cppi5_hdesc_calc_size(tx_chn->common.epib,
259 tx_chn->common.psdata_size,
260 tx_chn->common.swdata_size);
262 /* request and cfg UDMAP TX channel */
263 tx_chn->udma_tchanx = xudma_tchan_get(tx_chn->common.udmax, -1);
264 if (IS_ERR(tx_chn->udma_tchanx)) {
265 ret = PTR_ERR(tx_chn->udma_tchanx);
266 dev_err(dev, "UDMAX tchanx get err %d\n", ret);
269 tx_chn->udma_tchan_id = xudma_tchan_get_id(tx_chn->udma_tchanx);
271 atomic_set(&tx_chn->free_pkts, cfg->txcq_cfg.size);
273 /* request and cfg rings */
274 ret = k3_ringacc_request_rings_pair(tx_chn->common.ringacc,
275 tx_chn->udma_tchan_id, -1,
279 dev_err(dev, "Failed to get TX/TXCQ rings %d\n", ret);
283 ret = k3_ringacc_ring_cfg(tx_chn->ringtx, &cfg->tx_cfg);
285 dev_err(dev, "Failed to cfg ringtx %d\n", ret);
289 ret = k3_ringacc_ring_cfg(tx_chn->ringtxcq, &cfg->txcq_cfg);
291 dev_err(dev, "Failed to cfg ringtx %d\n", ret);
295 /* request and cfg psi-l */
296 tx_chn->common.src_thread =
297 xudma_dev_get_psil_base(tx_chn->common.udmax) +
298 tx_chn->udma_tchan_id;
300 ret = k3_udma_glue_cfg_tx_chn(tx_chn);
302 dev_err(dev, "Failed to cfg tchan %d\n", ret);
306 ret = xudma_navss_psil_pair(tx_chn->common.udmax,
307 tx_chn->common.src_thread,
308 tx_chn->common.dst_thread);
310 dev_err(dev, "PSI-L request err %d\n", ret);
314 tx_chn->psil_paired = true;
316 /* reset TX RT registers */
317 k3_udma_glue_disable_tx_chn(tx_chn);
319 k3_udma_glue_dump_tx_chn(tx_chn);
324 k3_udma_glue_release_tx_chn(tx_chn);
327 EXPORT_SYMBOL_GPL(k3_udma_glue_request_tx_chn);
329 void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
331 if (tx_chn->psil_paired) {
332 xudma_navss_psil_unpair(tx_chn->common.udmax,
333 tx_chn->common.src_thread,
334 tx_chn->common.dst_thread);
335 tx_chn->psil_paired = false;
338 if (!IS_ERR_OR_NULL(tx_chn->udma_tchanx))
339 xudma_tchan_put(tx_chn->common.udmax,
340 tx_chn->udma_tchanx);
342 if (tx_chn->ringtxcq)
343 k3_ringacc_ring_free(tx_chn->ringtxcq);
346 k3_ringacc_ring_free(tx_chn->ringtx);
348 EXPORT_SYMBOL_GPL(k3_udma_glue_release_tx_chn);
350 int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
351 struct cppi5_host_desc_t *desc_tx,
356 if (!atomic_add_unless(&tx_chn->free_pkts, -1, 0))
359 ringtxcq_id = k3_ringacc_get_ring_id(tx_chn->ringtxcq);
360 cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, ringtxcq_id);
362 return k3_ringacc_ring_push(tx_chn->ringtx, &desc_dma);
364 EXPORT_SYMBOL_GPL(k3_udma_glue_push_tx_chn);
366 int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
367 dma_addr_t *desc_dma)
371 ret = k3_ringacc_ring_pop(tx_chn->ringtxcq, desc_dma);
373 atomic_inc(&tx_chn->free_pkts);
377 EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn);
379 int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
381 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
382 UDMA_PEER_RT_EN_ENABLE);
384 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
385 UDMA_CHAN_RT_CTL_EN);
387 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
390 EXPORT_SYMBOL_GPL(k3_udma_glue_enable_tx_chn);
392 void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
394 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis1");
396 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 0);
398 xudma_tchanrt_write(tx_chn->udma_tchanx,
399 UDMA_CHAN_RT_PEER_RT_EN_REG, 0);
400 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis2");
402 EXPORT_SYMBOL_GPL(k3_udma_glue_disable_tx_chn);
404 void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
410 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown1");
412 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
413 UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
415 val = xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG);
417 while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
418 val = xudma_tchanrt_read(tx_chn->udma_tchanx,
419 UDMA_CHAN_RT_CTL_REG);
421 if (i > K3_UDMAX_TDOWN_TIMEOUT_US) {
422 dev_err(tx_chn->common.dev, "TX tdown timeout\n");
428 val = xudma_tchanrt_read(tx_chn->udma_tchanx,
429 UDMA_CHAN_RT_PEER_RT_EN_REG);
430 if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
431 dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n");
432 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown2");
434 EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_tx_chn);
436 void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
438 void (*cleanup)(void *data, dma_addr_t desc_dma))
443 /* reset TXCQ as it is not input for udma - expected to be empty */
444 if (tx_chn->ringtxcq)
445 k3_ringacc_ring_reset(tx_chn->ringtxcq);
448 * TXQ reset need to be special way as it is input for udma and its
449 * state cached by udma, so:
451 * 2) clean up TXQ and call callback .cleanup() for each desc
452 * 3) reset TXQ in a special way
454 occ_tx = k3_ringacc_ring_get_occ(tx_chn->ringtx);
455 dev_dbg(tx_chn->common.dev, "TX reset occ_tx %u\n", occ_tx);
457 for (i = 0; i < occ_tx; i++) {
458 ret = k3_ringacc_ring_pop(tx_chn->ringtx, &desc_dma);
460 dev_err(tx_chn->common.dev, "TX reset pop %d\n", ret);
463 cleanup(data, desc_dma);
466 k3_ringacc_ring_reset_dma(tx_chn->ringtx, occ_tx);
468 EXPORT_SYMBOL_GPL(k3_udma_glue_reset_tx_chn);
470 u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn)
472 return tx_chn->common.hdesc_size;
474 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_hdesc_size);
476 u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn)
478 return k3_ringacc_get_ring_id(tx_chn->ringtxcq);
480 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_txcq_id);
482 int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn)
484 tx_chn->virq = k3_ringacc_get_ring_irq_num(tx_chn->ringtxcq);
488 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_irq);
490 static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
492 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm;
493 struct ti_sci_msg_rm_udmap_rx_ch_cfg req;
496 memset(&req, 0, sizeof(req));
498 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
499 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
500 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
501 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
502 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID |
503 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
505 req.nav_id = tisci_rm->tisci_dev_id;
506 req.index = rx_chn->udma_rchan_id;
507 req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
509 * TODO: we can't support rxcq_qnum/RCHAN[a]_RCQ cfg with current sysfw
510 * and udmax impl, so just configure it to invalid value.
511 * req.rxcq_qnum = k3_ringacc_get_ring_id(rx_chn->flows[0].ringrx);
513 req.rxcq_qnum = 0xFFFF;
514 if (rx_chn->flow_num && rx_chn->flow_id_base != rx_chn->udma_rchan_id) {
515 /* Default flow + extra ones */
516 req.flowid_start = rx_chn->flow_id_base;
517 req.flowid_cnt = rx_chn->flow_num;
519 req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
520 req.rx_atype = rx_chn->common.atype;
522 ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
524 dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n",
525 rx_chn->udma_rchan_id, ret);
530 static void k3_udma_glue_release_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
533 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
535 if (IS_ERR_OR_NULL(flow->udma_rflow))
539 k3_ringacc_ring_free(flow->ringrxfdq);
542 k3_ringacc_ring_free(flow->ringrx);
544 xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow);
545 flow->udma_rflow = NULL;
546 rx_chn->flows_ready--;
549 static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
551 struct k3_udma_glue_rx_flow_cfg *flow_cfg)
553 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx];
554 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm;
555 struct device *dev = rx_chn->common.dev;
556 struct ti_sci_msg_rm_udmap_flow_cfg req;
561 flow->udma_rflow = xudma_rflow_get(rx_chn->common.udmax,
562 flow->udma_rflow_id);
563 if (IS_ERR(flow->udma_rflow)) {
564 ret = PTR_ERR(flow->udma_rflow);
565 dev_err(dev, "UDMAX rflow get err %d\n", ret);
569 if (flow->udma_rflow_id != xudma_rflow_get_id(flow->udma_rflow)) {
574 /* request and cfg rings */
575 ret = k3_ringacc_request_rings_pair(rx_chn->common.ringacc,
576 flow_cfg->ring_rxfdq0_id,
577 flow_cfg->ring_rxq_id,
581 dev_err(dev, "Failed to get RX/RXFDQ rings %d\n", ret);
585 ret = k3_ringacc_ring_cfg(flow->ringrx, &flow_cfg->rx_cfg);
587 dev_err(dev, "Failed to cfg ringrx %d\n", ret);
588 goto err_ringrxfdq_free;
591 ret = k3_ringacc_ring_cfg(flow->ringrxfdq, &flow_cfg->rxfdq_cfg);
593 dev_err(dev, "Failed to cfg ringrxfdq %d\n", ret);
594 goto err_ringrxfdq_free;
597 if (rx_chn->remote) {
598 rx_ring_id = TI_SCI_RESOURCE_NULL;
599 rx_ringfdq_id = TI_SCI_RESOURCE_NULL;
601 rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
602 rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
605 memset(&req, 0, sizeof(req));
608 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
609 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
610 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
611 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
612 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
613 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
614 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
615 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
616 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
617 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
618 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
619 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
620 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID;
621 req.nav_id = tisci_rm->tisci_dev_id;
622 req.flow_index = flow->udma_rflow_id;
623 if (rx_chn->common.epib)
624 req.rx_einfo_present = 1;
625 if (rx_chn->common.psdata_size)
626 req.rx_psinfo_present = 1;
627 if (flow_cfg->rx_error_handling)
628 req.rx_error_handling = 1;
629 req.rx_desc_type = 0;
630 req.rx_dest_qnum = rx_ring_id;
631 req.rx_src_tag_hi_sel = 0;
632 req.rx_src_tag_lo_sel = flow_cfg->src_tag_lo_sel;
633 req.rx_dest_tag_hi_sel = 0;
634 req.rx_dest_tag_lo_sel = 0;
635 req.rx_fdq0_sz0_qnum = rx_ringfdq_id;
636 req.rx_fdq1_qnum = rx_ringfdq_id;
637 req.rx_fdq2_qnum = rx_ringfdq_id;
638 req.rx_fdq3_qnum = rx_ringfdq_id;
640 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);
642 dev_err(dev, "flow%d config failed: %d\n", flow->udma_rflow_id,
644 goto err_ringrxfdq_free;
647 rx_chn->flows_ready++;
648 dev_dbg(dev, "flow%d config done. ready:%d\n",
649 flow->udma_rflow_id, rx_chn->flows_ready);
654 k3_ringacc_ring_free(flow->ringrxfdq);
655 k3_ringacc_ring_free(flow->ringrx);
658 xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow);
659 flow->udma_rflow = NULL;
664 static void k3_udma_glue_dump_rx_chn(struct k3_udma_glue_rx_channel *chn)
666 struct device *dev = chn->common.dev;
668 dev_dbg(dev, "dump_rx_chn:\n"
669 "udma_rchan_id: %d\n"
679 chn->common.src_thread,
680 chn->common.dst_thread,
682 chn->common.hdesc_size,
683 chn->common.psdata_size,
684 chn->common.swdata_size,
689 static void k3_udma_glue_dump_rx_rt_chn(struct k3_udma_glue_rx_channel *chn,
692 struct device *dev = chn->common.dev;
694 dev_dbg(dev, "=== dump ===> %s\n", mark);
696 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_CTL_REG,
697 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG));
698 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PEER_RT_EN_REG,
699 xudma_rchanrt_read(chn->udma_rchanx,
700 UDMA_CHAN_RT_PEER_RT_EN_REG));
701 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PCNT_REG,
702 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_PCNT_REG));
703 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_BCNT_REG,
704 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_BCNT_REG));
705 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_SBCNT_REG,
706 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_SBCNT_REG));
710 k3_udma_glue_allocate_rx_flows(struct k3_udma_glue_rx_channel *rx_chn,
711 struct k3_udma_glue_rx_channel_cfg *cfg)
716 if (cfg->flow_id_use_rxchan_id)
719 /* not a GP rflows */
720 if (rx_chn->flow_id_base != -1 &&
721 !xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base))
724 /* Allocate range of GP rflows */
725 ret = xudma_alloc_gp_rflow_range(rx_chn->common.udmax,
726 rx_chn->flow_id_base,
729 dev_err(rx_chn->common.dev, "UDMAX reserve_rflow %d cnt:%d err: %d\n",
730 rx_chn->flow_id_base, rx_chn->flow_num, ret);
733 rx_chn->flow_id_base = ret;
738 static struct k3_udma_glue_rx_channel *
739 k3_udma_glue_request_rx_chn_priv(struct device *dev, const char *name,
740 struct k3_udma_glue_rx_channel_cfg *cfg)
742 struct k3_udma_glue_rx_channel *rx_chn;
745 if (cfg->flow_id_num <= 0)
746 return ERR_PTR(-EINVAL);
748 if (cfg->flow_id_num != 1 &&
749 (cfg->def_flow_cfg || cfg->flow_id_use_rxchan_id))
750 return ERR_PTR(-EINVAL);
752 rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), GFP_KERNEL);
754 return ERR_PTR(-ENOMEM);
756 rx_chn->common.dev = dev;
757 rx_chn->common.swdata_size = cfg->swdata_size;
758 rx_chn->remote = false;
760 /* parse of udmap channel */
761 ret = of_k3_udma_glue_parse_chn(dev->of_node, name,
762 &rx_chn->common, false);
766 rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib,
767 rx_chn->common.psdata_size,
768 rx_chn->common.swdata_size);
770 /* request and cfg UDMAP RX channel */
771 rx_chn->udma_rchanx = xudma_rchan_get(rx_chn->common.udmax, -1);
772 if (IS_ERR(rx_chn->udma_rchanx)) {
773 ret = PTR_ERR(rx_chn->udma_rchanx);
774 dev_err(dev, "UDMAX rchanx get err %d\n", ret);
777 rx_chn->udma_rchan_id = xudma_rchan_get_id(rx_chn->udma_rchanx);
779 rx_chn->flow_num = cfg->flow_id_num;
780 rx_chn->flow_id_base = cfg->flow_id_base;
782 /* Use RX channel id as flow id: target dev can't generate flow_id */
783 if (cfg->flow_id_use_rxchan_id)
784 rx_chn->flow_id_base = rx_chn->udma_rchan_id;
786 rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num,
787 sizeof(*rx_chn->flows), GFP_KERNEL);
788 if (!rx_chn->flows) {
793 ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg);
797 for (i = 0; i < rx_chn->flow_num; i++)
798 rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i;
800 /* request and cfg psi-l */
801 rx_chn->common.dst_thread =
802 xudma_dev_get_psil_base(rx_chn->common.udmax) +
803 rx_chn->udma_rchan_id;
805 ret = k3_udma_glue_cfg_rx_chn(rx_chn);
807 dev_err(dev, "Failed to cfg rchan %d\n", ret);
811 /* init default RX flow only if flow_num = 1 */
812 if (cfg->def_flow_cfg) {
813 ret = k3_udma_glue_cfg_rx_flow(rx_chn, 0, cfg->def_flow_cfg);
818 ret = xudma_navss_psil_pair(rx_chn->common.udmax,
819 rx_chn->common.src_thread,
820 rx_chn->common.dst_thread);
822 dev_err(dev, "PSI-L request err %d\n", ret);
826 rx_chn->psil_paired = true;
828 /* reset RX RT registers */
829 k3_udma_glue_disable_rx_chn(rx_chn);
831 k3_udma_glue_dump_rx_chn(rx_chn);
836 k3_udma_glue_release_rx_chn(rx_chn);
840 static struct k3_udma_glue_rx_channel *
841 k3_udma_glue_request_remote_rx_chn(struct device *dev, const char *name,
842 struct k3_udma_glue_rx_channel_cfg *cfg)
844 struct k3_udma_glue_rx_channel *rx_chn;
847 if (cfg->flow_id_num <= 0 ||
848 cfg->flow_id_use_rxchan_id ||
850 cfg->flow_id_base < 0)
851 return ERR_PTR(-EINVAL);
854 * Remote RX channel is under control of Remote CPU core, so
855 * Linux can only request and manipulate by dedicated RX flows
858 rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), GFP_KERNEL);
860 return ERR_PTR(-ENOMEM);
862 rx_chn->common.dev = dev;
863 rx_chn->common.swdata_size = cfg->swdata_size;
864 rx_chn->remote = true;
865 rx_chn->udma_rchan_id = -1;
866 rx_chn->flow_num = cfg->flow_id_num;
867 rx_chn->flow_id_base = cfg->flow_id_base;
868 rx_chn->psil_paired = false;
870 /* parse of udmap channel */
871 ret = of_k3_udma_glue_parse_chn(dev->of_node, name,
872 &rx_chn->common, false);
876 rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib,
877 rx_chn->common.psdata_size,
878 rx_chn->common.swdata_size);
880 rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num,
881 sizeof(*rx_chn->flows), GFP_KERNEL);
882 if (!rx_chn->flows) {
887 ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg);
891 for (i = 0; i < rx_chn->flow_num; i++)
892 rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i;
894 k3_udma_glue_dump_rx_chn(rx_chn);
899 k3_udma_glue_release_rx_chn(rx_chn);
903 struct k3_udma_glue_rx_channel *
904 k3_udma_glue_request_rx_chn(struct device *dev, const char *name,
905 struct k3_udma_glue_rx_channel_cfg *cfg)
908 return k3_udma_glue_request_remote_rx_chn(dev, name, cfg);
910 return k3_udma_glue_request_rx_chn_priv(dev, name, cfg);
912 EXPORT_SYMBOL_GPL(k3_udma_glue_request_rx_chn);
914 void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
918 if (IS_ERR_OR_NULL(rx_chn->common.udmax))
921 if (rx_chn->psil_paired) {
922 xudma_navss_psil_unpair(rx_chn->common.udmax,
923 rx_chn->common.src_thread,
924 rx_chn->common.dst_thread);
925 rx_chn->psil_paired = false;
928 for (i = 0; i < rx_chn->flow_num; i++)
929 k3_udma_glue_release_rx_flow(rx_chn, i);
931 if (xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base))
932 xudma_free_gp_rflow_range(rx_chn->common.udmax,
933 rx_chn->flow_id_base,
936 if (!IS_ERR_OR_NULL(rx_chn->udma_rchanx))
937 xudma_rchan_put(rx_chn->common.udmax,
938 rx_chn->udma_rchanx);
940 EXPORT_SYMBOL_GPL(k3_udma_glue_release_rx_chn);
942 int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn,
944 struct k3_udma_glue_rx_flow_cfg *flow_cfg)
946 if (flow_idx >= rx_chn->flow_num)
949 return k3_udma_glue_cfg_rx_flow(rx_chn, flow_idx, flow_cfg);
951 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_init);
953 u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn,
956 struct k3_udma_glue_rx_flow *flow;
958 if (flow_idx >= rx_chn->flow_num)
961 flow = &rx_chn->flows[flow_idx];
963 return k3_ringacc_get_ring_id(flow->ringrxfdq);
965 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_get_fdq_id);
967 u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn)
969 return rx_chn->flow_id_base;
971 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_flow_id_base);
973 int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
976 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx];
977 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm;
978 struct device *dev = rx_chn->common.dev;
979 struct ti_sci_msg_rm_udmap_flow_cfg req;
987 rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
988 rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
990 memset(&req, 0, sizeof(req));
993 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
994 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
995 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
996 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
997 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID;
998 req.nav_id = tisci_rm->tisci_dev_id;
999 req.flow_index = flow->udma_rflow_id;
1000 req.rx_dest_qnum = rx_ring_id;
1001 req.rx_fdq0_sz0_qnum = rx_ringfdq_id;
1002 req.rx_fdq1_qnum = rx_ringfdq_id;
1003 req.rx_fdq2_qnum = rx_ringfdq_id;
1004 req.rx_fdq3_qnum = rx_ringfdq_id;
1006 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);
1008 dev_err(dev, "flow%d enable failed: %d\n", flow->udma_rflow_id,
1014 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_enable);
1016 int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
1019 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx];
1020 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm;
1021 struct device *dev = rx_chn->common.dev;
1022 struct ti_sci_msg_rm_udmap_flow_cfg req;
1025 if (!rx_chn->remote)
1028 memset(&req, 0, sizeof(req));
1030 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
1031 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
1032 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
1033 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
1034 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID;
1035 req.nav_id = tisci_rm->tisci_dev_id;
1036 req.flow_index = flow->udma_rflow_id;
1037 req.rx_dest_qnum = TI_SCI_RESOURCE_NULL;
1038 req.rx_fdq0_sz0_qnum = TI_SCI_RESOURCE_NULL;
1039 req.rx_fdq1_qnum = TI_SCI_RESOURCE_NULL;
1040 req.rx_fdq2_qnum = TI_SCI_RESOURCE_NULL;
1041 req.rx_fdq3_qnum = TI_SCI_RESOURCE_NULL;
1043 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);
1045 dev_err(dev, "flow%d disable failed: %d\n", flow->udma_rflow_id,
1051 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_disable);
1053 int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
1058 if (rx_chn->flows_ready < rx_chn->flow_num)
1061 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
1062 UDMA_CHAN_RT_CTL_EN);
1064 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
1065 UDMA_PEER_RT_EN_ENABLE);
1067 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en");
1070 EXPORT_SYMBOL_GPL(k3_udma_glue_enable_rx_chn);
1072 void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
1074 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis1");
1076 xudma_rchanrt_write(rx_chn->udma_rchanx,
1077 UDMA_CHAN_RT_PEER_RT_EN_REG, 0);
1078 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, 0);
1080 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis2");
1082 EXPORT_SYMBOL_GPL(k3_udma_glue_disable_rx_chn);
1084 void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
1093 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown1");
1095 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
1096 UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN);
1098 val = xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG);
1100 while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
1101 val = xudma_rchanrt_read(rx_chn->udma_rchanx,
1102 UDMA_CHAN_RT_CTL_REG);
1104 if (i > K3_UDMAX_TDOWN_TIMEOUT_US) {
1105 dev_err(rx_chn->common.dev, "RX tdown timeout\n");
1111 val = xudma_rchanrt_read(rx_chn->udma_rchanx,
1112 UDMA_CHAN_RT_PEER_RT_EN_REG);
1113 if (sync && (val & UDMA_PEER_RT_EN_ENABLE))
1114 dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n");
1115 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown2");
1117 EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_rx_chn);
1119 void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
1120 u32 flow_num, void *data,
1121 void (*cleanup)(void *data, dma_addr_t desc_dma), bool skip_fdq)
1123 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
1124 struct device *dev = rx_chn->common.dev;
1125 dma_addr_t desc_dma;
1128 /* reset RXCQ as it is not input for udma - expected to be empty */
1129 occ_rx = k3_ringacc_ring_get_occ(flow->ringrx);
1130 dev_dbg(dev, "RX reset flow %u occ_rx %u\n", flow_num, occ_rx);
1132 k3_ringacc_ring_reset(flow->ringrx);
1134 /* Skip RX FDQ in case one FDQ is used for the set of flows */
1139 * RX FDQ reset need to be special way as it is input for udma and its
1140 * state cached by udma, so:
1141 * 1) save RX FDQ occ
1142 * 2) clean up RX FDQ and call callback .cleanup() for each desc
1143 * 3) reset RX FDQ in a special way
1145 occ_rx = k3_ringacc_ring_get_occ(flow->ringrxfdq);
1146 dev_dbg(dev, "RX reset flow %u occ_rx_fdq %u\n", flow_num, occ_rx);
1148 for (i = 0; i < occ_rx; i++) {
1149 ret = k3_ringacc_ring_pop(flow->ringrxfdq, &desc_dma);
1151 dev_err(dev, "RX reset pop %d\n", ret);
1154 cleanup(data, desc_dma);
1157 k3_ringacc_ring_reset_dma(flow->ringrxfdq, occ_rx);
1159 EXPORT_SYMBOL_GPL(k3_udma_glue_reset_rx_chn);
1161 int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
1162 u32 flow_num, struct cppi5_host_desc_t *desc_rx,
1163 dma_addr_t desc_dma)
1165 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
1167 return k3_ringacc_ring_push(flow->ringrxfdq, &desc_dma);
1169 EXPORT_SYMBOL_GPL(k3_udma_glue_push_rx_chn);
1171 int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
1172 u32 flow_num, dma_addr_t *desc_dma)
1174 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
1176 return k3_ringacc_ring_pop(flow->ringrx, desc_dma);
1178 EXPORT_SYMBOL_GPL(k3_udma_glue_pop_rx_chn);
1180 int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
1183 struct k3_udma_glue_rx_flow *flow;
1185 flow = &rx_chn->flows[flow_num];
1187 flow->virq = k3_ringacc_get_ring_irq_num(flow->ringrx);
1191 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_irq);