GNU Linux-libre 4.9.299-gnu1
[releases.git] / drivers / dma / tegra210-adma.c
1 /*
2  * ADMA driver for Nvidia's Tegra210 ADMA controller.
3  *
4  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/iopoll.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/of_dma.h>
24 #include <linux/of_irq.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/slab.h>
27
28 #include "virt-dma.h"
29
30 #define ADMA_CH_CMD                                     0x00
31 #define ADMA_CH_STATUS                                  0x0c
32 #define ADMA_CH_STATUS_XFER_EN                          BIT(0)
33
34 #define ADMA_CH_INT_STATUS                              0x10
35 #define ADMA_CH_INT_STATUS_XFER_DONE                    BIT(0)
36
37 #define ADMA_CH_INT_CLEAR                               0x1c
38 #define ADMA_CH_CTRL                                    0x24
39 #define ADMA_CH_CTRL_TX_REQ(val)                        (((val) & 0xf) << 28)
40 #define ADMA_CH_CTRL_TX_REQ_MAX                         10
41 #define ADMA_CH_CTRL_RX_REQ(val)                        (((val) & 0xf) << 24)
42 #define ADMA_CH_CTRL_RX_REQ_MAX                         10
43 #define ADMA_CH_CTRL_DIR(val)                           (((val) & 0xf) << 12)
44 #define ADMA_CH_CTRL_DIR_AHUB2MEM                       2
45 #define ADMA_CH_CTRL_DIR_MEM2AHUB                       4
46 #define ADMA_CH_CTRL_MODE_CONTINUOUS                    (2 << 8)
47 #define ADMA_CH_CTRL_FLOWCTRL_EN                        BIT(1)
48
49 #define ADMA_CH_CONFIG                                  0x28
50 #define ADMA_CH_CONFIG_SRC_BUF(val)                     (((val) & 0x7) << 28)
51 #define ADMA_CH_CONFIG_TRG_BUF(val)                     (((val) & 0x7) << 24)
52 #define ADMA_CH_CONFIG_BURST_SIZE(val)                  (((val) & 0x7) << 20)
53 #define ADMA_CH_CONFIG_BURST_16                         5
54 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val)              ((val) & 0xf)
55 #define ADMA_CH_CONFIG_MAX_BUFS                         8
56
57 #define ADMA_CH_FIFO_CTRL                               0x2c
58 #define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val)              (((val) & 0xf) << 24)
59 #define ADMA_CH_FIFO_CTRL_STARV_THRES(val)              (((val) & 0xf) << 16)
60 #define ADMA_CH_FIFO_CTRL_TX_SIZE(val)                  (((val) & 0xf) << 8)
61 #define ADMA_CH_FIFO_CTRL_RX_SIZE(val)                  ((val) & 0xf)
62
63 #define ADMA_CH_LOWER_SRC_ADDR                          0x34
64 #define ADMA_CH_LOWER_TRG_ADDR                          0x3c
65 #define ADMA_CH_TC                                      0x44
66 #define ADMA_CH_TC_COUNT_MASK                           0x3ffffffc
67
68 #define ADMA_CH_XFER_STATUS                             0x54
69 #define ADMA_CH_XFER_STATUS_COUNT_MASK                  0xffff
70
71 #define ADMA_GLOBAL_CMD                                 0xc00
72 #define ADMA_GLOBAL_SOFT_RESET                          0xc04
73 #define ADMA_GLOBAL_INT_CLEAR                           0xc20
74 #define ADMA_GLOBAL_CTRL                                0xc24
75
76 #define ADMA_CH_REG_OFFSET(a)                           (a * 0x80)
77
78 #define ADMA_CH_FIFO_CTRL_DEFAULT       (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) | \
79                                          ADMA_CH_FIFO_CTRL_STARV_THRES(1) | \
80                                          ADMA_CH_FIFO_CTRL_TX_SIZE(3)     | \
81                                          ADMA_CH_FIFO_CTRL_RX_SIZE(3))
82 struct tegra_adma;
83
84 /*
85  * struct tegra_adma_chip_data - Tegra chip specific data
86  * @nr_channels: Number of DMA channels available.
87  */
88 struct tegra_adma_chip_data {
89         int nr_channels;
90 };
91
92 /*
93  * struct tegra_adma_chan_regs - Tegra ADMA channel registers
94  */
95 struct tegra_adma_chan_regs {
96         unsigned int ctrl;
97         unsigned int config;
98         unsigned int src_addr;
99         unsigned int trg_addr;
100         unsigned int fifo_ctrl;
101         unsigned int cmd;
102         unsigned int tc;
103 };
104
105 /*
106  * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
107  */
108 struct tegra_adma_desc {
109         struct virt_dma_desc            vd;
110         struct tegra_adma_chan_regs     ch_regs;
111         size_t                          buf_len;
112         size_t                          period_len;
113         size_t                          num_periods;
114 };
115
116 /*
117  * struct tegra_adma_chan - Tegra ADMA channel information
118  */
119 struct tegra_adma_chan {
120         struct virt_dma_chan            vc;
121         struct tegra_adma_desc          *desc;
122         struct tegra_adma               *tdma;
123         int                             irq;
124         void __iomem                    *chan_addr;
125
126         /* Slave channel configuration info */
127         struct dma_slave_config         sconfig;
128         enum dma_transfer_direction     sreq_dir;
129         unsigned int                    sreq_index;
130         bool                            sreq_reserved;
131         struct tegra_adma_chan_regs     ch_regs;
132
133         /* Transfer count and position info */
134         unsigned int                    tx_buf_count;
135         unsigned int                    tx_buf_pos;
136 };
137
138 /*
139  * struct tegra_adma - Tegra ADMA controller information
140  */
141 struct tegra_adma {
142         struct dma_device               dma_dev;
143         struct device                   *dev;
144         void __iomem                    *base_addr;
145         struct clk                      *ahub_clk;
146         unsigned int                    nr_channels;
147         unsigned long                   rx_requests_reserved;
148         unsigned long                   tx_requests_reserved;
149
150         /* Used to store global command register state when suspending */
151         unsigned int                    global_cmd;
152
153         /* Last member of the structure */
154         struct tegra_adma_chan          channels[0];
155 };
156
157 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
158 {
159         writel(val, tdma->base_addr + reg);
160 }
161
162 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
163 {
164         return readl(tdma->base_addr + reg);
165 }
166
167 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
168 {
169         writel(val, tdc->chan_addr + reg);
170 }
171
172 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
173 {
174         return readl(tdc->chan_addr + reg);
175 }
176
177 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
178 {
179         return container_of(dc, struct tegra_adma_chan, vc.chan);
180 }
181
182 static inline struct tegra_adma_desc *to_tegra_adma_desc(
183                 struct dma_async_tx_descriptor *td)
184 {
185         return container_of(td, struct tegra_adma_desc, vd.tx);
186 }
187
188 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
189 {
190         return tdc->tdma->dev;
191 }
192
193 static void tegra_adma_desc_free(struct virt_dma_desc *vd)
194 {
195         kfree(container_of(vd, struct tegra_adma_desc, vd));
196 }
197
198 static int tegra_adma_slave_config(struct dma_chan *dc,
199                                    struct dma_slave_config *sconfig)
200 {
201         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
202
203         memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
204
205         return 0;
206 }
207
208 static int tegra_adma_init(struct tegra_adma *tdma)
209 {
210         u32 status;
211         int ret;
212
213         /* Clear any interrupts */
214         tdma_write(tdma, ADMA_GLOBAL_INT_CLEAR, 0x1);
215
216         /* Assert soft reset */
217         tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
218
219         /* Wait for reset to clear */
220         ret = readx_poll_timeout(readl,
221                                  tdma->base_addr + ADMA_GLOBAL_SOFT_RESET,
222                                  status, status == 0, 20, 10000);
223         if (ret)
224                 return ret;
225
226         /* Enable global ADMA registers */
227         tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
228
229         return 0;
230 }
231
232 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
233                                     enum dma_transfer_direction direction)
234 {
235         struct tegra_adma *tdma = tdc->tdma;
236         unsigned int sreq_index = tdc->sreq_index;
237
238         if (tdc->sreq_reserved)
239                 return tdc->sreq_dir == direction ? 0 : -EINVAL;
240
241         switch (direction) {
242         case DMA_MEM_TO_DEV:
243                 if (sreq_index > ADMA_CH_CTRL_TX_REQ_MAX) {
244                         dev_err(tdma->dev, "invalid DMA request\n");
245                         return -EINVAL;
246                 }
247
248                 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
249                         dev_err(tdma->dev, "DMA request reserved\n");
250                         return -EINVAL;
251                 }
252                 break;
253
254         case DMA_DEV_TO_MEM:
255                 if (sreq_index > ADMA_CH_CTRL_RX_REQ_MAX) {
256                         dev_err(tdma->dev, "invalid DMA request\n");
257                         return -EINVAL;
258                 }
259
260                 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
261                         dev_err(tdma->dev, "DMA request reserved\n");
262                         return -EINVAL;
263                 }
264                 break;
265
266         default:
267                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
268                          dma_chan_name(&tdc->vc.chan));
269                 return -EINVAL;
270         }
271
272         tdc->sreq_dir = direction;
273         tdc->sreq_reserved = true;
274
275         return 0;
276 }
277
278 static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
279 {
280         struct tegra_adma *tdma = tdc->tdma;
281
282         if (!tdc->sreq_reserved)
283                 return;
284
285         switch (tdc->sreq_dir) {
286         case DMA_MEM_TO_DEV:
287                 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
288                 break;
289
290         case DMA_DEV_TO_MEM:
291                 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
292                 break;
293
294         default:
295                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
296                          dma_chan_name(&tdc->vc.chan));
297                 return;
298         }
299
300         tdc->sreq_reserved = false;
301 }
302
303 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
304 {
305         u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
306
307         return status & ADMA_CH_INT_STATUS_XFER_DONE;
308 }
309
310 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
311 {
312         u32 status = tegra_adma_irq_status(tdc);
313
314         if (status)
315                 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
316
317         return status;
318 }
319
320 static void tegra_adma_stop(struct tegra_adma_chan *tdc)
321 {
322         unsigned int status;
323
324         /* Disable ADMA */
325         tdma_ch_write(tdc, ADMA_CH_CMD, 0);
326
327         /* Clear interrupt status */
328         tegra_adma_irq_clear(tdc);
329
330         if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
331                         status, !(status & ADMA_CH_STATUS_XFER_EN),
332                         20, 10000)) {
333                 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
334                 return;
335         }
336
337         kfree(tdc->desc);
338         tdc->desc = NULL;
339 }
340
341 static void tegra_adma_start(struct tegra_adma_chan *tdc)
342 {
343         struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
344         struct tegra_adma_chan_regs *ch_regs;
345         struct tegra_adma_desc *desc;
346
347         if (!vd)
348                 return;
349
350         list_del(&vd->node);
351
352         desc = to_tegra_adma_desc(&vd->tx);
353
354         if (!desc) {
355                 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
356                 return;
357         }
358
359         ch_regs = &desc->ch_regs;
360
361         tdc->tx_buf_pos = 0;
362         tdc->tx_buf_count = 0;
363         tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
364         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
365         tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
366         tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
367         tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
368         tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
369
370         /* Start ADMA */
371         tdma_ch_write(tdc, ADMA_CH_CMD, 1);
372
373         tdc->desc = desc;
374 }
375
376 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
377 {
378         struct tegra_adma_desc *desc = tdc->desc;
379         unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
380         unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
381         unsigned int periods_remaining;
382
383         /*
384          * Handle wrap around of buffer count register
385          */
386         if (pos < tdc->tx_buf_pos)
387                 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
388         else
389                 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
390
391         periods_remaining = tdc->tx_buf_count % desc->num_periods;
392         tdc->tx_buf_pos = pos;
393
394         return desc->buf_len - (periods_remaining * desc->period_len);
395 }
396
397 static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
398 {
399         struct tegra_adma_chan *tdc = dev_id;
400         unsigned long status;
401         unsigned long flags;
402
403         spin_lock_irqsave(&tdc->vc.lock, flags);
404
405         status = tegra_adma_irq_clear(tdc);
406         if (status == 0 || !tdc->desc) {
407                 spin_unlock_irqrestore(&tdc->vc.lock, flags);
408                 return IRQ_NONE;
409         }
410
411         vchan_cyclic_callback(&tdc->desc->vd);
412
413         spin_unlock_irqrestore(&tdc->vc.lock, flags);
414
415         return IRQ_HANDLED;
416 }
417
418 static void tegra_adma_issue_pending(struct dma_chan *dc)
419 {
420         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
421         unsigned long flags;
422
423         spin_lock_irqsave(&tdc->vc.lock, flags);
424
425         if (vchan_issue_pending(&tdc->vc)) {
426                 if (!tdc->desc)
427                         tegra_adma_start(tdc);
428         }
429
430         spin_unlock_irqrestore(&tdc->vc.lock, flags);
431 }
432
433 static int tegra_adma_terminate_all(struct dma_chan *dc)
434 {
435         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
436         unsigned long flags;
437         LIST_HEAD(head);
438
439         spin_lock_irqsave(&tdc->vc.lock, flags);
440
441         if (tdc->desc)
442                 tegra_adma_stop(tdc);
443
444         tegra_adma_request_free(tdc);
445         vchan_get_all_descriptors(&tdc->vc, &head);
446         spin_unlock_irqrestore(&tdc->vc.lock, flags);
447         vchan_dma_desc_free_list(&tdc->vc, &head);
448
449         return 0;
450 }
451
452 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
453                                             dma_cookie_t cookie,
454                                             struct dma_tx_state *txstate)
455 {
456         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
457         struct tegra_adma_desc *desc;
458         struct virt_dma_desc *vd;
459         enum dma_status ret;
460         unsigned long flags;
461         unsigned int residual;
462
463         ret = dma_cookie_status(dc, cookie, txstate);
464         if (ret == DMA_COMPLETE || !txstate)
465                 return ret;
466
467         spin_lock_irqsave(&tdc->vc.lock, flags);
468
469         vd = vchan_find_desc(&tdc->vc, cookie);
470         if (vd) {
471                 desc = to_tegra_adma_desc(&vd->tx);
472                 residual = desc->ch_regs.tc;
473         } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
474                 residual = tegra_adma_get_residue(tdc);
475         } else {
476                 residual = 0;
477         }
478
479         spin_unlock_irqrestore(&tdc->vc.lock, flags);
480
481         dma_set_residue(txstate, residual);
482
483         return ret;
484 }
485
486 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
487                                       struct tegra_adma_desc *desc,
488                                       dma_addr_t buf_addr,
489                                       enum dma_transfer_direction direction)
490 {
491         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
492         unsigned int burst_size, adma_dir;
493
494         if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
495                 return -EINVAL;
496
497         switch (direction) {
498         case DMA_MEM_TO_DEV:
499                 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
500                 burst_size = fls(tdc->sconfig.dst_maxburst);
501                 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
502                 ch_regs->ctrl = ADMA_CH_CTRL_TX_REQ(tdc->sreq_index);
503                 ch_regs->src_addr = buf_addr;
504                 break;
505
506         case DMA_DEV_TO_MEM:
507                 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
508                 burst_size = fls(tdc->sconfig.src_maxburst);
509                 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
510                 ch_regs->ctrl = ADMA_CH_CTRL_RX_REQ(tdc->sreq_index);
511                 ch_regs->trg_addr = buf_addr;
512                 break;
513
514         default:
515                 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
516                 return -EINVAL;
517         }
518
519         if (!burst_size || burst_size > ADMA_CH_CONFIG_BURST_16)
520                 burst_size = ADMA_CH_CONFIG_BURST_16;
521
522         ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
523                          ADMA_CH_CTRL_MODE_CONTINUOUS |
524                          ADMA_CH_CTRL_FLOWCTRL_EN;
525         ch_regs->config |= ADMA_CH_CONFIG_BURST_SIZE(burst_size);
526         ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
527         ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
528         ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
529
530         return tegra_adma_request_alloc(tdc, direction);
531 }
532
533 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
534         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
535         size_t period_len, enum dma_transfer_direction direction,
536         unsigned long flags)
537 {
538         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
539         struct tegra_adma_desc *desc = NULL;
540
541         if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
542                 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
543                 return NULL;
544         }
545
546         if (buf_len % period_len) {
547                 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
548                 return NULL;
549         }
550
551         if (!IS_ALIGNED(buf_addr, 4)) {
552                 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
553                 return NULL;
554         }
555
556         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
557         if (!desc)
558                 return NULL;
559
560         desc->buf_len = buf_len;
561         desc->period_len = period_len;
562         desc->num_periods = buf_len / period_len;
563
564         if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
565                 kfree(desc);
566                 return NULL;
567         }
568
569         return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
570 }
571
572 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
573 {
574         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
575         int ret;
576
577         ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
578         if (ret) {
579                 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
580                         dma_chan_name(dc));
581                 return ret;
582         }
583
584         ret = pm_runtime_get_sync(tdc2dev(tdc));
585         if (ret < 0) {
586                 pm_runtime_put_noidle(tdc2dev(tdc));
587                 free_irq(tdc->irq, tdc);
588                 return ret;
589         }
590
591         dma_cookie_init(&tdc->vc.chan);
592
593         return 0;
594 }
595
596 static void tegra_adma_free_chan_resources(struct dma_chan *dc)
597 {
598         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
599
600         tegra_adma_terminate_all(dc);
601         vchan_free_chan_resources(&tdc->vc);
602         tasklet_kill(&tdc->vc.task);
603         free_irq(tdc->irq, tdc);
604         pm_runtime_put(tdc2dev(tdc));
605
606         tdc->sreq_index = 0;
607         tdc->sreq_dir = DMA_TRANS_NONE;
608 }
609
610 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
611                                            struct of_dma *ofdma)
612 {
613         struct tegra_adma *tdma = ofdma->of_dma_data;
614         struct tegra_adma_chan *tdc;
615         struct dma_chan *chan;
616         unsigned int sreq_index;
617
618         if (dma_spec->args_count != 1)
619                 return NULL;
620
621         sreq_index = dma_spec->args[0];
622
623         if (sreq_index == 0) {
624                 dev_err(tdma->dev, "DMA request must not be 0\n");
625                 return NULL;
626         }
627
628         chan = dma_get_any_slave_channel(&tdma->dma_dev);
629         if (!chan)
630                 return NULL;
631
632         tdc = to_tegra_adma_chan(chan);
633         tdc->sreq_index = sreq_index;
634
635         return chan;
636 }
637
638 static int tegra_adma_runtime_suspend(struct device *dev)
639 {
640         struct tegra_adma *tdma = dev_get_drvdata(dev);
641         struct tegra_adma_chan_regs *ch_reg;
642         struct tegra_adma_chan *tdc;
643         int i;
644
645         tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
646         if (!tdma->global_cmd)
647                 goto clk_disable;
648
649         for (i = 0; i < tdma->nr_channels; i++) {
650                 tdc = &tdma->channels[i];
651                 ch_reg = &tdc->ch_regs;
652                 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
653                 /* skip if channel is not active */
654                 if (!ch_reg->cmd)
655                         continue;
656                 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
657                 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
658                 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
659                 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
660                 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
661                 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
662         }
663
664 clk_disable:
665         clk_disable_unprepare(tdma->ahub_clk);
666
667         return 0;
668 }
669
670 static int tegra_adma_runtime_resume(struct device *dev)
671 {
672         struct tegra_adma *tdma = dev_get_drvdata(dev);
673         struct tegra_adma_chan_regs *ch_reg;
674         struct tegra_adma_chan *tdc;
675         int ret, i;
676
677         ret = clk_prepare_enable(tdma->ahub_clk);
678         if (ret) {
679                 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
680                 return ret;
681         }
682         tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
683
684         if (!tdma->global_cmd)
685                 return 0;
686
687         for (i = 0; i < tdma->nr_channels; i++) {
688                 tdc = &tdma->channels[i];
689                 ch_reg = &tdc->ch_regs;
690                 /* skip if channel was not active earlier */
691                 if (!ch_reg->cmd)
692                         continue;
693                 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
694                 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
695                 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
696                 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
697                 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
698                 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
699                 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
700         }
701
702         return 0;
703 }
704
705 static const struct tegra_adma_chip_data tegra210_chip_data = {
706         .nr_channels = 22,
707 };
708
709 static const struct of_device_id tegra_adma_of_match[] = {
710         { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
711         { },
712 };
713 MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
714
715 static int tegra_adma_probe(struct platform_device *pdev)
716 {
717         const struct tegra_adma_chip_data *cdata;
718         struct tegra_adma *tdma;
719         struct resource *res;
720         int ret, i;
721
722         cdata = of_device_get_match_data(&pdev->dev);
723         if (!cdata) {
724                 dev_err(&pdev->dev, "device match data not found\n");
725                 return -ENODEV;
726         }
727
728         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
729                             sizeof(struct tegra_adma_chan), GFP_KERNEL);
730         if (!tdma)
731                 return -ENOMEM;
732
733         tdma->dev = &pdev->dev;
734         tdma->nr_channels = cdata->nr_channels;
735         platform_set_drvdata(pdev, tdma);
736
737         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
739         if (IS_ERR(tdma->base_addr))
740                 return PTR_ERR(tdma->base_addr);
741
742         tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
743         if (IS_ERR(tdma->ahub_clk)) {
744                 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
745                 return PTR_ERR(tdma->ahub_clk);
746         }
747
748         INIT_LIST_HEAD(&tdma->dma_dev.channels);
749         for (i = 0; i < tdma->nr_channels; i++) {
750                 struct tegra_adma_chan *tdc = &tdma->channels[i];
751
752                 tdc->chan_addr = tdma->base_addr + ADMA_CH_REG_OFFSET(i);
753
754                 tdc->irq = of_irq_get(pdev->dev.of_node, i);
755                 if (tdc->irq < 0) {
756                         ret = tdc->irq;
757                         goto irq_dispose;
758                 }
759
760                 vchan_init(&tdc->vc, &tdma->dma_dev);
761                 tdc->vc.desc_free = tegra_adma_desc_free;
762                 tdc->tdma = tdma;
763         }
764
765         pm_runtime_enable(&pdev->dev);
766
767         ret = pm_runtime_get_sync(&pdev->dev);
768         if (ret < 0) {
769                 pm_runtime_put_noidle(&pdev->dev);
770                 goto rpm_disable;
771         }
772
773         ret = tegra_adma_init(tdma);
774         if (ret)
775                 goto rpm_put;
776
777         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
778         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
779         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
780
781         tdma->dma_dev.dev = &pdev->dev;
782         tdma->dma_dev.device_alloc_chan_resources =
783                                         tegra_adma_alloc_chan_resources;
784         tdma->dma_dev.device_free_chan_resources =
785                                         tegra_adma_free_chan_resources;
786         tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
787         tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
788         tdma->dma_dev.device_config = tegra_adma_slave_config;
789         tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
790         tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
791         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
792         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
793         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
794         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
795
796         ret = dma_async_device_register(&tdma->dma_dev);
797         if (ret < 0) {
798                 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
799                 goto rpm_put;
800         }
801
802         ret = of_dma_controller_register(pdev->dev.of_node,
803                                          tegra_dma_of_xlate, tdma);
804         if (ret < 0) {
805                 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
806                 goto dma_remove;
807         }
808
809         pm_runtime_put(&pdev->dev);
810
811         dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
812                  tdma->nr_channels);
813
814         return 0;
815
816 dma_remove:
817         dma_async_device_unregister(&tdma->dma_dev);
818 rpm_put:
819         pm_runtime_put_sync(&pdev->dev);
820 rpm_disable:
821         pm_runtime_disable(&pdev->dev);
822 irq_dispose:
823         while (--i >= 0)
824                 irq_dispose_mapping(tdma->channels[i].irq);
825
826         return ret;
827 }
828
829 static int tegra_adma_remove(struct platform_device *pdev)
830 {
831         struct tegra_adma *tdma = platform_get_drvdata(pdev);
832         int i;
833
834         of_dma_controller_free(pdev->dev.of_node);
835         dma_async_device_unregister(&tdma->dma_dev);
836
837         for (i = 0; i < tdma->nr_channels; ++i)
838                 irq_dispose_mapping(tdma->channels[i].irq);
839
840         pm_runtime_put_sync(&pdev->dev);
841         pm_runtime_disable(&pdev->dev);
842
843         return 0;
844 }
845
846 #ifdef CONFIG_PM_SLEEP
847 static int tegra_adma_pm_suspend(struct device *dev)
848 {
849         return pm_runtime_suspended(dev) == false;
850 }
851 #endif
852
853 static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
854         SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
855                            tegra_adma_runtime_resume, NULL)
856         SET_SYSTEM_SLEEP_PM_OPS(tegra_adma_pm_suspend, NULL)
857 };
858
859 static struct platform_driver tegra_admac_driver = {
860         .driver = {
861                 .name   = "tegra-adma",
862                 .pm     = &tegra_adma_dev_pm_ops,
863                 .of_match_table = tegra_adma_of_match,
864         },
865         .probe          = tegra_adma_probe,
866         .remove         = tegra_adma_remove,
867 };
868
869 module_platform_driver(tegra_admac_driver);
870
871 MODULE_ALIAS("platform:tegra210-adma");
872 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
873 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
874 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
875 MODULE_LICENSE("GPL v2");