2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
29 #include <linux/module.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/reset.h>
37 #include <linux/slab.h>
39 #include "dmaengine.h"
41 #define TEGRA_APBDMA_GENERAL 0x0
42 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
44 #define TEGRA_APBDMA_CONTROL 0x010
45 #define TEGRA_APBDMA_IRQ_MASK 0x01c
46 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
49 #define TEGRA_APBDMA_CHAN_CSR 0x00
50 #define TEGRA_APBDMA_CSR_ENB BIT(31)
51 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52 #define TEGRA_APBDMA_CSR_HOLD BIT(29)
53 #define TEGRA_APBDMA_CSR_DIR BIT(28)
54 #define TEGRA_APBDMA_CSR_ONCE BIT(27)
55 #define TEGRA_APBDMA_CSR_FLOW BIT(21)
56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
60 #define TEGRA_APBDMA_CHAN_STATUS 0x004
61 #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
62 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
63 #define TEGRA_APBDMA_STATUS_HALT BIT(29)
64 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
65 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
66 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
68 #define TEGRA_APBDMA_CHAN_CSRE 0x00C
69 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
71 /* AHB memory address */
72 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
74 /* AHB sequence register */
75 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
76 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
77 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
82 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
83 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
84 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
85 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
86 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
87 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
88 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
91 #define TEGRA_APBDMA_CHAN_APBPTR 0x018
93 /* APB sequence register */
94 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
95 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
100 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
101 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
103 /* Tegra148 specific registers */
104 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
106 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
109 * If any burst is in flight and DMA paused then this is the time to complete
110 * on-flight burst and update DMA status register.
112 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
114 /* Channel base address offset from APBDMA base address */
115 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
120 * tegra_dma_chip_data Tegra chip specific DMA data
121 * @nr_channels: Number of channels available in the controller.
122 * @channel_reg_size: Channel register size/stride.
123 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
124 * @support_channel_pause: Support channel wise pause of dma.
125 * @support_separate_wcount_reg: Support separate word count register.
127 struct tegra_dma_chip_data {
129 int channel_reg_size;
131 bool support_channel_pause;
132 bool support_separate_wcount_reg;
135 /* DMA channel registers */
136 struct tegra_dma_channel_regs {
138 unsigned long ahb_ptr;
139 unsigned long apb_ptr;
140 unsigned long ahb_seq;
141 unsigned long apb_seq;
142 unsigned long wcount;
146 * tegra_dma_sg_req: Dma request details to configure hardware. This
147 * contains the details for one transfer to configure DMA hw.
148 * The client's request for data transfer can be broken into multiple
149 * sub-transfer as per requester details and hw support.
150 * This sub transfer get added in the list of transfer and point to Tegra
151 * DMA descriptor which manages the transfer details.
153 struct tegra_dma_sg_req {
154 struct tegra_dma_channel_regs ch_regs;
158 struct list_head node;
159 struct tegra_dma_desc *dma_desc;
163 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
164 * This descriptor keep track of transfer status, callbacks and request
167 struct tegra_dma_desc {
168 struct dma_async_tx_descriptor txd;
170 int bytes_transferred;
171 enum dma_status dma_status;
172 struct list_head node;
173 struct list_head tx_list;
174 struct list_head cb_node;
178 struct tegra_dma_channel;
180 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
183 /* tegra_dma_channel: Channel specific information */
184 struct tegra_dma_channel {
185 struct dma_chan dma_chan;
190 void __iomem *chan_addr;
193 struct tegra_dma *tdma;
196 /* Different lists for managing the requests */
197 struct list_head free_sg_req;
198 struct list_head pending_sg_req;
199 struct list_head free_dma_desc;
200 struct list_head cb_desc;
202 /* ISR handler and tasklet for bottom half of isr handling */
203 dma_isr_handler isr_handler;
204 struct tasklet_struct tasklet;
206 /* Channel-slave specific configuration */
207 unsigned int slave_id;
208 struct dma_slave_config dma_sconfig;
209 struct tegra_dma_channel_regs channel_reg;
212 /* tegra_dma: Tegra DMA specific information */
214 struct dma_device dma_dev;
217 struct reset_control *rst;
218 spinlock_t global_lock;
219 void __iomem *base_addr;
220 const struct tegra_dma_chip_data *chip_data;
223 * Counter for managing global pausing of the DMA controller.
224 * Only applicable for devices that don't support individual
227 u32 global_pause_count;
229 /* Some register need to be cache before suspend */
232 /* Last member of the structure */
233 struct tegra_dma_channel channels[0];
236 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
238 writel(val, tdma->base_addr + reg);
241 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
243 return readl(tdma->base_addr + reg);
246 static inline void tdc_write(struct tegra_dma_channel *tdc,
249 writel(val, tdc->chan_addr + reg);
252 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
254 return readl(tdc->chan_addr + reg);
257 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
259 return container_of(dc, struct tegra_dma_channel, dma_chan);
262 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
263 struct dma_async_tx_descriptor *td)
265 return container_of(td, struct tegra_dma_desc, txd);
268 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
270 return &tdc->dma_chan.dev->device;
273 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
274 static int tegra_dma_runtime_suspend(struct device *dev);
275 static int tegra_dma_runtime_resume(struct device *dev);
277 /* Get DMA desc from free list, if not there then allocate it. */
278 static struct tegra_dma_desc *tegra_dma_desc_get(
279 struct tegra_dma_channel *tdc)
281 struct tegra_dma_desc *dma_desc;
284 spin_lock_irqsave(&tdc->lock, flags);
286 /* Do not allocate if desc are waiting for ack */
287 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
288 if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) {
289 list_del(&dma_desc->node);
290 spin_unlock_irqrestore(&tdc->lock, flags);
291 dma_desc->txd.flags = 0;
296 spin_unlock_irqrestore(&tdc->lock, flags);
298 /* Allocate DMA desc */
299 dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
301 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
305 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
306 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
307 dma_desc->txd.flags = 0;
311 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
312 struct tegra_dma_desc *dma_desc)
316 spin_lock_irqsave(&tdc->lock, flags);
317 if (!list_empty(&dma_desc->tx_list))
318 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
319 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
320 spin_unlock_irqrestore(&tdc->lock, flags);
323 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
324 struct tegra_dma_channel *tdc)
326 struct tegra_dma_sg_req *sg_req = NULL;
329 spin_lock_irqsave(&tdc->lock, flags);
330 if (!list_empty(&tdc->free_sg_req)) {
331 sg_req = list_first_entry(&tdc->free_sg_req,
332 typeof(*sg_req), node);
333 list_del(&sg_req->node);
334 spin_unlock_irqrestore(&tdc->lock, flags);
337 spin_unlock_irqrestore(&tdc->lock, flags);
339 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
341 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
345 static int tegra_dma_slave_config(struct dma_chan *dc,
346 struct dma_slave_config *sconfig)
348 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
350 if (!list_empty(&tdc->pending_sg_req)) {
351 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
355 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
357 tdc->slave_id = sconfig->slave_id;
358 tdc->config_init = true;
362 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
363 bool wait_for_burst_complete)
365 struct tegra_dma *tdma = tdc->tdma;
367 spin_lock(&tdma->global_lock);
369 if (tdc->tdma->global_pause_count == 0) {
370 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
371 if (wait_for_burst_complete)
372 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
375 tdc->tdma->global_pause_count++;
377 spin_unlock(&tdma->global_lock);
380 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
382 struct tegra_dma *tdma = tdc->tdma;
384 spin_lock(&tdma->global_lock);
386 if (WARN_ON(tdc->tdma->global_pause_count == 0))
389 if (--tdc->tdma->global_pause_count == 0)
390 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
391 TEGRA_APBDMA_GENERAL_ENABLE);
394 spin_unlock(&tdma->global_lock);
397 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
398 bool wait_for_burst_complete)
400 struct tegra_dma *tdma = tdc->tdma;
402 if (tdma->chip_data->support_channel_pause) {
403 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
404 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
405 if (wait_for_burst_complete)
406 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
408 tegra_dma_global_pause(tdc, wait_for_burst_complete);
412 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
414 struct tegra_dma *tdma = tdc->tdma;
416 if (tdma->chip_data->support_channel_pause) {
417 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
419 tegra_dma_global_resume(tdc);
423 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
428 /* Disable interrupts */
429 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
430 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
434 csr &= ~TEGRA_APBDMA_CSR_ENB;
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
437 /* Clear interrupt status if it is there */
438 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
439 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
440 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
441 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
446 static void tegra_dma_start(struct tegra_dma_channel *tdc,
447 struct tegra_dma_sg_req *sg_req)
449 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
451 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
452 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
453 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
454 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
455 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
456 if (tdc->tdma->chip_data->support_separate_wcount_reg)
457 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
460 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
461 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
464 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
465 struct tegra_dma_sg_req *nsg_req)
467 unsigned long status;
470 * The DMA controller reloads the new configuration for next transfer
471 * after last burst of current transfer completes.
472 * If there is no IEC status then this makes sure that last burst
473 * has not be completed. There may be case that last burst is on
474 * flight and so it can complete but because DMA is paused, it
475 * will not generates interrupt as well as not reload the new
477 * If there is already IEC status then interrupt handler need to
478 * load new configuration.
480 tegra_dma_pause(tdc, false);
481 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
484 * If interrupt is pending then do nothing as the ISR will handle
485 * the programing for new request.
487 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
488 dev_err(tdc2dev(tdc),
489 "Skipping new configuration as interrupt is pending\n");
490 tegra_dma_resume(tdc);
494 /* Safe to program new configuration */
495 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
496 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
497 if (tdc->tdma->chip_data->support_separate_wcount_reg)
498 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
499 nsg_req->ch_regs.wcount);
500 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
501 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
502 nsg_req->configured = true;
504 tegra_dma_resume(tdc);
507 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
509 struct tegra_dma_sg_req *sg_req;
511 if (list_empty(&tdc->pending_sg_req))
514 sg_req = list_first_entry(&tdc->pending_sg_req,
515 typeof(*sg_req), node);
516 tegra_dma_start(tdc, sg_req);
517 sg_req->configured = true;
521 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
523 struct tegra_dma_sg_req *hsgreq;
524 struct tegra_dma_sg_req *hnsgreq;
526 if (list_empty(&tdc->pending_sg_req))
529 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
530 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
531 hnsgreq = list_first_entry(&hsgreq->node,
532 typeof(*hnsgreq), node);
533 tegra_dma_configure_for_next(tdc, hnsgreq);
537 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
538 struct tegra_dma_sg_req *sg_req, unsigned long status)
540 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
543 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
545 struct tegra_dma_sg_req *sgreq;
546 struct tegra_dma_desc *dma_desc;
548 while (!list_empty(&tdc->pending_sg_req)) {
549 sgreq = list_first_entry(&tdc->pending_sg_req,
550 typeof(*sgreq), node);
551 list_move_tail(&sgreq->node, &tdc->free_sg_req);
552 if (sgreq->last_sg) {
553 dma_desc = sgreq->dma_desc;
554 dma_desc->dma_status = DMA_ERROR;
555 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
557 /* Add in cb list if it is not there. */
558 if (!dma_desc->cb_count)
559 list_add_tail(&dma_desc->cb_node,
561 dma_desc->cb_count++;
564 tdc->isr_handler = NULL;
567 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
568 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
570 struct tegra_dma_sg_req *hsgreq = NULL;
572 if (list_empty(&tdc->pending_sg_req)) {
573 dev_err(tdc2dev(tdc), "Dma is running without req\n");
579 * Check that head req on list should be in flight.
580 * If it is not in flight then abort transfer as
581 * looping of transfer can not continue.
583 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
584 if (!hsgreq->configured) {
586 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
587 tegra_dma_abort_all(tdc);
591 /* Configure next request */
593 tdc_configure_next_head_desc(tdc);
597 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
600 struct tegra_dma_sg_req *sgreq;
601 struct tegra_dma_desc *dma_desc;
604 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
605 dma_desc = sgreq->dma_desc;
606 dma_desc->bytes_transferred += sgreq->req_len;
608 list_del(&sgreq->node);
609 if (sgreq->last_sg) {
610 dma_desc->dma_status = DMA_COMPLETE;
611 dma_cookie_complete(&dma_desc->txd);
612 if (!dma_desc->cb_count)
613 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
614 dma_desc->cb_count++;
615 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
617 list_add_tail(&sgreq->node, &tdc->free_sg_req);
619 /* Do not start DMA if it is going to be terminate */
620 if (to_terminate || list_empty(&tdc->pending_sg_req))
623 tdc_start_head_req(tdc);
626 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
629 struct tegra_dma_sg_req *sgreq;
630 struct tegra_dma_desc *dma_desc;
633 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
634 dma_desc = sgreq->dma_desc;
635 /* if we dma for long enough the transfer count will wrap */
636 dma_desc->bytes_transferred =
637 (dma_desc->bytes_transferred + sgreq->req_len) %
638 dma_desc->bytes_requested;
640 /* Callback need to be call */
641 if (!dma_desc->cb_count)
642 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
643 dma_desc->cb_count++;
645 /* If not last req then put at end of pending list */
646 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
647 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
648 sgreq->configured = false;
649 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
651 dma_desc->dma_status = DMA_ERROR;
655 static void tegra_dma_tasklet(unsigned long data)
657 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
658 dma_async_tx_callback callback = NULL;
659 void *callback_param = NULL;
660 struct tegra_dma_desc *dma_desc;
664 spin_lock_irqsave(&tdc->lock, flags);
665 while (!list_empty(&tdc->cb_desc)) {
666 dma_desc = list_first_entry(&tdc->cb_desc,
667 typeof(*dma_desc), cb_node);
668 list_del(&dma_desc->cb_node);
669 callback = dma_desc->txd.callback;
670 callback_param = dma_desc->txd.callback_param;
671 cb_count = dma_desc->cb_count;
672 dma_desc->cb_count = 0;
673 spin_unlock_irqrestore(&tdc->lock, flags);
674 while (cb_count-- && callback)
675 callback(callback_param);
676 spin_lock_irqsave(&tdc->lock, flags);
678 spin_unlock_irqrestore(&tdc->lock, flags);
681 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
683 struct tegra_dma_channel *tdc = dev_id;
684 unsigned long status;
687 spin_lock_irqsave(&tdc->lock, flags);
689 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
690 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
691 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
692 tdc->isr_handler(tdc, false);
693 tasklet_schedule(&tdc->tasklet);
694 spin_unlock_irqrestore(&tdc->lock, flags);
698 spin_unlock_irqrestore(&tdc->lock, flags);
699 dev_info(tdc2dev(tdc),
700 "Interrupt already served status 0x%08lx\n", status);
704 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
706 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
707 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
711 spin_lock_irqsave(&tdc->lock, flags);
712 dma_desc->dma_status = DMA_IN_PROGRESS;
713 cookie = dma_cookie_assign(&dma_desc->txd);
714 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
715 spin_unlock_irqrestore(&tdc->lock, flags);
719 static void tegra_dma_issue_pending(struct dma_chan *dc)
721 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
724 spin_lock_irqsave(&tdc->lock, flags);
725 if (list_empty(&tdc->pending_sg_req)) {
726 dev_err(tdc2dev(tdc), "No DMA request\n");
730 tdc_start_head_req(tdc);
732 /* Continuous single mode: Configure next req */
735 * Wait for 1 burst time for configure DMA for
738 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
739 tdc_configure_next_head_desc(tdc);
743 spin_unlock_irqrestore(&tdc->lock, flags);
746 static int tegra_dma_terminate_all(struct dma_chan *dc)
748 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
749 struct tegra_dma_sg_req *sgreq;
750 struct tegra_dma_desc *dma_desc;
752 unsigned long status;
753 unsigned long wcount;
756 spin_lock_irqsave(&tdc->lock, flags);
761 /* Pause DMA before checking the queue status */
762 tegra_dma_pause(tdc, true);
764 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
765 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
766 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
767 tdc->isr_handler(tdc, true);
768 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
770 if (tdc->tdma->chip_data->support_separate_wcount_reg)
771 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
775 was_busy = tdc->busy;
778 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
779 sgreq = list_first_entry(&tdc->pending_sg_req,
780 typeof(*sgreq), node);
781 sgreq->dma_desc->bytes_transferred +=
782 get_current_xferred_count(tdc, sgreq, wcount);
784 tegra_dma_resume(tdc);
787 tegra_dma_abort_all(tdc);
789 while (!list_empty(&tdc->cb_desc)) {
790 dma_desc = list_first_entry(&tdc->cb_desc,
791 typeof(*dma_desc), cb_node);
792 list_del(&dma_desc->cb_node);
793 dma_desc->cb_count = 0;
795 spin_unlock_irqrestore(&tdc->lock, flags);
799 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
800 dma_cookie_t cookie, struct dma_tx_state *txstate)
802 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
803 struct tegra_dma_desc *dma_desc;
804 struct tegra_dma_sg_req *sg_req;
807 unsigned int residual;
809 ret = dma_cookie_status(dc, cookie, txstate);
810 if (ret == DMA_COMPLETE)
813 spin_lock_irqsave(&tdc->lock, flags);
815 /* Check on wait_ack desc status */
816 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
817 if (dma_desc->txd.cookie == cookie) {
818 residual = dma_desc->bytes_requested -
819 (dma_desc->bytes_transferred %
820 dma_desc->bytes_requested);
821 dma_set_residue(txstate, residual);
822 ret = dma_desc->dma_status;
823 spin_unlock_irqrestore(&tdc->lock, flags);
828 /* Check in pending list */
829 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
830 dma_desc = sg_req->dma_desc;
831 if (dma_desc->txd.cookie == cookie) {
832 residual = dma_desc->bytes_requested -
833 (dma_desc->bytes_transferred %
834 dma_desc->bytes_requested);
835 dma_set_residue(txstate, residual);
836 ret = dma_desc->dma_status;
837 spin_unlock_irqrestore(&tdc->lock, flags);
842 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
843 spin_unlock_irqrestore(&tdc->lock, flags);
847 static inline int get_bus_width(struct tegra_dma_channel *tdc,
848 enum dma_slave_buswidth slave_bw)
851 case DMA_SLAVE_BUSWIDTH_1_BYTE:
852 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
853 case DMA_SLAVE_BUSWIDTH_2_BYTES:
854 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
855 case DMA_SLAVE_BUSWIDTH_4_BYTES:
856 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
857 case DMA_SLAVE_BUSWIDTH_8_BYTES:
858 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
860 dev_warn(tdc2dev(tdc),
861 "slave bw is not supported, using 32bits\n");
862 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
866 static inline int get_burst_size(struct tegra_dma_channel *tdc,
867 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
873 * burst_size from client is in terms of the bus_width.
874 * convert them into AHB memory width which is 4 byte.
876 burst_byte = burst_size * slave_bw;
877 burst_ahb_width = burst_byte / 4;
879 /* If burst size is 0 then calculate the burst size based on length */
880 if (!burst_ahb_width) {
882 return TEGRA_APBDMA_AHBSEQ_BURST_1;
883 else if ((len >> 4) & 0x1)
884 return TEGRA_APBDMA_AHBSEQ_BURST_4;
886 return TEGRA_APBDMA_AHBSEQ_BURST_8;
888 if (burst_ahb_width < 4)
889 return TEGRA_APBDMA_AHBSEQ_BURST_1;
890 else if (burst_ahb_width < 8)
891 return TEGRA_APBDMA_AHBSEQ_BURST_4;
893 return TEGRA_APBDMA_AHBSEQ_BURST_8;
896 static int get_transfer_param(struct tegra_dma_channel *tdc,
897 enum dma_transfer_direction direction, unsigned long *apb_addr,
898 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
899 enum dma_slave_buswidth *slave_bw)
904 *apb_addr = tdc->dma_sconfig.dst_addr;
905 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
906 *burst_size = tdc->dma_sconfig.dst_maxburst;
907 *slave_bw = tdc->dma_sconfig.dst_addr_width;
908 *csr = TEGRA_APBDMA_CSR_DIR;
912 *apb_addr = tdc->dma_sconfig.src_addr;
913 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
914 *burst_size = tdc->dma_sconfig.src_maxburst;
915 *slave_bw = tdc->dma_sconfig.src_addr_width;
920 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
926 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
927 struct tegra_dma_channel_regs *ch_regs, u32 len)
929 u32 len_field = (len - 4) & 0xFFFC;
931 if (tdc->tdma->chip_data->support_separate_wcount_reg)
932 ch_regs->wcount = len_field;
934 ch_regs->csr |= len_field;
937 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
938 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
939 enum dma_transfer_direction direction, unsigned long flags,
942 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
943 struct tegra_dma_desc *dma_desc;
945 struct scatterlist *sg;
946 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
947 struct list_head req_list;
948 struct tegra_dma_sg_req *sg_req = NULL;
950 enum dma_slave_buswidth slave_bw;
952 if (!tdc->config_init) {
953 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
957 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
961 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
962 &burst_size, &slave_bw) < 0)
965 INIT_LIST_HEAD(&req_list);
967 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
968 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
969 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
970 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
972 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
973 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
974 if (flags & DMA_PREP_INTERRUPT)
975 csr |= TEGRA_APBDMA_CSR_IE_EOC;
977 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
979 dma_desc = tegra_dma_desc_get(tdc);
981 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
984 INIT_LIST_HEAD(&dma_desc->tx_list);
985 INIT_LIST_HEAD(&dma_desc->cb_node);
986 dma_desc->cb_count = 0;
987 dma_desc->bytes_requested = 0;
988 dma_desc->bytes_transferred = 0;
989 dma_desc->dma_status = DMA_IN_PROGRESS;
991 /* Make transfer requests */
992 for_each_sg(sgl, sg, sg_len, i) {
995 mem = sg_dma_address(sg);
996 len = sg_dma_len(sg);
998 if ((len & 3) || (mem & 3) ||
999 (len > tdc->tdma->chip_data->max_dma_count)) {
1000 dev_err(tdc2dev(tdc),
1001 "Dma length/memory address is not supported\n");
1002 tegra_dma_desc_put(tdc, dma_desc);
1006 sg_req = tegra_dma_sg_req_get(tdc);
1008 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1009 tegra_dma_desc_put(tdc, dma_desc);
1013 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1014 dma_desc->bytes_requested += len;
1016 sg_req->ch_regs.apb_ptr = apb_ptr;
1017 sg_req->ch_regs.ahb_ptr = mem;
1018 sg_req->ch_regs.csr = csr;
1019 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1020 sg_req->ch_regs.apb_seq = apb_seq;
1021 sg_req->ch_regs.ahb_seq = ahb_seq;
1022 sg_req->configured = false;
1023 sg_req->last_sg = false;
1024 sg_req->dma_desc = dma_desc;
1025 sg_req->req_len = len;
1027 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1029 sg_req->last_sg = true;
1030 if (flags & DMA_CTRL_ACK)
1031 dma_desc->txd.flags = DMA_CTRL_ACK;
1034 * Make sure that mode should not be conflicting with currently
1037 if (!tdc->isr_handler) {
1038 tdc->isr_handler = handle_once_dma_done;
1039 tdc->cyclic = false;
1042 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1043 tegra_dma_desc_put(tdc, dma_desc);
1048 return &dma_desc->txd;
1051 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1052 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1053 size_t period_len, enum dma_transfer_direction direction,
1054 unsigned long flags)
1056 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1057 struct tegra_dma_desc *dma_desc = NULL;
1058 struct tegra_dma_sg_req *sg_req = NULL;
1059 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1062 dma_addr_t mem = buf_addr;
1064 enum dma_slave_buswidth slave_bw;
1066 if (!buf_len || !period_len) {
1067 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1071 if (!tdc->config_init) {
1072 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1077 * We allow to take more number of requests till DMA is
1078 * not started. The driver will loop over all requests.
1079 * Once DMA is started then new requests can be queued only after
1080 * terminating the DMA.
1083 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1088 * We only support cycle transfer when buf_len is multiple of
1091 if (buf_len % period_len) {
1092 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1097 if ((len & 3) || (buf_addr & 3) ||
1098 (len > tdc->tdma->chip_data->max_dma_count)) {
1099 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1103 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1104 &burst_size, &slave_bw) < 0)
1107 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1108 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1109 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1110 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1112 csr |= TEGRA_APBDMA_CSR_FLOW;
1113 if (flags & DMA_PREP_INTERRUPT)
1114 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1115 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1117 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1119 dma_desc = tegra_dma_desc_get(tdc);
1121 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1125 INIT_LIST_HEAD(&dma_desc->tx_list);
1126 INIT_LIST_HEAD(&dma_desc->cb_node);
1127 dma_desc->cb_count = 0;
1129 dma_desc->bytes_transferred = 0;
1130 dma_desc->bytes_requested = buf_len;
1131 remain_len = buf_len;
1133 /* Split transfer equal to period size */
1134 while (remain_len) {
1135 sg_req = tegra_dma_sg_req_get(tdc);
1137 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1138 tegra_dma_desc_put(tdc, dma_desc);
1142 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1143 sg_req->ch_regs.apb_ptr = apb_ptr;
1144 sg_req->ch_regs.ahb_ptr = mem;
1145 sg_req->ch_regs.csr = csr;
1146 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1147 sg_req->ch_regs.apb_seq = apb_seq;
1148 sg_req->ch_regs.ahb_seq = ahb_seq;
1149 sg_req->configured = false;
1150 sg_req->last_sg = false;
1151 sg_req->dma_desc = dma_desc;
1152 sg_req->req_len = len;
1154 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1158 sg_req->last_sg = true;
1159 if (flags & DMA_CTRL_ACK)
1160 dma_desc->txd.flags = DMA_CTRL_ACK;
1163 * Make sure that mode should not be conflicting with currently
1166 if (!tdc->isr_handler) {
1167 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1171 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1172 tegra_dma_desc_put(tdc, dma_desc);
1177 return &dma_desc->txd;
1180 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1182 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1183 struct tegra_dma *tdma = tdc->tdma;
1186 dma_cookie_init(&tdc->dma_chan);
1187 tdc->config_init = false;
1188 ret = clk_prepare_enable(tdma->dma_clk);
1190 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1194 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1196 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1197 struct tegra_dma *tdma = tdc->tdma;
1199 struct tegra_dma_desc *dma_desc;
1200 struct tegra_dma_sg_req *sg_req;
1201 struct list_head dma_desc_list;
1202 struct list_head sg_req_list;
1203 unsigned long flags;
1205 INIT_LIST_HEAD(&dma_desc_list);
1206 INIT_LIST_HEAD(&sg_req_list);
1208 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1210 tegra_dma_terminate_all(dc);
1212 spin_lock_irqsave(&tdc->lock, flags);
1213 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1214 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1215 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1216 INIT_LIST_HEAD(&tdc->cb_desc);
1217 tdc->config_init = false;
1218 tdc->isr_handler = NULL;
1219 spin_unlock_irqrestore(&tdc->lock, flags);
1221 while (!list_empty(&dma_desc_list)) {
1222 dma_desc = list_first_entry(&dma_desc_list,
1223 typeof(*dma_desc), node);
1224 list_del(&dma_desc->node);
1228 while (!list_empty(&sg_req_list)) {
1229 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1230 list_del(&sg_req->node);
1233 clk_disable_unprepare(tdma->dma_clk);
1238 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1239 struct of_dma *ofdma)
1241 struct tegra_dma *tdma = ofdma->of_dma_data;
1242 struct dma_chan *chan;
1243 struct tegra_dma_channel *tdc;
1245 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1249 tdc = to_tegra_dma_chan(chan);
1250 tdc->slave_id = dma_spec->args[0];
1255 /* Tegra20 specific DMA controller information */
1256 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1258 .channel_reg_size = 0x20,
1259 .max_dma_count = 1024UL * 64,
1260 .support_channel_pause = false,
1261 .support_separate_wcount_reg = false,
1264 /* Tegra30 specific DMA controller information */
1265 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1267 .channel_reg_size = 0x20,
1268 .max_dma_count = 1024UL * 64,
1269 .support_channel_pause = false,
1270 .support_separate_wcount_reg = false,
1273 /* Tegra114 specific DMA controller information */
1274 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1276 .channel_reg_size = 0x20,
1277 .max_dma_count = 1024UL * 64,
1278 .support_channel_pause = true,
1279 .support_separate_wcount_reg = false,
1282 /* Tegra148 specific DMA controller information */
1283 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1285 .channel_reg_size = 0x40,
1286 .max_dma_count = 1024UL * 64,
1287 .support_channel_pause = true,
1288 .support_separate_wcount_reg = true,
1292 static const struct of_device_id tegra_dma_of_match[] = {
1294 .compatible = "nvidia,tegra148-apbdma",
1295 .data = &tegra148_dma_chip_data,
1297 .compatible = "nvidia,tegra114-apbdma",
1298 .data = &tegra114_dma_chip_data,
1300 .compatible = "nvidia,tegra30-apbdma",
1301 .data = &tegra30_dma_chip_data,
1303 .compatible = "nvidia,tegra20-apbdma",
1304 .data = &tegra20_dma_chip_data,
1308 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1310 static int tegra_dma_probe(struct platform_device *pdev)
1312 struct resource *res;
1313 struct tegra_dma *tdma;
1316 const struct tegra_dma_chip_data *cdata = NULL;
1317 const struct of_device_id *match;
1319 match = of_match_device(tegra_dma_of_match, &pdev->dev);
1321 dev_err(&pdev->dev, "Error: No device match found\n");
1324 cdata = match->data;
1326 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1327 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1329 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1333 tdma->dev = &pdev->dev;
1334 tdma->chip_data = cdata;
1335 platform_set_drvdata(pdev, tdma);
1337 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1339 if (IS_ERR(tdma->base_addr))
1340 return PTR_ERR(tdma->base_addr);
1342 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1343 if (IS_ERR(tdma->dma_clk)) {
1344 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1345 return PTR_ERR(tdma->dma_clk);
1348 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1349 if (IS_ERR(tdma->rst)) {
1350 dev_err(&pdev->dev, "Error: Missing reset\n");
1351 return PTR_ERR(tdma->rst);
1354 spin_lock_init(&tdma->global_lock);
1356 pm_runtime_enable(&pdev->dev);
1357 if (!pm_runtime_enabled(&pdev->dev)) {
1358 ret = tegra_dma_runtime_resume(&pdev->dev);
1360 dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1362 goto err_pm_disable;
1366 /* Enable clock before accessing registers */
1367 ret = clk_prepare_enable(tdma->dma_clk);
1369 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1370 goto err_pm_disable;
1373 /* Reset DMA controller */
1374 reset_control_assert(tdma->rst);
1376 reset_control_deassert(tdma->rst);
1378 /* Enable global DMA registers */
1379 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1380 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1381 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1383 clk_disable_unprepare(tdma->dma_clk);
1385 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1386 for (i = 0; i < cdata->nr_channels; i++) {
1387 struct tegra_dma_channel *tdc = &tdma->channels[i];
1389 tdc->chan_addr = tdma->base_addr +
1390 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1391 (i * cdata->channel_reg_size);
1393 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1396 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1399 tdc->irq = res->start;
1400 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1401 ret = devm_request_irq(&pdev->dev, tdc->irq,
1402 tegra_dma_isr, 0, tdc->name, tdc);
1405 "request_irq failed with err %d channel %d\n",
1410 tdc->dma_chan.device = &tdma->dma_dev;
1411 dma_cookie_init(&tdc->dma_chan);
1412 list_add_tail(&tdc->dma_chan.device_node,
1413 &tdma->dma_dev.channels);
1417 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1418 (unsigned long)tdc);
1419 spin_lock_init(&tdc->lock);
1421 INIT_LIST_HEAD(&tdc->pending_sg_req);
1422 INIT_LIST_HEAD(&tdc->free_sg_req);
1423 INIT_LIST_HEAD(&tdc->free_dma_desc);
1424 INIT_LIST_HEAD(&tdc->cb_desc);
1427 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1428 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1429 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1431 tdma->global_pause_count = 0;
1432 tdma->dma_dev.dev = &pdev->dev;
1433 tdma->dma_dev.device_alloc_chan_resources =
1434 tegra_dma_alloc_chan_resources;
1435 tdma->dma_dev.device_free_chan_resources =
1436 tegra_dma_free_chan_resources;
1437 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1438 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1439 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1440 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1441 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1442 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1443 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1444 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1445 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1446 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1447 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1449 * XXX The hardware appears to support
1450 * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1451 * only used by this driver during tegra_dma_terminate_all()
1453 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1454 tdma->dma_dev.device_config = tegra_dma_slave_config;
1455 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1456 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1457 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1459 ret = dma_async_device_register(&tdma->dma_dev);
1462 "Tegra20 APB DMA driver registration failed %d\n", ret);
1466 ret = of_dma_controller_register(pdev->dev.of_node,
1467 tegra_dma_of_xlate, tdma);
1470 "Tegra20 APB DMA OF registration failed %d\n", ret);
1471 goto err_unregister_dma_dev;
1474 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1475 cdata->nr_channels);
1478 err_unregister_dma_dev:
1479 dma_async_device_unregister(&tdma->dma_dev);
1482 struct tegra_dma_channel *tdc = &tdma->channels[i];
1483 tasklet_kill(&tdc->tasklet);
1487 pm_runtime_disable(&pdev->dev);
1488 if (!pm_runtime_status_suspended(&pdev->dev))
1489 tegra_dma_runtime_suspend(&pdev->dev);
1493 static int tegra_dma_remove(struct platform_device *pdev)
1495 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1497 struct tegra_dma_channel *tdc;
1499 dma_async_device_unregister(&tdma->dma_dev);
1501 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1502 tdc = &tdma->channels[i];
1503 tasklet_kill(&tdc->tasklet);
1506 pm_runtime_disable(&pdev->dev);
1507 if (!pm_runtime_status_suspended(&pdev->dev))
1508 tegra_dma_runtime_suspend(&pdev->dev);
1513 static int tegra_dma_runtime_suspend(struct device *dev)
1515 struct platform_device *pdev = to_platform_device(dev);
1516 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1518 clk_disable_unprepare(tdma->dma_clk);
1522 static int tegra_dma_runtime_resume(struct device *dev)
1524 struct platform_device *pdev = to_platform_device(dev);
1525 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1528 ret = clk_prepare_enable(tdma->dma_clk);
1530 dev_err(dev, "clk_enable failed: %d\n", ret);
1536 #ifdef CONFIG_PM_SLEEP
1537 static int tegra_dma_pm_suspend(struct device *dev)
1539 struct tegra_dma *tdma = dev_get_drvdata(dev);
1543 /* Enable clock before accessing register */
1544 ret = tegra_dma_runtime_resume(dev);
1548 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1549 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1550 struct tegra_dma_channel *tdc = &tdma->channels[i];
1551 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1553 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1554 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1555 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1556 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1557 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1561 tegra_dma_runtime_suspend(dev);
1565 static int tegra_dma_pm_resume(struct device *dev)
1567 struct tegra_dma *tdma = dev_get_drvdata(dev);
1571 /* Enable clock before accessing register */
1572 ret = tegra_dma_runtime_resume(dev);
1576 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1577 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1578 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1580 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1581 struct tegra_dma_channel *tdc = &tdma->channels[i];
1582 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1584 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1585 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1586 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1587 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1588 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1589 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1593 tegra_dma_runtime_suspend(dev);
1598 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1600 .runtime_suspend = tegra_dma_runtime_suspend,
1601 .runtime_resume = tegra_dma_runtime_resume,
1603 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1606 static struct platform_driver tegra_dmac_driver = {
1608 .name = "tegra-apbdma",
1609 .pm = &tegra_dma_dev_pm_ops,
1610 .of_match_table = tegra_dma_of_match,
1612 .probe = tegra_dma_probe,
1613 .remove = tegra_dma_remove,
1616 module_platform_driver(tegra_dmac_driver);
1618 MODULE_ALIAS("platform:tegra20-apbdma");
1619 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1620 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1621 MODULE_LICENSE("GPL v2");