drivers/dma/stm32-dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for STM32 DMA controller
   4  *
   5  * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   6  *
   7  * Copyright (C) M'boumba Cedric Madianga 2015
   8  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   9  *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30
  31 #include "virt-dma.h"
  32
  33 #define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  34 #define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  35 #define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  36 #define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  37 #define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  38 #define STM32_DMA_HTI                   BIT(4) /* Half Transfer Interrupt */
  39 #define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  40 #define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  41 #define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  42 #define STM32_DMA_MASKI                 (STM32_DMA_TCI \
  43                                          | STM32_DMA_TEI \
  44                                          | STM32_DMA_DMEI \
  45                                          | STM32_DMA_FEI)
  46
  47 /* DMA Stream x Configuration Register */
  48 #define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  49 #define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  50 #define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  51 #define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  52 #define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  53 #define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  54 #define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  55 #define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  56 #define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  57 #define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  58 #define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  59 #define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  60 #define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  61 #define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  62 #define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  63 #define STM32_DMA_SCR_TRBUFF            BIT(20) /* Bufferable transfer for USART/UART */
  64 #define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  65 #define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  66 #define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  67 #define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  68 #define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  69 #define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  70 #define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  71 #define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Complete Int Enable
  72                                                 */
  73 #define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  74 #define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  75 #define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  76 #define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  77                                         | STM32_DMA_SCR_MINC \
  78                                         | STM32_DMA_SCR_PINCOS \
  79                                         | STM32_DMA_SCR_PL_MASK)
  80 #define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  81                                         | STM32_DMA_SCR_TEIE \
  82                                         | STM32_DMA_SCR_DMEIE)
  83
  84 /* DMA Stream x number of data register */
  85 #define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  86
  87 /* DMA stream peripheral address register */
  88 #define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  89
  90 /* DMA stream x memory 0 address register */
  91 #define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  92
  93 /* DMA stream x memory 1 address register */
  94 #define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  95
  96 /* DMA stream x FIFO control register */
  97 #define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  98 #define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  99 #define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
 100 #define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
 101 #define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
 102 #define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
 103                                         | STM32_DMA_SFCR_DMDIS)
 104
 105 /* DMA direction */
 106 #define STM32_DMA_DEV_TO_MEM            0x00
 107 #define STM32_DMA_MEM_TO_DEV            0x01
 108 #define STM32_DMA_MEM_TO_MEM            0x02
 109
 110 /* DMA priority level */
 111 #define STM32_DMA_PRIORITY_LOW          0x00
 112 #define STM32_DMA_PRIORITY_MEDIUM       0x01
 113 #define STM32_DMA_PRIORITY_HIGH         0x02
 114 #define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 115
 116 /* DMA FIFO threshold selection */
 117 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 118 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 119 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 120 #define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 121 #define STM32_DMA_FIFO_THRESHOLD_NONE                   0x04
 122
 123 #define STM32_DMA_MAX_DATA_ITEMS        0xffff
 124 /*
 125  * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
 126  * gather at boundary. Thus it's safer to round down this value on FIFO
 127  * size (16 Bytes)
 128  */
 129 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS        \
 130         ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
 131 #define STM32_DMA_MAX_CHANNELS          0x08
 132 #define STM32_DMA_MAX_REQUEST_ID        0x08
 133 #define STM32_DMA_MAX_DATA_PARAM        0x03
 134 #define STM32_DMA_FIFO_SIZE             16      /* FIFO is 16 bytes */
 135 #define STM32_DMA_MIN_BURST             4
 136 #define STM32_DMA_MAX_BURST             16
 137
 138 /* DMA Features */
 139 #define STM32_DMA_THRESHOLD_FTR_MASK    GENMASK(1, 0)
 140 #define STM32_DMA_THRESHOLD_FTR_GET(n)  ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
 141 #define STM32_DMA_DIRECT_MODE_MASK      BIT(2)
 142 #define STM32_DMA_DIRECT_MODE_GET(n)    (((n) & STM32_DMA_DIRECT_MODE_MASK) >> 2)
 143 #define STM32_DMA_ALT_ACK_MODE_MASK     BIT(4)
 144 #define STM32_DMA_ALT_ACK_MODE_GET(n)   (((n) & STM32_DMA_ALT_ACK_MODE_MASK) >> 4)
 145
 146 enum stm32_dma_width {
 147         STM32_DMA_BYTE,
 148         STM32_DMA_HALF_WORD,
 149         STM32_DMA_WORD,
 150 };
 151
 152 enum stm32_dma_burst_size {
 153         STM32_DMA_BURST_SINGLE,
 154         STM32_DMA_BURST_INCR4,
 155         STM32_DMA_BURST_INCR8,
 156         STM32_DMA_BURST_INCR16,
 157 };
 158
 159 /**
 160  * struct stm32_dma_cfg - STM32 DMA custom configuration
 161  * @channel_id: channel ID
 162  * @request_line: DMA request
 163  * @stream_config: 32bit mask specifying the DMA channel configuration
 164  * @features: 32bit mask specifying the DMA Feature list
 165  */
 166 struct stm32_dma_cfg {
 167         u32 channel_id;
 168         u32 request_line;
 169         u32 stream_config;
 170         u32 features;
 171 };
 172
 173 struct stm32_dma_chan_reg {
 174         u32 dma_lisr;
 175         u32 dma_hisr;
 176         u32 dma_lifcr;
 177         u32 dma_hifcr;
 178         u32 dma_scr;
 179         u32 dma_sndtr;
 180         u32 dma_spar;
 181         u32 dma_sm0ar;
 182         u32 dma_sm1ar;
 183         u32 dma_sfcr;
 184 };
 185
 186 struct stm32_dma_sg_req {
 187         u32 len;
 188         struct stm32_dma_chan_reg chan_reg;
 189 };
 190
 191 struct stm32_dma_desc {
 192         struct virt_dma_desc vdesc;
 193         bool cyclic;
 194         u32 num_sgs;
 195         struct stm32_dma_sg_req sg_req[];
 196 };
 197
 198 struct stm32_dma_chan {
 199         struct virt_dma_chan vchan;
 200         bool config_init;
 201         bool busy;
 202         u32 id;
 203         u32 irq;
 204         struct stm32_dma_desc *desc;
 205         u32 next_sg;
 206         struct dma_slave_config dma_sconfig;
 207         struct stm32_dma_chan_reg chan_reg;
 208         u32 threshold;
 209         u32 mem_burst;
 210         u32 mem_width;
 211 };
 212
 213 struct stm32_dma_device {
 214         struct dma_device ddev;
 215         void __iomem *base;
 216         struct clk *clk;
 217         bool mem2mem;
 218         struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 219 };
 220
 221 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 222 {
 223         return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 224                             ddev);
 225 }
 226
 227 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 228 {
 229         return container_of(c, struct stm32_dma_chan, vchan.chan);
 230 }
 231
 232 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 233 {
 234         return container_of(vdesc, struct stm32_dma_desc, vdesc);
 235 }
 236
 237 static struct device *chan2dev(struct stm32_dma_chan *chan)
 238 {
 239         return &chan->vchan.chan.dev->device;
 240 }
 241
 242 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 243 {
 244         return readl_relaxed(dmadev->base + reg);
 245 }
 246
 247 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 248 {
 249         writel_relaxed(val, dmadev->base + reg);
 250 }
 251
 252 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 253                                enum dma_slave_buswidth width)
 254 {
 255         switch (width) {
 256         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 257                 return STM32_DMA_BYTE;
 258         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 259                 return STM32_DMA_HALF_WORD;
 260         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 261                 return STM32_DMA_WORD;
 262         default:
 263                 dev_err(chan2dev(chan), "Dma bus width not supported\n");
 264                 return -EINVAL;
 265         }
 266 }
 267
 268 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
 269                                                        dma_addr_t buf_addr,
 270                                                        u32 threshold)
 271 {
 272         enum dma_slave_buswidth max_width;
 273
 274         if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
 275                 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 276         else
 277                 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 278
 279         while ((buf_len < max_width  || buf_len % max_width) &&
 280                max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
 281                 max_width = max_width >> 1;
 282
 283         if (buf_addr & (max_width - 1))
 284                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 285
 286         return max_width;
 287 }
 288
 289 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
 290                                                 enum dma_slave_buswidth width)
 291 {
 292         u32 remaining;
 293
 294         if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
 295                 return false;
 296
 297         if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 298                 if (burst != 0) {
 299                         /*
 300                          * If number of beats fit in several whole bursts
 301                          * this configuration is allowed.
 302                          */
 303                         remaining = ((STM32_DMA_FIFO_SIZE / width) *
 304                                      (threshold + 1) / 4) % burst;
 305
 306                         if (remaining == 0)
 307                                 return true;
 308                 } else {
 309                         return true;
 310                 }
 311         }
 312
 313         return false;
 314 }
 315
 316 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
 317 {
 318         /* If FIFO direct mode, burst is not possible */
 319         if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
 320                 return false;
 321
 322         /*
 323          * Buffer or period length has to be aligned on FIFO depth.
 324          * Otherwise bytes may be stuck within FIFO at buffer or period
 325          * length.
 326          */
 327         return ((buf_len % ((threshold + 1) * 4)) == 0);
 328 }
 329
 330 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
 331                                     enum dma_slave_buswidth width)
 332 {
 333         u32 best_burst = max_burst;
 334
 335         if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
 336                 return 0;
 337
 338         while ((buf_len < best_burst * width && best_burst > 1) ||
 339                !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
 340                                                     width)) {
 341                 if (best_burst > STM32_DMA_MIN_BURST)
 342                         best_burst = best_burst >> 1;
 343                 else
 344                         best_burst = 0;
 345         }
 346
 347         return best_burst;
 348 }
 349
 350 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 351 {
 352         switch (maxburst) {
 353         case 0:
 354         case 1:
 355                 return STM32_DMA_BURST_SINGLE;
 356         case 4:
 357                 return STM32_DMA_BURST_INCR4;
 358         case 8:
 359                 return STM32_DMA_BURST_INCR8;
 360         case 16:
 361                 return STM32_DMA_BURST_INCR16;
 362         default:
 363                 dev_err(chan2dev(chan), "Dma burst size not supported\n");
 364                 return -EINVAL;
 365         }
 366 }
 367
 368 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 369                                       u32 src_burst, u32 dst_burst)
 370 {
 371         chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 372         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 373
 374         if (!src_burst && !dst_burst) {
 375                 /* Using direct mode */
 376                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 377         } else {
 378                 /* Using FIFO mode */
 379                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 380         }
 381 }
 382
 383 static int stm32_dma_slave_config(struct dma_chan *c,
 384                                   struct dma_slave_config *config)
 385 {
 386         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 387
 388         memcpy(&chan->dma_sconfig, config, sizeof(*config));
 389
 390         chan->config_init = true;
 391
 392         return 0;
 393 }
 394
 395 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 396 {
 397         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 398         u32 flags, dma_isr;
 399
 400         /*
 401          * Read "flags" from DMA_xISR register corresponding to the selected
 402          * DMA channel at the correct bit offset inside that register.
 403          *
 404          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 405          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 406          */
 407
 408         if (chan->id & 4)
 409                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 410         else
 411                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 412
 413         flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 414
 415         return flags & STM32_DMA_MASKI;
 416 }
 417
 418 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 419 {
 420         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 421         u32 dma_ifcr;
 422
 423         /*
 424          * Write "flags" to the DMA_xIFCR register corresponding to the selected
 425          * DMA channel at the correct bit offset inside that register.
 426          *
 427          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 428          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 429          */
 430         flags &= STM32_DMA_MASKI;
 431         dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 432
 433         if (chan->id & 4)
 434                 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 435         else
 436                 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 437 }
 438
 439 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 440 {
 441         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 442         u32 dma_scr, id, reg;
 443
 444         id = chan->id;
 445         reg = STM32_DMA_SCR(id);
 446         dma_scr = stm32_dma_read(dmadev, reg);
 447
 448         if (dma_scr & STM32_DMA_SCR_EN) {
 449                 dma_scr &= ~STM32_DMA_SCR_EN;
 450                 stm32_dma_write(dmadev, reg, dma_scr);
 451
 452                 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
 453                                         dma_scr, !(dma_scr & STM32_DMA_SCR_EN),
 454                                         10, 1000000);
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void stm32_dma_stop(struct stm32_dma_chan *chan)
 461 {
 462         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 463         u32 dma_scr, dma_sfcr, status;
 464         int ret;
 465
 466         /* Disable interrupts */
 467         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 468         dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 469         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 470         dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 471         dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 472         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 473
 474         /* Disable DMA */
 475         ret = stm32_dma_disable_chan(chan);
 476         if (ret < 0)
 477                 return;
 478
 479         /* Clear interrupt status if it is there */
 480         status = stm32_dma_irq_status(chan);
 481         if (status) {
 482                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 483                         __func__, status);
 484                 stm32_dma_irq_clear(chan, status);
 485         }
 486
 487         chan->busy = false;
 488 }
 489
 490 static int stm32_dma_terminate_all(struct dma_chan *c)
 491 {
 492         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 493         unsigned long flags;
 494         LIST_HEAD(head);
 495
 496         spin_lock_irqsave(&chan->vchan.lock, flags);
 497
 498         if (chan->desc) {
 499                 vchan_terminate_vdesc(&chan->desc->vdesc);
 500                 if (chan->busy)
 501                         stm32_dma_stop(chan);
 502                 chan->desc = NULL;
 503         }
 504
 505         vchan_get_all_descriptors(&chan->vchan, &head);
 506         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 507         vchan_dma_desc_free_list(&chan->vchan, &head);
 508
 509         return 0;
 510 }
 511
 512 static void stm32_dma_synchronize(struct dma_chan *c)
 513 {
 514         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 515
 516         vchan_synchronize(&chan->vchan);
 517 }
 518
 519 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 520 {
 521         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 522         u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 523         u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 524         u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 525         u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 526         u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 527         u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 528
 529         dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 530         dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 531         dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 532         dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 533         dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 534         dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 535 }
 536
 537 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 538
 539 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 540 {
 541         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 542         struct virt_dma_desc *vdesc;
 543         struct stm32_dma_sg_req *sg_req;
 544         struct stm32_dma_chan_reg *reg;
 545         u32 status;
 546         int ret;
 547
 548         ret = stm32_dma_disable_chan(chan);
 549         if (ret < 0)
 550                 return;
 551
 552         if (!chan->desc) {
 553                 vdesc = vchan_next_desc(&chan->vchan);
 554                 if (!vdesc)
 555                         return;
 556
 557                 list_del(&vdesc->node);
 558
 559                 chan->desc = to_stm32_dma_desc(vdesc);
 560                 chan->next_sg = 0;
 561         }
 562
 563         if (chan->next_sg == chan->desc->num_sgs)
 564                 chan->next_sg = 0;
 565
 566         sg_req = &chan->desc->sg_req[chan->next_sg];
 567         reg = &sg_req->chan_reg;
 568
 569         reg->dma_scr &= ~STM32_DMA_SCR_EN;
 570         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 571         stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 572         stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 573         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 574         stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 575         stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 576
 577         chan->next_sg++;
 578
 579         /* Clear interrupt status if it is there */
 580         status = stm32_dma_irq_status(chan);
 581         if (status)
 582                 stm32_dma_irq_clear(chan, status);
 583
 584         if (chan->desc->cyclic)
 585                 stm32_dma_configure_next_sg(chan);
 586
 587         stm32_dma_dump_reg(chan);
 588
 589         /* Start DMA */
 590         reg->dma_scr |= STM32_DMA_SCR_EN;
 591         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 592
 593         chan->busy = true;
 594
 595         dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
 596 }
 597
 598 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 599 {
 600         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 601         struct stm32_dma_sg_req *sg_req;
 602         u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 603
 604         id = chan->id;
 605         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 606
 607         if (dma_scr & STM32_DMA_SCR_DBM) {
 608                 if (chan->next_sg == chan->desc->num_sgs)
 609                         chan->next_sg = 0;
 610
 611                 sg_req = &chan->desc->sg_req[chan->next_sg];
 612
 613                 if (dma_scr & STM32_DMA_SCR_CT) {
 614                         dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 615                         stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 616                         dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 617                                 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 618                 } else {
 619                         dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 620                         stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 621                         dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 622                                 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 623                 }
 624         }
 625 }
 626
 627 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 628 {
 629         if (chan->desc) {
 630                 if (chan->desc->cyclic) {
 631                         vchan_cyclic_callback(&chan->desc->vdesc);
 632                         chan->next_sg++;
 633                         stm32_dma_configure_next_sg(chan);
 634                 } else {
 635                         chan->busy = false;
 636                         if (chan->next_sg == chan->desc->num_sgs) {
 637                                 vchan_cookie_complete(&chan->desc->vdesc);
 638                                 chan->desc = NULL;
 639                         }
 640                         stm32_dma_start_transfer(chan);
 641                 }
 642         }
 643 }
 644
 645 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 646 {
 647         struct stm32_dma_chan *chan = devid;
 648         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 649         u32 status, scr, sfcr;
 650
 651         spin_lock(&chan->vchan.lock);
 652
 653         status = stm32_dma_irq_status(chan);
 654         scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 655         sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 656
 657         if (status & STM32_DMA_FEI) {
 658                 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
 659                 status &= ~STM32_DMA_FEI;
 660                 if (sfcr & STM32_DMA_SFCR_FEIE) {
 661                         if (!(scr & STM32_DMA_SCR_EN) &&
 662                             !(status & STM32_DMA_TCI))
 663                                 dev_err(chan2dev(chan), "FIFO Error\n");
 664                         else
 665                                 dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
 666                 }
 667         }
 668         if (status & STM32_DMA_DMEI) {
 669                 stm32_dma_irq_clear(chan, STM32_DMA_DMEI);
 670                 status &= ~STM32_DMA_DMEI;
 671                 if (sfcr & STM32_DMA_SCR_DMEIE)
 672                         dev_dbg(chan2dev(chan), "Direct mode overrun\n");
 673         }
 674
 675         if (status & STM32_DMA_TCI) {
 676                 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 677                 if (scr & STM32_DMA_SCR_TCIE)
 678                         stm32_dma_handle_chan_done(chan);
 679                 status &= ~STM32_DMA_TCI;
 680         }
 681
 682         if (status & STM32_DMA_HTI) {
 683                 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
 684                 status &= ~STM32_DMA_HTI;
 685         }
 686
 687         if (status) {
 688                 stm32_dma_irq_clear(chan, status);
 689                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 690                 if (!(scr & STM32_DMA_SCR_EN))
 691                         dev_err(chan2dev(chan), "chan disabled by HW\n");
 692         }
 693
 694         spin_unlock(&chan->vchan.lock);
 695
 696         return IRQ_HANDLED;
 697 }
 698
 699 static void stm32_dma_issue_pending(struct dma_chan *c)
 700 {
 701         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 702         unsigned long flags;
 703
 704         spin_lock_irqsave(&chan->vchan.lock, flags);
 705         if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 706                 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
 707                 stm32_dma_start_transfer(chan);
 708
 709         }
 710         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 711 }
 712
 713 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 714                                     enum dma_transfer_direction direction,
 715                                     enum dma_slave_buswidth *buswidth,
 716                                     u32 buf_len, dma_addr_t buf_addr)
 717 {
 718         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 719         int src_bus_width, dst_bus_width;
 720         int src_burst_size, dst_burst_size;
 721         u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 722         u32 dma_scr, fifoth;
 723
 724         src_addr_width = chan->dma_sconfig.src_addr_width;
 725         dst_addr_width = chan->dma_sconfig.dst_addr_width;
 726         src_maxburst = chan->dma_sconfig.src_maxburst;
 727         dst_maxburst = chan->dma_sconfig.dst_maxburst;
 728         fifoth = chan->threshold;
 729
 730         switch (direction) {
 731         case DMA_MEM_TO_DEV:
 732                 /* Set device data size */
 733                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 734                 if (dst_bus_width < 0)
 735                         return dst_bus_width;
 736
 737                 /* Set device burst size */
 738                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 739                                                           dst_maxburst,
 740                                                           fifoth,
 741                                                           dst_addr_width);
 742
 743                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 744                 if (dst_burst_size < 0)
 745                         return dst_burst_size;
 746
 747                 /* Set memory data size */
 748                 src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
 749                                                          fifoth);
 750                 chan->mem_width = src_addr_width;
 751                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 752                 if (src_bus_width < 0)
 753                         return src_bus_width;
 754
 755                 /*
 756                  * Set memory burst size - burst not possible if address is not aligned on
 757                  * the address boundary equal to the size of the transfer
 758                  */
 759                 if (buf_addr & (buf_len - 1))
 760                         src_maxburst = 1;
 761                 else
 762                         src_maxburst = STM32_DMA_MAX_BURST;
 763                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 764                                                           src_maxburst,
 765                                                           fifoth,
 766                                                           src_addr_width);
 767                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 768                 if (src_burst_size < 0)
 769                         return src_burst_size;
 770
 771                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 772                         STM32_DMA_SCR_PSIZE(dst_bus_width) |
 773                         STM32_DMA_SCR_MSIZE(src_bus_width) |
 774                         STM32_DMA_SCR_PBURST(dst_burst_size) |
 775                         STM32_DMA_SCR_MBURST(src_burst_size);
 776
 777                 /* Set FIFO threshold */
 778                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 779                 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
 780                         chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
 781
 782                 /* Set peripheral address */
 783                 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 784                 *buswidth = dst_addr_width;
 785                 break;
 786
 787         case DMA_DEV_TO_MEM:
 788                 /* Set device data size */
 789                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 790                 if (src_bus_width < 0)
 791                         return src_bus_width;
 792
 793                 /* Set device burst size */
 794                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 795                                                           src_maxburst,
 796                                                           fifoth,
 797                                                           src_addr_width);
 798                 chan->mem_burst = src_best_burst;
 799                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 800                 if (src_burst_size < 0)
 801                         return src_burst_size;
 802
 803                 /* Set memory data size */
 804                 dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
 805                                                          fifoth);
 806                 chan->mem_width = dst_addr_width;
 807                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 808                 if (dst_bus_width < 0)
 809                         return dst_bus_width;
 810
 811                 /*
 812                  * Set memory burst size - burst not possible if address is not aligned on
 813                  * the address boundary equal to the size of the transfer
 814                  */
 815                 if (buf_addr & (buf_len - 1))
 816                         dst_maxburst = 1;
 817                 else
 818                         dst_maxburst = STM32_DMA_MAX_BURST;
 819                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 820                                                           dst_maxburst,
 821                                                           fifoth,
 822                                                           dst_addr_width);
 823                 chan->mem_burst = dst_best_burst;
 824                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 825                 if (dst_burst_size < 0)
 826                         return dst_burst_size;
 827
 828                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 829                         STM32_DMA_SCR_PSIZE(src_bus_width) |
 830                         STM32_DMA_SCR_MSIZE(dst_bus_width) |
 831                         STM32_DMA_SCR_PBURST(src_burst_size) |
 832                         STM32_DMA_SCR_MBURST(dst_burst_size);
 833
 834                 /* Set FIFO threshold */
 835                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 836                 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
 837                         chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
 838
 839                 /* Set peripheral address */
 840                 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 841                 *buswidth = chan->dma_sconfig.src_addr_width;
 842                 break;
 843
 844         default:
 845                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 846                 return -EINVAL;
 847         }
 848
 849         stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
 850
 851         /* Set DMA control register */
 852         chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 853                         STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 854                         STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 855         chan->chan_reg.dma_scr |= dma_scr;
 856
 857         return 0;
 858 }
 859
 860 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 861 {
 862         memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 863 }
 864
 865 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 866         struct dma_chan *c, struct scatterlist *sgl,
 867         u32 sg_len, enum dma_transfer_direction direction,
 868         unsigned long flags, void *context)
 869 {
 870         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 871         struct stm32_dma_desc *desc;
 872         struct scatterlist *sg;
 873         enum dma_slave_buswidth buswidth;
 874         u32 nb_data_items;
 875         int i, ret;
 876
 877         if (!chan->config_init) {
 878                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 879                 return NULL;
 880         }
 881
 882         if (sg_len < 1) {
 883                 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 884                 return NULL;
 885         }
 886
 887         desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
 888         if (!desc)
 889                 return NULL;
 890
 891         /* Set peripheral flow controller */
 892         if (chan->dma_sconfig.device_fc)
 893                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 894         else
 895                 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 896
 897         for_each_sg(sgl, sg, sg_len, i) {
 898                 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
 899                                                sg_dma_len(sg),
 900                                                sg_dma_address(sg));
 901                 if (ret < 0)
 902                         goto err;
 903
 904                 desc->sg_req[i].len = sg_dma_len(sg);
 905
 906                 nb_data_items = desc->sg_req[i].len / buswidth;
 907                 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 908                         dev_err(chan2dev(chan), "nb items not supported\n");
 909                         goto err;
 910                 }
 911
 912                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 913                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 914                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 915                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 916                 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 917                 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 918                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 919         }
 920
 921         desc->num_sgs = sg_len;
 922         desc->cyclic = false;
 923
 924         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 925
 926 err:
 927         kfree(desc);
 928         return NULL;
 929 }
 930
 931 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 932         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 933         size_t period_len, enum dma_transfer_direction direction,
 934         unsigned long flags)
 935 {
 936         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 937         struct stm32_dma_desc *desc;
 938         enum dma_slave_buswidth buswidth;
 939         u32 num_periods, nb_data_items;
 940         int i, ret;
 941
 942         if (!buf_len || !period_len) {
 943                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 944                 return NULL;
 945         }
 946
 947         if (!chan->config_init) {
 948                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 949                 return NULL;
 950         }
 951
 952         if (buf_len % period_len) {
 953                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 954                 return NULL;
 955         }
 956
 957         /*
 958          * We allow to take more number of requests till DMA is
 959          * not started. The driver will loop over all requests.
 960          * Once DMA is started then new requests can be queued only after
 961          * terminating the DMA.
 962          */
 963         if (chan->busy) {
 964                 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 965                 return NULL;
 966         }
 967
 968         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len,
 969                                        buf_addr);
 970         if (ret < 0)
 971                 return NULL;
 972
 973         nb_data_items = period_len / buswidth;
 974         if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 975                 dev_err(chan2dev(chan), "number of items not supported\n");
 976                 return NULL;
 977         }
 978
 979         /*  Enable Circular mode or double buffer mode */
 980         if (buf_len == period_len)
 981                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 982         else
 983                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 984
 985         /* Clear periph ctrl if client set it */
 986         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 987
 988         num_periods = buf_len / period_len;
 989
 990         desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT);
 991         if (!desc)
 992                 return NULL;
 993
 994         for (i = 0; i < num_periods; i++) {
 995                 desc->sg_req[i].len = period_len;
 996
 997                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 998                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 999                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
1000                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
1001                 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
1002                 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
1003                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1004                 buf_addr += period_len;
1005         }
1006
1007         desc->num_sgs = num_periods;
1008         desc->cyclic = true;
1009
1010         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1011 }
1012
1013 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
1014         struct dma_chan *c, dma_addr_t dest,
1015         dma_addr_t src, size_t len, unsigned long flags)
1016 {
1017         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1018         enum dma_slave_buswidth max_width;
1019         struct stm32_dma_desc *desc;
1020         size_t xfer_count, offset;
1021         u32 num_sgs, best_burst, dma_burst, threshold;
1022         int i;
1023
1024         num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1025         desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
1026         if (!desc)
1027                 return NULL;
1028
1029         threshold = chan->threshold;
1030
1031         for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
1032                 xfer_count = min_t(size_t, len - offset,
1033                                    STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1034
1035                 /* Compute best burst size */
1036                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1037                 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1038                                                       threshold, max_width);
1039                 dma_burst = stm32_dma_get_burst(chan, best_burst);
1040
1041                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1042                 desc->sg_req[i].chan_reg.dma_scr =
1043                         STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
1044                         STM32_DMA_SCR_PBURST(dma_burst) |
1045                         STM32_DMA_SCR_MBURST(dma_burst) |
1046                         STM32_DMA_SCR_MINC |
1047                         STM32_DMA_SCR_PINC |
1048                         STM32_DMA_SCR_TCIE |
1049                         STM32_DMA_SCR_TEIE;
1050                 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1051                 desc->sg_req[i].chan_reg.dma_sfcr |=
1052                         STM32_DMA_SFCR_FTH(threshold);
1053                 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1054                 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1055                 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1056                 desc->sg_req[i].len = xfer_count;
1057         }
1058
1059         desc->num_sgs = num_sgs;
1060         desc->cyclic = false;
1061
1062         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1063 }
1064
1065 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1066 {
1067         u32 dma_scr, width, ndtr;
1068         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1069
1070         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1071         width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1072         ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1073
1074         return ndtr << width;
1075 }
1076
1077 /**
1078  * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1079  * @chan: dma channel
1080  *
1081  * This function called when IRQ are disable, checks that the hardware has not
1082  * switched on the next transfer in double buffer mode. The test is done by
1083  * comparing the next_sg memory address with the hardware related register
1084  * (based on CT bit value).
1085  *
1086  * Returns true if expected current transfer is still running or double
1087  * buffer mode is not activated.
1088  */
1089 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
1090 {
1091         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1092         struct stm32_dma_sg_req *sg_req;
1093         u32 dma_scr, dma_smar, id;
1094
1095         id = chan->id;
1096         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1097
1098         if (!(dma_scr & STM32_DMA_SCR_DBM))
1099                 return true;
1100
1101         sg_req = &chan->desc->sg_req[chan->next_sg];
1102
1103         if (dma_scr & STM32_DMA_SCR_CT) {
1104                 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1105                 return (dma_smar == sg_req->chan_reg.dma_sm0ar);
1106         }
1107
1108         dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1109
1110         return (dma_smar == sg_req->chan_reg.dma_sm1ar);
1111 }
1112
1113 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1114                                      struct stm32_dma_desc *desc,
1115                                      u32 next_sg)
1116 {
1117         u32 modulo, burst_size;
1118         u32 residue;
1119         u32 n_sg = next_sg;
1120         struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
1121         int i;
1122
1123         /*
1124          * Calculate the residue means compute the descriptors
1125          * information:
1126          * - the sg_req currently transferred
1127          * - the Hardware remaining position in this sg (NDTR bits field).
1128          *
1129          * A race condition may occur if DMA is running in cyclic or double
1130          * buffer mode, since the DMA register are automatically reloaded at end
1131          * of period transfer. The hardware may have switched to the next
1132          * transfer (CT bit updated) just before the position (SxNDTR reg) is
1133          * read.
1134          * In this case the SxNDTR reg could (or not) correspond to the new
1135          * transfer position, and not the expected one.
1136          * The strategy implemented in the stm32 driver is to:
1137          *  - read the SxNDTR register
1138          *  - crosscheck that hardware is still in current transfer.
1139          * In case of switch, we can assume that the DMA is at the beginning of
1140          * the next transfer. So we approximate the residue in consequence, by
1141          * pointing on the beginning of next transfer.
1142          *
1143          * This race condition doesn't apply for none cyclic mode, as double
1144          * buffer is not used. In such situation registers are updated by the
1145          * software.
1146          */
1147
1148         residue = stm32_dma_get_remaining_bytes(chan);
1149
1150         if (!stm32_dma_is_current_sg(chan)) {
1151                 n_sg++;
1152                 if (n_sg == chan->desc->num_sgs)
1153                         n_sg = 0;
1154                 residue = sg_req->len;
1155         }
1156
1157         /*
1158          * In cyclic mode, for the last period, residue = remaining bytes
1159          * from NDTR,
1160          * else for all other periods in cyclic mode, and in sg mode,
1161          * residue = remaining bytes from NDTR + remaining
1162          * periods/sg to be transferred
1163          */
1164         if (!chan->desc->cyclic || n_sg != 0)
1165                 for (i = n_sg; i < desc->num_sgs; i++)
1166                         residue += desc->sg_req[i].len;
1167
1168         if (!chan->mem_burst)
1169                 return residue;
1170
1171         burst_size = chan->mem_burst * chan->mem_width;
1172         modulo = residue % burst_size;
1173         if (modulo)
1174                 residue = residue - modulo + burst_size;
1175
1176         return residue;
1177 }
1178
1179 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1180                                            dma_cookie_t cookie,
1181                                            struct dma_tx_state *state)
1182 {
1183         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1184         struct virt_dma_desc *vdesc;
1185         enum dma_status status;
1186         unsigned long flags;
1187         u32 residue = 0;
1188
1189         status = dma_cookie_status(c, cookie, state);
1190         if (status == DMA_COMPLETE || !state)
1191                 return status;
1192
1193         spin_lock_irqsave(&chan->vchan.lock, flags);
1194         vdesc = vchan_find_desc(&chan->vchan, cookie);
1195         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1196                 residue = stm32_dma_desc_residue(chan, chan->desc,
1197                                                  chan->next_sg);
1198         else if (vdesc)
1199                 residue = stm32_dma_desc_residue(chan,
1200                                                  to_stm32_dma_desc(vdesc), 0);
1201         dma_set_residue(state, residue);
1202
1203         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1204
1205         return status;
1206 }
1207
1208 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1209 {
1210         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1211         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1212         int ret;
1213
1214         chan->config_init = false;
1215
1216         ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1217         if (ret < 0)
1218                 return ret;
1219
1220         ret = stm32_dma_disable_chan(chan);
1221         if (ret < 0)
1222                 pm_runtime_put(dmadev->ddev.dev);
1223
1224         return ret;
1225 }
1226
1227 static void stm32_dma_free_chan_resources(struct dma_chan *c)
1228 {
1229         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1230         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1231         unsigned long flags;
1232
1233         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1234
1235         if (chan->busy) {
1236                 spin_lock_irqsave(&chan->vchan.lock, flags);
1237                 stm32_dma_stop(chan);
1238                 chan->desc = NULL;
1239                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1240         }
1241
1242         pm_runtime_put(dmadev->ddev.dev);
1243
1244         vchan_free_chan_resources(to_virt_chan(c));
1245         stm32_dma_clear_reg(&chan->chan_reg);
1246         chan->threshold = 0;
1247 }
1248
1249 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1250 {
1251         kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1252 }
1253
1254 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1255                                  struct stm32_dma_cfg *cfg)
1256 {
1257         stm32_dma_clear_reg(&chan->chan_reg);
1258
1259         chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1260         chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1261
1262         /* Enable Interrupts  */
1263         chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1264
1265         chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1266         if (STM32_DMA_DIRECT_MODE_GET(cfg->features))
1267                 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE;
1268         if (STM32_DMA_ALT_ACK_MODE_GET(cfg->features))
1269                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;
1270 }
1271
1272 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1273                                            struct of_dma *ofdma)
1274 {
1275         struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1276         struct device *dev = dmadev->ddev.dev;
1277         struct stm32_dma_cfg cfg;
1278         struct stm32_dma_chan *chan;
1279         struct dma_chan *c;
1280
1281         if (dma_spec->args_count < 4) {
1282                 dev_err(dev, "Bad number of cells\n");
1283                 return NULL;
1284         }
1285
1286         cfg.channel_id = dma_spec->args[0];
1287         cfg.request_line = dma_spec->args[1];
1288         cfg.stream_config = dma_spec->args[2];
1289         cfg.features = dma_spec->args[3];
1290
1291         if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1292             cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1293                 dev_err(dev, "Bad channel and/or request id\n");
1294                 return NULL;
1295         }
1296
1297         chan = &dmadev->chan[cfg.channel_id];
1298
1299         c = dma_get_slave_channel(&chan->vchan.chan);
1300         if (!c) {
1301                 dev_err(dev, "No more channels available\n");
1302                 return NULL;
1303         }
1304
1305         stm32_dma_set_config(chan, &cfg);
1306
1307         return c;
1308 }
1309
1310 static const struct of_device_id stm32_dma_of_match[] = {
1311         { .compatible = "st,stm32-dma", },
1312         { /* sentinel */ },
1313 };
1314 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1315
1316 static int stm32_dma_probe(struct platform_device *pdev)
1317 {
1318         struct stm32_dma_chan *chan;
1319         struct stm32_dma_device *dmadev;
1320         struct dma_device *dd;
1321         const struct of_device_id *match;
1322         struct resource *res;
1323         struct reset_control *rst;
1324         int i, ret;
1325
1326         match = of_match_device(stm32_dma_of_match, &pdev->dev);
1327         if (!match) {
1328                 dev_err(&pdev->dev, "Error: No device match found\n");
1329                 return -ENODEV;
1330         }
1331
1332         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1333         if (!dmadev)
1334                 return -ENOMEM;
1335
1336         dd = &dmadev->ddev;
1337
1338         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1340         if (IS_ERR(dmadev->base))
1341                 return PTR_ERR(dmadev->base);
1342
1343         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1344         if (IS_ERR(dmadev->clk))
1345                 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
1346
1347         ret = clk_prepare_enable(dmadev->clk);
1348         if (ret < 0) {
1349                 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1350                 return ret;
1351         }
1352
1353         dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1354                                                 "st,mem2mem");
1355
1356         rst = devm_reset_control_get(&pdev->dev, NULL);
1357         if (IS_ERR(rst)) {
1358                 ret = PTR_ERR(rst);
1359                 if (ret == -EPROBE_DEFER)
1360                         goto clk_free;
1361         } else {
1362                 reset_control_assert(rst);
1363                 udelay(2);
1364                 reset_control_deassert(rst);
1365         }
1366
1367         dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1368
1369         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1370         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1371         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1372         dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1373         dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1374         dd->device_tx_status = stm32_dma_tx_status;
1375         dd->device_issue_pending = stm32_dma_issue_pending;
1376         dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1377         dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1378         dd->device_config = stm32_dma_slave_config;
1379         dd->device_terminate_all = stm32_dma_terminate_all;
1380         dd->device_synchronize = stm32_dma_synchronize;
1381         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1382                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1383                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1384         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1385                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1386                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1387         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1388         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1389         dd->copy_align = DMAENGINE_ALIGN_32_BYTES;
1390         dd->max_burst = STM32_DMA_MAX_BURST;
1391         dd->descriptor_reuse = true;
1392         dd->dev = &pdev->dev;
1393         INIT_LIST_HEAD(&dd->channels);
1394
1395         if (dmadev->mem2mem) {
1396                 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1397                 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1398                 dd->directions |= BIT(DMA_MEM_TO_MEM);
1399         }
1400
1401         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1402                 chan = &dmadev->chan[i];
1403                 chan->id = i;
1404                 chan->vchan.desc_free = stm32_dma_desc_free;
1405                 vchan_init(&chan->vchan, dd);
1406         }
1407
1408         ret = dma_async_device_register(dd);
1409         if (ret)
1410                 goto clk_free;
1411
1412         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1413                 chan = &dmadev->chan[i];
1414                 ret = platform_get_irq(pdev, i);
1415                 if (ret < 0)
1416                         goto err_unregister;
1417                 chan->irq = ret;
1418
1419                 ret = devm_request_irq(&pdev->dev, chan->irq,
1420                                        stm32_dma_chan_irq, 0,
1421                                        dev_name(chan2dev(chan)), chan);
1422                 if (ret) {
1423                         dev_err(&pdev->dev,
1424                                 "request_irq failed with err %d channel %d\n",
1425                                 ret, i);
1426                         goto err_unregister;
1427                 }
1428         }
1429
1430         ret = of_dma_controller_register(pdev->dev.of_node,
1431                                          stm32_dma_of_xlate, dmadev);
1432         if (ret < 0) {
1433                 dev_err(&pdev->dev,
1434                         "STM32 DMA DMA OF registration failed %d\n", ret);
1435                 goto err_unregister;
1436         }
1437
1438         platform_set_drvdata(pdev, dmadev);
1439
1440         pm_runtime_set_active(&pdev->dev);
1441         pm_runtime_enable(&pdev->dev);
1442         pm_runtime_get_noresume(&pdev->dev);
1443         pm_runtime_put(&pdev->dev);
1444
1445         dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1446
1447         return 0;
1448
1449 err_unregister:
1450         dma_async_device_unregister(dd);
1451 clk_free:
1452         clk_disable_unprepare(dmadev->clk);
1453
1454         return ret;
1455 }
1456
1457 #ifdef CONFIG_PM
1458 static int stm32_dma_runtime_suspend(struct device *dev)
1459 {
1460         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1461
1462         clk_disable_unprepare(dmadev->clk);
1463
1464         return 0;
1465 }
1466
1467 static int stm32_dma_runtime_resume(struct device *dev)
1468 {
1469         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1470         int ret;
1471
1472         ret = clk_prepare_enable(dmadev->clk);
1473         if (ret) {
1474                 dev_err(dev, "failed to prepare_enable clock\n");
1475                 return ret;
1476         }
1477
1478         return 0;
1479 }
1480 #endif
1481
1482 #ifdef CONFIG_PM_SLEEP
1483 static int stm32_dma_suspend(struct device *dev)
1484 {
1485         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1486         int id, ret, scr;
1487
1488         ret = pm_runtime_resume_and_get(dev);
1489         if (ret < 0)
1490                 return ret;
1491
1492         for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) {
1493                 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1494                 if (scr & STM32_DMA_SCR_EN) {
1495                         dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
1496                         return -EBUSY;
1497                 }
1498         }
1499
1500         pm_runtime_put_sync(dev);
1501
1502         pm_runtime_force_suspend(dev);
1503
1504         return 0;
1505 }
1506
1507 static int stm32_dma_resume(struct device *dev)
1508 {
1509         return pm_runtime_force_resume(dev);
1510 }
1511 #endif
1512
1513 static const struct dev_pm_ops stm32_dma_pm_ops = {
1514         SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume)
1515         SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
1516                            stm32_dma_runtime_resume, NULL)
1517 };
1518
1519 static struct platform_driver stm32_dma_driver = {
1520         .driver = {
1521                 .name = "stm32-dma",
1522                 .of_match_table = stm32_dma_of_match,
1523                 .pm = &stm32_dma_pm_ops,
1524         },
1525         .probe = stm32_dma_probe,
1526 };
1527
1528 static int __init stm32_dma_init(void)
1529 {
1530         return platform_driver_register(&stm32_dma_driver);
1531 }
1532 subsys_initcall(stm32_dma_init);