drivers/dma/stm32-dma.c

   1 /*
   2  * Driver for STM32 DMA controller
   3  *
   4  * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   5  *
   6  * Copyright (C) M'boumba Cedric Madianga 2015
   7  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   8  *
   9  * License terms:  GNU General Public License (GPL), version 2
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/list.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_dma.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reset.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28
  29 #include "virt-dma.h"
  30
  31 #define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  32 #define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  33 #define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  34 #define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  35 #define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  36 #define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  37 #define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  38 #define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  39
  40 /* DMA Stream x Configuration Register */
  41 #define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  42 #define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  43 #define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  44 #define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  45 #define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  46 #define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  47 #define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  48 #define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  49 #define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  50 #define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  51 #define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  52 #define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  53 #define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  54 #define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  55 #define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  56 #define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  57 #define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  58 #define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  59 #define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  60 #define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  61 #define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  62 #define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  63 #define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Cplete Int Enable*/
  64 #define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  65 #define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  66 #define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  67 #define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  68                                         | STM32_DMA_SCR_MINC \
  69                                         | STM32_DMA_SCR_PINCOS \
  70                                         | STM32_DMA_SCR_PL_MASK)
  71 #define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  72                                         | STM32_DMA_SCR_TEIE \
  73                                         | STM32_DMA_SCR_DMEIE)
  74
  75 /* DMA Stream x number of data register */
  76 #define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  77
  78 /* DMA stream peripheral address register */
  79 #define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  80
  81 /* DMA stream x memory 0 address register */
  82 #define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  83
  84 /* DMA stream x memory 1 address register */
  85 #define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  86
  87 /* DMA stream x FIFO control register */
  88 #define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  89 #define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  90 #define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
  91 #define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
  92 #define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
  93 #define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
  94                                         | STM32_DMA_SFCR_DMDIS)
  95
  96 /* DMA direction */
  97 #define STM32_DMA_DEV_TO_MEM            0x00
  98 #define STM32_DMA_MEM_TO_DEV            0x01
  99 #define STM32_DMA_MEM_TO_MEM            0x02
 100
 101 /* DMA priority level */
 102 #define STM32_DMA_PRIORITY_LOW          0x00
 103 #define STM32_DMA_PRIORITY_MEDIUM       0x01
 104 #define STM32_DMA_PRIORITY_HIGH         0x02
 105 #define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 106
 107 /* DMA FIFO threshold selection */
 108 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 109 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 110 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 111 #define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 112
 113 #define STM32_DMA_MAX_DATA_ITEMS        0xffff
 114 #define STM32_DMA_MAX_CHANNELS          0x08
 115 #define STM32_DMA_MAX_REQUEST_ID        0x08
 116 #define STM32_DMA_MAX_DATA_PARAM        0x03
 117 #define STM32_DMA_MAX_BURST             16
 118
 119 enum stm32_dma_width {
 120         STM32_DMA_BYTE,
 121         STM32_DMA_HALF_WORD,
 122         STM32_DMA_WORD,
 123 };
 124
 125 enum stm32_dma_burst_size {
 126         STM32_DMA_BURST_SINGLE,
 127         STM32_DMA_BURST_INCR4,
 128         STM32_DMA_BURST_INCR8,
 129         STM32_DMA_BURST_INCR16,
 130 };
 131
 132 struct stm32_dma_cfg {
 133         u32 channel_id;
 134         u32 request_line;
 135         u32 stream_config;
 136         u32 threshold;
 137 };
 138
 139 struct stm32_dma_chan_reg {
 140         u32 dma_lisr;
 141         u32 dma_hisr;
 142         u32 dma_lifcr;
 143         u32 dma_hifcr;
 144         u32 dma_scr;
 145         u32 dma_sndtr;
 146         u32 dma_spar;
 147         u32 dma_sm0ar;
 148         u32 dma_sm1ar;
 149         u32 dma_sfcr;
 150 };
 151
 152 struct stm32_dma_sg_req {
 153         u32 len;
 154         struct stm32_dma_chan_reg chan_reg;
 155 };
 156
 157 struct stm32_dma_desc {
 158         struct virt_dma_desc vdesc;
 159         bool cyclic;
 160         u32 num_sgs;
 161         struct stm32_dma_sg_req sg_req[];
 162 };
 163
 164 struct stm32_dma_chan {
 165         struct virt_dma_chan vchan;
 166         bool config_init;
 167         bool busy;
 168         u32 id;
 169         u32 irq;
 170         struct stm32_dma_desc *desc;
 171         u32 next_sg;
 172         struct dma_slave_config dma_sconfig;
 173         struct stm32_dma_chan_reg chan_reg;
 174 };
 175
 176 struct stm32_dma_device {
 177         struct dma_device ddev;
 178         void __iomem *base;
 179         struct clk *clk;
 180         struct reset_control *rst;
 181         bool mem2mem;
 182         struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 183 };
 184
 185 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 186 {
 187         return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 188                             ddev);
 189 }
 190
 191 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 192 {
 193         return container_of(c, struct stm32_dma_chan, vchan.chan);
 194 }
 195
 196 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 197 {
 198         return container_of(vdesc, struct stm32_dma_desc, vdesc);
 199 }
 200
 201 static struct device *chan2dev(struct stm32_dma_chan *chan)
 202 {
 203         return &chan->vchan.chan.dev->device;
 204 }
 205
 206 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 207 {
 208         return readl_relaxed(dmadev->base + reg);
 209 }
 210
 211 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 212 {
 213         writel_relaxed(val, dmadev->base + reg);
 214 }
 215
 216 static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
 217 {
 218         return kzalloc(sizeof(struct stm32_dma_desc) +
 219                        sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
 220 }
 221
 222 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 223                                enum dma_slave_buswidth width)
 224 {
 225         switch (width) {
 226         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 227                 return STM32_DMA_BYTE;
 228         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 229                 return STM32_DMA_HALF_WORD;
 230         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 231                 return STM32_DMA_WORD;
 232         default:
 233                 dev_err(chan2dev(chan), "Dma bus width not supported\n");
 234                 return -EINVAL;
 235         }
 236 }
 237
 238 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 239 {
 240         switch (maxburst) {
 241         case 0:
 242         case 1:
 243                 return STM32_DMA_BURST_SINGLE;
 244         case 4:
 245                 return STM32_DMA_BURST_INCR4;
 246         case 8:
 247                 return STM32_DMA_BURST_INCR8;
 248         case 16:
 249                 return STM32_DMA_BURST_INCR16;
 250         default:
 251                 dev_err(chan2dev(chan), "Dma burst size not supported\n");
 252                 return -EINVAL;
 253         }
 254 }
 255
 256 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 257                                       u32 src_maxburst, u32 dst_maxburst)
 258 {
 259         chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 260         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 261
 262         if ((!src_maxburst) && (!dst_maxburst)) {
 263                 /* Using direct mode */
 264                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 265         } else {
 266                 /* Using FIFO mode */
 267                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 268         }
 269 }
 270
 271 static int stm32_dma_slave_config(struct dma_chan *c,
 272                                   struct dma_slave_config *config)
 273 {
 274         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 275
 276         memcpy(&chan->dma_sconfig, config, sizeof(*config));
 277
 278         chan->config_init = true;
 279
 280         return 0;
 281 }
 282
 283 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 284 {
 285         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 286         u32 flags, dma_isr;
 287
 288         /*
 289          * Read "flags" from DMA_xISR register corresponding to the selected
 290          * DMA channel at the correct bit offset inside that register.
 291          *
 292          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 293          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 294          */
 295
 296         if (chan->id & 4)
 297                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 298         else
 299                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 300
 301         flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 302
 303         return flags;
 304 }
 305
 306 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 307 {
 308         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 309         u32 dma_ifcr;
 310
 311         /*
 312          * Write "flags" to the DMA_xIFCR register corresponding to the selected
 313          * DMA channel at the correct bit offset inside that register.
 314          *
 315          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 316          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 317          */
 318         dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 319
 320         if (chan->id & 4)
 321                 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 322         else
 323                 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 324 }
 325
 326 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 327 {
 328         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 329         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 330         u32 dma_scr, id;
 331
 332         id = chan->id;
 333         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 334
 335         if (dma_scr & STM32_DMA_SCR_EN) {
 336                 dma_scr &= ~STM32_DMA_SCR_EN;
 337                 stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr);
 338
 339                 do {
 340                         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 341                         dma_scr &= STM32_DMA_SCR_EN;
 342                         if (!dma_scr)
 343                                 break;
 344
 345                         if (time_after_eq(jiffies, timeout)) {
 346                                 dev_err(chan2dev(chan), "%s: timeout!\n",
 347                                         __func__);
 348                                 return -EBUSY;
 349                         }
 350                         cond_resched();
 351                 } while (1);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void stm32_dma_stop(struct stm32_dma_chan *chan)
 358 {
 359         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 360         u32 dma_scr, dma_sfcr, status;
 361         int ret;
 362
 363         /* Disable interrupts */
 364         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 365         dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 366         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 367         dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 368         dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 369         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 370
 371         /* Disable DMA */
 372         ret = stm32_dma_disable_chan(chan);
 373         if (ret < 0)
 374                 return;
 375
 376         /* Clear interrupt status if it is there */
 377         status = stm32_dma_irq_status(chan);
 378         if (status) {
 379                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 380                         __func__, status);
 381                 stm32_dma_irq_clear(chan, status);
 382         }
 383
 384         chan->busy = false;
 385 }
 386
 387 static int stm32_dma_terminate_all(struct dma_chan *c)
 388 {
 389         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 390         unsigned long flags;
 391         LIST_HEAD(head);
 392
 393         spin_lock_irqsave(&chan->vchan.lock, flags);
 394
 395         if (chan->busy) {
 396                 stm32_dma_stop(chan);
 397                 chan->desc = NULL;
 398         }
 399
 400         vchan_get_all_descriptors(&chan->vchan, &head);
 401         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 402         vchan_dma_desc_free_list(&chan->vchan, &head);
 403
 404         return 0;
 405 }
 406
 407 static void stm32_dma_synchronize(struct dma_chan *c)
 408 {
 409         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 410
 411         vchan_synchronize(&chan->vchan);
 412 }
 413
 414 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 415 {
 416         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 417         u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 418         u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 419         u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 420         u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 421         u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 422         u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 423
 424         dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 425         dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 426         dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 427         dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 428         dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 429         dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 430 }
 431
 432 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 433
 434 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 435 {
 436         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 437         struct virt_dma_desc *vdesc;
 438         struct stm32_dma_sg_req *sg_req;
 439         struct stm32_dma_chan_reg *reg;
 440         u32 status;
 441         int ret;
 442
 443         ret = stm32_dma_disable_chan(chan);
 444         if (ret < 0)
 445                 return;
 446
 447         if (!chan->desc) {
 448                 vdesc = vchan_next_desc(&chan->vchan);
 449                 if (!vdesc)
 450                         return;
 451
 452                 chan->desc = to_stm32_dma_desc(vdesc);
 453                 chan->next_sg = 0;
 454         }
 455
 456         if (chan->next_sg == chan->desc->num_sgs)
 457                 chan->next_sg = 0;
 458
 459         sg_req = &chan->desc->sg_req[chan->next_sg];
 460         reg = &sg_req->chan_reg;
 461
 462         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 463         stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 464         stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 465         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 466         stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 467         stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 468
 469         chan->next_sg++;
 470
 471         /* Clear interrupt status if it is there */
 472         status = stm32_dma_irq_status(chan);
 473         if (status)
 474                 stm32_dma_irq_clear(chan, status);
 475
 476         if (chan->desc->cyclic)
 477                 stm32_dma_configure_next_sg(chan);
 478
 479         stm32_dma_dump_reg(chan);
 480
 481         /* Start DMA */
 482         reg->dma_scr |= STM32_DMA_SCR_EN;
 483         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 484
 485         chan->busy = true;
 486
 487         dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan);
 488 }
 489
 490 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 491 {
 492         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 493         struct stm32_dma_sg_req *sg_req;
 494         u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 495
 496         id = chan->id;
 497         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 498
 499         if (dma_scr & STM32_DMA_SCR_DBM) {
 500                 if (chan->next_sg == chan->desc->num_sgs)
 501                         chan->next_sg = 0;
 502
 503                 sg_req = &chan->desc->sg_req[chan->next_sg];
 504
 505                 if (dma_scr & STM32_DMA_SCR_CT) {
 506                         dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 507                         stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 508                         dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 509                                 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 510                 } else {
 511                         dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 512                         stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 513                         dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 514                                 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 515                 }
 516         }
 517 }
 518
 519 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 520 {
 521         if (chan->desc) {
 522                 if (chan->desc->cyclic) {
 523                         vchan_cyclic_callback(&chan->desc->vdesc);
 524                         chan->next_sg++;
 525                         stm32_dma_configure_next_sg(chan);
 526                 } else {
 527                         chan->busy = false;
 528                         if (chan->next_sg == chan->desc->num_sgs) {
 529                                 list_del(&chan->desc->vdesc.node);
 530                                 vchan_cookie_complete(&chan->desc->vdesc);
 531                                 chan->desc = NULL;
 532                         }
 533                         stm32_dma_start_transfer(chan);
 534                 }
 535         }
 536 }
 537
 538 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 539 {
 540         struct stm32_dma_chan *chan = devid;
 541         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 542         u32 status, scr;
 543
 544         spin_lock(&chan->vchan.lock);
 545
 546         status = stm32_dma_irq_status(chan);
 547         scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 548
 549         if ((status & STM32_DMA_TCI) && (scr & STM32_DMA_SCR_TCIE)) {
 550                 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 551                 stm32_dma_handle_chan_done(chan);
 552
 553         } else {
 554                 stm32_dma_irq_clear(chan, status);
 555                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 556         }
 557
 558         spin_unlock(&chan->vchan.lock);
 559
 560         return IRQ_HANDLED;
 561 }
 562
 563 static void stm32_dma_issue_pending(struct dma_chan *c)
 564 {
 565         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&chan->vchan.lock, flags);
 569         if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 570                 dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan);
 571                 stm32_dma_start_transfer(chan);
 572
 573         }
 574         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 575 }
 576
 577 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 578                                     enum dma_transfer_direction direction,
 579                                     enum dma_slave_buswidth *buswidth)
 580 {
 581         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 582         int src_bus_width, dst_bus_width;
 583         int src_burst_size, dst_burst_size;
 584         u32 src_maxburst, dst_maxburst;
 585         u32 dma_scr = 0;
 586
 587         src_addr_width = chan->dma_sconfig.src_addr_width;
 588         dst_addr_width = chan->dma_sconfig.dst_addr_width;
 589         src_maxburst = chan->dma_sconfig.src_maxburst;
 590         dst_maxburst = chan->dma_sconfig.dst_maxburst;
 591
 592         switch (direction) {
 593         case DMA_MEM_TO_DEV:
 594                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 595                 if (dst_bus_width < 0)
 596                         return dst_bus_width;
 597
 598                 dst_burst_size = stm32_dma_get_burst(chan, dst_maxburst);
 599                 if (dst_burst_size < 0)
 600                         return dst_burst_size;
 601
 602                 if (!src_addr_width)
 603                         src_addr_width = dst_addr_width;
 604
 605                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 606                 if (src_bus_width < 0)
 607                         return src_bus_width;
 608
 609                 src_burst_size = stm32_dma_get_burst(chan, src_maxburst);
 610                 if (src_burst_size < 0)
 611                         return src_burst_size;
 612
 613                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 614                         STM32_DMA_SCR_PSIZE(dst_bus_width) |
 615                         STM32_DMA_SCR_MSIZE(src_bus_width) |
 616                         STM32_DMA_SCR_PBURST(dst_burst_size) |
 617                         STM32_DMA_SCR_MBURST(src_burst_size);
 618
 619                 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 620                 *buswidth = dst_addr_width;
 621                 break;
 622
 623         case DMA_DEV_TO_MEM:
 624                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 625                 if (src_bus_width < 0)
 626                         return src_bus_width;
 627
 628                 src_burst_size = stm32_dma_get_burst(chan, src_maxburst);
 629                 if (src_burst_size < 0)
 630                         return src_burst_size;
 631
 632                 if (!dst_addr_width)
 633                         dst_addr_width = src_addr_width;
 634
 635                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 636                 if (dst_bus_width < 0)
 637                         return dst_bus_width;
 638
 639                 dst_burst_size = stm32_dma_get_burst(chan, dst_maxburst);
 640                 if (dst_burst_size < 0)
 641                         return dst_burst_size;
 642
 643                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 644                         STM32_DMA_SCR_PSIZE(src_bus_width) |
 645                         STM32_DMA_SCR_MSIZE(dst_bus_width) |
 646                         STM32_DMA_SCR_PBURST(src_burst_size) |
 647                         STM32_DMA_SCR_MBURST(dst_burst_size);
 648
 649                 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 650                 *buswidth = chan->dma_sconfig.src_addr_width;
 651                 break;
 652
 653         default:
 654                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 655                 return -EINVAL;
 656         }
 657
 658         stm32_dma_set_fifo_config(chan, src_maxburst, dst_maxburst);
 659
 660         chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 661                         STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 662                         STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 663         chan->chan_reg.dma_scr |= dma_scr;
 664
 665         return 0;
 666 }
 667
 668 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 669 {
 670         memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 671 }
 672
 673 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 674         struct dma_chan *c, struct scatterlist *sgl,
 675         u32 sg_len, enum dma_transfer_direction direction,
 676         unsigned long flags, void *context)
 677 {
 678         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 679         struct stm32_dma_desc *desc;
 680         struct scatterlist *sg;
 681         enum dma_slave_buswidth buswidth;
 682         u32 nb_data_items;
 683         int i, ret;
 684
 685         if (!chan->config_init) {
 686                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 687                 return NULL;
 688         }
 689
 690         if (sg_len < 1) {
 691                 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 692                 return NULL;
 693         }
 694
 695         desc = stm32_dma_alloc_desc(sg_len);
 696         if (!desc)
 697                 return NULL;
 698
 699         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth);
 700         if (ret < 0)
 701                 goto err;
 702
 703         /* Set peripheral flow controller */
 704         if (chan->dma_sconfig.device_fc)
 705                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 706         else
 707                 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 708
 709         for_each_sg(sgl, sg, sg_len, i) {
 710                 desc->sg_req[i].len = sg_dma_len(sg);
 711
 712                 nb_data_items = desc->sg_req[i].len / buswidth;
 713                 if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) {
 714                         dev_err(chan2dev(chan), "nb items not supported\n");
 715                         goto err;
 716                 }
 717
 718                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 719                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 720                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 721                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 722                 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 723                 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 724                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 725         }
 726
 727         desc->num_sgs = sg_len;
 728         desc->cyclic = false;
 729
 730         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 731
 732 err:
 733         kfree(desc);
 734         return NULL;
 735 }
 736
 737 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 738         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 739         size_t period_len, enum dma_transfer_direction direction,
 740         unsigned long flags)
 741 {
 742         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 743         struct stm32_dma_desc *desc;
 744         enum dma_slave_buswidth buswidth;
 745         u32 num_periods, nb_data_items;
 746         int i, ret;
 747
 748         if (!buf_len || !period_len) {
 749                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 750                 return NULL;
 751         }
 752
 753         if (!chan->config_init) {
 754                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 755                 return NULL;
 756         }
 757
 758         if (buf_len % period_len) {
 759                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 760                 return NULL;
 761         }
 762
 763         /*
 764          * We allow to take more number of requests till DMA is
 765          * not started. The driver will loop over all requests.
 766          * Once DMA is started then new requests can be queued only after
 767          * terminating the DMA.
 768          */
 769         if (chan->busy) {
 770                 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 771                 return NULL;
 772         }
 773
 774         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth);
 775         if (ret < 0)
 776                 return NULL;
 777
 778         nb_data_items = period_len / buswidth;
 779         if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) {
 780                 dev_err(chan2dev(chan), "number of items not supported\n");
 781                 return NULL;
 782         }
 783
 784         /*  Enable Circular mode or double buffer mode */
 785         if (buf_len == period_len)
 786                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 787         else
 788                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 789
 790         /* Clear periph ctrl if client set it */
 791         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 792
 793         num_periods = buf_len / period_len;
 794
 795         desc = stm32_dma_alloc_desc(num_periods);
 796         if (!desc)
 797                 return NULL;
 798
 799         for (i = 0; i < num_periods; i++) {
 800                 desc->sg_req[i].len = period_len;
 801
 802                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 803                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 804                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 805                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 806                 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
 807                 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
 808                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 809                 buf_addr += period_len;
 810         }
 811
 812         desc->num_sgs = num_periods;
 813         desc->cyclic = true;
 814
 815         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 816 }
 817
 818 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
 819         struct dma_chan *c, dma_addr_t dest,
 820         dma_addr_t src, size_t len, unsigned long flags)
 821 {
 822         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 823         u32 num_sgs;
 824         struct stm32_dma_desc *desc;
 825         size_t xfer_count, offset;
 826         int i;
 827
 828         num_sgs = DIV_ROUND_UP(len, STM32_DMA_MAX_DATA_ITEMS);
 829         desc = stm32_dma_alloc_desc(num_sgs);
 830         if (!desc)
 831                 return NULL;
 832
 833         for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
 834                 xfer_count = min_t(size_t, len - offset,
 835                                    STM32_DMA_MAX_DATA_ITEMS);
 836
 837                 desc->sg_req[i].len = xfer_count;
 838
 839                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 840                 desc->sg_req[i].chan_reg.dma_scr =
 841                         STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
 842                         STM32_DMA_SCR_MINC |
 843                         STM32_DMA_SCR_PINC |
 844                         STM32_DMA_SCR_TCIE |
 845                         STM32_DMA_SCR_TEIE;
 846                 desc->sg_req[i].chan_reg.dma_sfcr = STM32_DMA_SFCR_DMDIS |
 847                         STM32_DMA_SFCR_FTH(STM32_DMA_FIFO_THRESHOLD_FULL) |
 848                         STM32_DMA_SFCR_FEIE;
 849                 desc->sg_req[i].chan_reg.dma_spar = src + offset;
 850                 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
 851                 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
 852         }
 853
 854         desc->num_sgs = num_sgs;
 855         desc->cyclic = false;
 856
 857         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 858 }
 859
 860 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
 861 {
 862         u32 dma_scr, width, ndtr;
 863         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 864
 865         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 866         width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
 867         ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 868
 869         return ndtr << width;
 870 }
 871
 872 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
 873                                      struct stm32_dma_desc *desc,
 874                                      u32 next_sg)
 875 {
 876         u32 residue = 0;
 877         int i;
 878
 879         /*
 880          * In cyclic mode, for the last period, residue = remaining bytes from
 881          * NDTR
 882          */
 883         if (chan->desc->cyclic && next_sg == 0)
 884                 return stm32_dma_get_remaining_bytes(chan);
 885
 886         /*
 887          * For all other periods in cyclic mode, and in sg mode,
 888          * residue = remaining bytes from NDTR + remaining periods/sg to be
 889          * transferred
 890          */
 891         for (i = next_sg; i < desc->num_sgs; i++)
 892                 residue += desc->sg_req[i].len;
 893         residue += stm32_dma_get_remaining_bytes(chan);
 894
 895         return residue;
 896 }
 897
 898 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
 899                                            dma_cookie_t cookie,
 900                                            struct dma_tx_state *state)
 901 {
 902         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 903         struct virt_dma_desc *vdesc;
 904         enum dma_status status;
 905         unsigned long flags;
 906         u32 residue = 0;
 907
 908         status = dma_cookie_status(c, cookie, state);
 909         if ((status == DMA_COMPLETE) || (!state))
 910                 return status;
 911
 912         spin_lock_irqsave(&chan->vchan.lock, flags);
 913         vdesc = vchan_find_desc(&chan->vchan, cookie);
 914         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
 915                 residue = stm32_dma_desc_residue(chan, chan->desc,
 916                                                  chan->next_sg);
 917         else if (vdesc)
 918                 residue = stm32_dma_desc_residue(chan,
 919                                                  to_stm32_dma_desc(vdesc), 0);
 920         dma_set_residue(state, residue);
 921
 922         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 923
 924         return status;
 925 }
 926
 927 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
 928 {
 929         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 930         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 931         int ret;
 932
 933         chan->config_init = false;
 934         ret = clk_prepare_enable(dmadev->clk);
 935         if (ret < 0) {
 936                 dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);
 937                 return ret;
 938         }
 939
 940         ret = stm32_dma_disable_chan(chan);
 941         if (ret < 0)
 942                 clk_disable_unprepare(dmadev->clk);
 943
 944         return ret;
 945 }
 946
 947 static void stm32_dma_free_chan_resources(struct dma_chan *c)
 948 {
 949         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 950         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 951         unsigned long flags;
 952
 953         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
 954
 955         if (chan->busy) {
 956                 spin_lock_irqsave(&chan->vchan.lock, flags);
 957                 stm32_dma_stop(chan);
 958                 chan->desc = NULL;
 959                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
 960         }
 961
 962         clk_disable_unprepare(dmadev->clk);
 963
 964         vchan_free_chan_resources(to_virt_chan(c));
 965 }
 966
 967 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
 968 {
 969         kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
 970 }
 971
 972 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
 973                           struct stm32_dma_cfg *cfg)
 974 {
 975         stm32_dma_clear_reg(&chan->chan_reg);
 976
 977         chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
 978         chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
 979
 980         /* Enable Interrupts  */
 981         chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
 982
 983         chan->chan_reg.dma_sfcr = cfg->threshold & STM32_DMA_SFCR_FTH_MASK;
 984 }
 985
 986 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
 987                                            struct of_dma *ofdma)
 988 {
 989         struct stm32_dma_device *dmadev = ofdma->of_dma_data;
 990         struct device *dev = dmadev->ddev.dev;
 991         struct stm32_dma_cfg cfg;
 992         struct stm32_dma_chan *chan;
 993         struct dma_chan *c;
 994
 995         if (dma_spec->args_count < 4) {
 996                 dev_err(dev, "Bad number of cells\n");
 997                 return NULL;
 998         }
 999
1000         cfg.channel_id = dma_spec->args[0];
1001         cfg.request_line = dma_spec->args[1];
1002         cfg.stream_config = dma_spec->args[2];
1003         cfg.threshold = dma_spec->args[3];
1004
1005         if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
1006             (cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
1007                 dev_err(dev, "Bad channel and/or request id\n");
1008                 return NULL;
1009         }
1010
1011         chan = &dmadev->chan[cfg.channel_id];
1012
1013         c = dma_get_slave_channel(&chan->vchan.chan);
1014         if (!c) {
1015                 dev_err(dev, "No more channels available\n");
1016                 return NULL;
1017         }
1018
1019         stm32_dma_set_config(chan, &cfg);
1020
1021         return c;
1022 }
1023
1024 static const struct of_device_id stm32_dma_of_match[] = {
1025         { .compatible = "st,stm32-dma", },
1026         { /* sentinel */ },
1027 };
1028 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1029
1030 static int stm32_dma_probe(struct platform_device *pdev)
1031 {
1032         struct stm32_dma_chan *chan;
1033         struct stm32_dma_device *dmadev;
1034         struct dma_device *dd;
1035         const struct of_device_id *match;
1036         struct resource *res;
1037         int i, ret;
1038
1039         match = of_match_device(stm32_dma_of_match, &pdev->dev);
1040         if (!match) {
1041                 dev_err(&pdev->dev, "Error: No device match found\n");
1042                 return -ENODEV;
1043         }
1044
1045         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1046         if (!dmadev)
1047                 return -ENOMEM;
1048
1049         dd = &dmadev->ddev;
1050
1051         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1053         if (IS_ERR(dmadev->base))
1054                 return PTR_ERR(dmadev->base);
1055
1056         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1057         if (IS_ERR(dmadev->clk)) {
1058                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1059                 return PTR_ERR(dmadev->clk);
1060         }
1061
1062         dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1063                                                 "st,mem2mem");
1064
1065         dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1066         if (!IS_ERR(dmadev->rst)) {
1067                 reset_control_assert(dmadev->rst);
1068                 udelay(2);
1069                 reset_control_deassert(dmadev->rst);
1070         }
1071
1072         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1073         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1074         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1075         dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1076         dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1077         dd->device_tx_status = stm32_dma_tx_status;
1078         dd->device_issue_pending = stm32_dma_issue_pending;
1079         dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1080         dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1081         dd->device_config = stm32_dma_slave_config;
1082         dd->device_terminate_all = stm32_dma_terminate_all;
1083         dd->device_synchronize = stm32_dma_synchronize;
1084         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1085                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1086                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1087         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1088                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1089                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1090         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1091         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1092         dd->max_burst = STM32_DMA_MAX_BURST;
1093         dd->dev = &pdev->dev;
1094         INIT_LIST_HEAD(&dd->channels);
1095
1096         if (dmadev->mem2mem) {
1097                 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1098                 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1099                 dd->directions |= BIT(DMA_MEM_TO_MEM);
1100         }
1101
1102         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1103                 chan = &dmadev->chan[i];
1104                 chan->id = i;
1105                 chan->vchan.desc_free = stm32_dma_desc_free;
1106                 vchan_init(&chan->vchan, dd);
1107         }
1108
1109         ret = dma_async_device_register(dd);
1110         if (ret)
1111                 return ret;
1112
1113         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1114                 chan = &dmadev->chan[i];
1115                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1116                 if (!res) {
1117                         ret = -EINVAL;
1118                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1119                         goto err_unregister;
1120                 }
1121                 chan->irq = res->start;
1122                 ret = devm_request_irq(&pdev->dev, chan->irq,
1123                                        stm32_dma_chan_irq, 0,
1124                                        dev_name(chan2dev(chan)), chan);
1125                 if (ret) {
1126                         dev_err(&pdev->dev,
1127                                 "request_irq failed with err %d channel %d\n",
1128                                 ret, i);
1129                         goto err_unregister;
1130                 }
1131         }
1132
1133         ret = of_dma_controller_register(pdev->dev.of_node,
1134                                          stm32_dma_of_xlate, dmadev);
1135         if (ret < 0) {
1136                 dev_err(&pdev->dev,
1137                         "STM32 DMA DMA OF registration failed %d\n", ret);
1138                 goto err_unregister;
1139         }
1140
1141         platform_set_drvdata(pdev, dmadev);
1142
1143         dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1144
1145         return 0;
1146
1147 err_unregister:
1148         dma_async_device_unregister(dd);
1149
1150         return ret;
1151 }
1152
1153 static struct platform_driver stm32_dma_driver = {
1154         .driver = {
1155                 .name = "stm32-dma",
1156                 .of_match_table = stm32_dma_of_match,
1157         },
1158 };
1159
1160 static int __init stm32_dma_init(void)
1161 {
1162         return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe);
1163 }
1164 subsys_initcall(stm32_dma_init);