2 * Qualcomm Technologies HIDMA DMA engine interface
4 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
18 * Copyright (C) Semihalf 2009
19 * Copyright (C) Ilya Yanok, Emcraft Systems 2010
20 * Copyright (C) Alexander Popov, Promcontroller 2014
22 * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
23 * (defines, structures and comments) was taken from MPC5121 DMA driver
24 * written by Hongjun Chen <hong-jun.chen@freescale.com>.
26 * Approved as OSADL project by a majority of OSADL members and funded
27 * by OSADL membership fees in 2009; for details see www.osadl.org.
29 * This program is free software; you can redistribute it and/or modify it
30 * under the terms of the GNU General Public License as published by the Free
31 * Software Foundation; either version 2 of the License, or (at your option)
34 * This program is distributed in the hope that it will be useful, but WITHOUT
35 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
39 * The full GNU General Public License is included in this distribution in the
40 * file called COPYING.
43 /* Linux Foundation elects GPLv2 license only. */
45 #include <linux/dmaengine.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/list.h>
48 #include <linux/module.h>
49 #include <linux/platform_device.h>
50 #include <linux/slab.h>
51 #include <linux/spinlock.h>
52 #include <linux/of_dma.h>
53 #include <linux/property.h>
54 #include <linux/delay.h>
55 #include <linux/acpi.h>
56 #include <linux/irq.h>
57 #include <linux/atomic.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/msi.h>
61 #include "../dmaengine.h"
65 * Default idle time is 2 seconds. This parameter can
66 * be overridden by changing the following
67 * /sys/bus/platform/devices/QCOM8061:<xy>/power/autosuspend_delay_ms
70 #define HIDMA_AUTOSUSPEND_TIMEOUT 2000
71 #define HIDMA_ERR_INFO_SW 0xFF
72 #define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE 0x0
73 #define HIDMA_NR_DEFAULT_DESC 10
74 #define HIDMA_MSI_INTS 11
76 static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev)
78 return container_of(dmadev, struct hidma_dev, ddev);
82 struct hidma_dev *to_hidma_dev_from_lldev(struct hidma_lldev **_lldevp)
84 return container_of(_lldevp, struct hidma_dev, lldev);
87 static inline struct hidma_chan *to_hidma_chan(struct dma_chan *dmach)
89 return container_of(dmach, struct hidma_chan, chan);
93 struct hidma_desc *to_hidma_desc(struct dma_async_tx_descriptor *t)
95 return container_of(t, struct hidma_desc, desc);
98 static void hidma_free(struct hidma_dev *dmadev)
100 INIT_LIST_HEAD(&dmadev->ddev.channels);
103 static unsigned int nr_desc_prm;
104 module_param(nr_desc_prm, uint, 0644);
105 MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
108 /* process completed descriptors */
109 static void hidma_process_completed(struct hidma_chan *mchan)
111 struct dma_device *ddev = mchan->chan.device;
112 struct hidma_dev *mdma = to_hidma_dev(ddev);
113 struct dma_async_tx_descriptor *desc;
114 dma_cookie_t last_cookie;
115 struct hidma_desc *mdesc;
116 struct hidma_desc *next;
117 unsigned long irqflags;
118 struct list_head list;
120 INIT_LIST_HEAD(&list);
122 /* Get all completed descriptors */
123 spin_lock_irqsave(&mchan->lock, irqflags);
124 list_splice_tail_init(&mchan->completed, &list);
125 spin_unlock_irqrestore(&mchan->lock, irqflags);
127 /* Execute callbacks and run dependencies */
128 list_for_each_entry_safe(mdesc, next, &list, node) {
129 enum dma_status llstat;
130 struct dmaengine_desc_callback cb;
131 struct dmaengine_result result;
134 last_cookie = desc->cookie;
136 llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch);
138 spin_lock_irqsave(&mchan->lock, irqflags);
139 if (llstat == DMA_COMPLETE) {
140 mchan->last_success = last_cookie;
141 result.result = DMA_TRANS_NOERROR;
143 result.result = DMA_TRANS_ABORTED;
146 dma_cookie_complete(desc);
147 spin_unlock_irqrestore(&mchan->lock, irqflags);
149 dmaengine_desc_get_callback(desc, &cb);
151 dma_run_dependencies(desc);
153 spin_lock_irqsave(&mchan->lock, irqflags);
154 list_move(&mdesc->node, &mchan->free);
155 spin_unlock_irqrestore(&mchan->lock, irqflags);
157 dmaengine_desc_callback_invoke(&cb, &result);
162 * Called once for each submitted descriptor.
163 * PM is locked once for each descriptor that is currently
166 static void hidma_callback(void *data)
168 struct hidma_desc *mdesc = data;
169 struct hidma_chan *mchan = to_hidma_chan(mdesc->desc.chan);
170 struct dma_device *ddev = mchan->chan.device;
171 struct hidma_dev *dmadev = to_hidma_dev(ddev);
172 unsigned long irqflags;
175 spin_lock_irqsave(&mchan->lock, irqflags);
176 if (mdesc->node.next) {
177 /* Delete from the active list, add to completed list */
178 list_move_tail(&mdesc->node, &mchan->completed);
181 /* calculate the next running descriptor */
182 mchan->running = list_first_entry(&mchan->active,
183 struct hidma_desc, node);
185 spin_unlock_irqrestore(&mchan->lock, irqflags);
187 hidma_process_completed(mchan);
190 pm_runtime_mark_last_busy(dmadev->ddev.dev);
191 pm_runtime_put_autosuspend(dmadev->ddev.dev);
195 static int hidma_chan_init(struct hidma_dev *dmadev, u32 dma_sig)
197 struct hidma_chan *mchan;
198 struct dma_device *ddev;
200 mchan = devm_kzalloc(dmadev->ddev.dev, sizeof(*mchan), GFP_KERNEL);
204 ddev = &dmadev->ddev;
205 mchan->dma_sig = dma_sig;
206 mchan->dmadev = dmadev;
207 mchan->chan.device = ddev;
208 dma_cookie_init(&mchan->chan);
210 INIT_LIST_HEAD(&mchan->free);
211 INIT_LIST_HEAD(&mchan->prepared);
212 INIT_LIST_HEAD(&mchan->active);
213 INIT_LIST_HEAD(&mchan->completed);
214 INIT_LIST_HEAD(&mchan->queued);
216 spin_lock_init(&mchan->lock);
217 list_add_tail(&mchan->chan.device_node, &ddev->channels);
218 dmadev->ddev.chancnt++;
222 static void hidma_issue_task(unsigned long arg)
224 struct hidma_dev *dmadev = (struct hidma_dev *)arg;
226 pm_runtime_get_sync(dmadev->ddev.dev);
227 hidma_ll_start(dmadev->lldev);
230 static void hidma_issue_pending(struct dma_chan *dmach)
232 struct hidma_chan *mchan = to_hidma_chan(dmach);
233 struct hidma_dev *dmadev = mchan->dmadev;
235 struct hidma_desc *qdesc, *next;
238 spin_lock_irqsave(&mchan->lock, flags);
239 list_for_each_entry_safe(qdesc, next, &mchan->queued, node) {
240 hidma_ll_queue_request(dmadev->lldev, qdesc->tre_ch);
241 list_move_tail(&qdesc->node, &mchan->active);
244 if (!mchan->running) {
245 struct hidma_desc *desc = list_first_entry(&mchan->active,
248 mchan->running = desc;
250 spin_unlock_irqrestore(&mchan->lock, flags);
252 /* PM will be released in hidma_callback function. */
253 status = pm_runtime_get(dmadev->ddev.dev);
255 tasklet_schedule(&dmadev->task);
257 hidma_ll_start(dmadev->lldev);
260 static inline bool hidma_txn_is_success(dma_cookie_t cookie,
261 dma_cookie_t last_success, dma_cookie_t last_used)
263 if (last_success <= last_used) {
264 if ((cookie <= last_success) || (cookie > last_used))
267 if ((cookie <= last_success) && (cookie > last_used))
273 static enum dma_status hidma_tx_status(struct dma_chan *dmach,
275 struct dma_tx_state *txstate)
277 struct hidma_chan *mchan = to_hidma_chan(dmach);
280 ret = dma_cookie_status(dmach, cookie, txstate);
281 if (ret == DMA_COMPLETE) {
284 is_success = hidma_txn_is_success(cookie, mchan->last_success,
286 return is_success ? ret : DMA_ERROR;
289 if (mchan->paused && (ret == DMA_IN_PROGRESS)) {
291 dma_cookie_t runcookie;
293 spin_lock_irqsave(&mchan->lock, flags);
295 runcookie = mchan->running->desc.cookie;
299 if (runcookie == cookie)
302 spin_unlock_irqrestore(&mchan->lock, flags);
309 * Submit descriptor to hardware.
310 * Lock the PM for each descriptor we are sending.
312 static dma_cookie_t hidma_tx_submit(struct dma_async_tx_descriptor *txd)
314 struct hidma_chan *mchan = to_hidma_chan(txd->chan);
315 struct hidma_dev *dmadev = mchan->dmadev;
316 struct hidma_desc *mdesc;
317 unsigned long irqflags;
320 pm_runtime_get_sync(dmadev->ddev.dev);
321 if (!hidma_ll_isenabled(dmadev->lldev)) {
322 pm_runtime_mark_last_busy(dmadev->ddev.dev);
323 pm_runtime_put_autosuspend(dmadev->ddev.dev);
326 pm_runtime_mark_last_busy(dmadev->ddev.dev);
327 pm_runtime_put_autosuspend(dmadev->ddev.dev);
329 mdesc = container_of(txd, struct hidma_desc, desc);
330 spin_lock_irqsave(&mchan->lock, irqflags);
332 /* Move descriptor to queued */
333 list_move_tail(&mdesc->node, &mchan->queued);
336 cookie = dma_cookie_assign(txd);
338 spin_unlock_irqrestore(&mchan->lock, irqflags);
343 static int hidma_alloc_chan_resources(struct dma_chan *dmach)
345 struct hidma_chan *mchan = to_hidma_chan(dmach);
346 struct hidma_dev *dmadev = mchan->dmadev;
347 struct hidma_desc *mdesc, *tmp;
348 unsigned long irqflags;
353 if (mchan->allocated)
356 /* Alloc descriptors for this channel */
357 for (i = 0; i < dmadev->nr_descriptors; i++) {
358 mdesc = kzalloc(sizeof(struct hidma_desc), GFP_NOWAIT);
363 dma_async_tx_descriptor_init(&mdesc->desc, dmach);
364 mdesc->desc.tx_submit = hidma_tx_submit;
366 rc = hidma_ll_request(dmadev->lldev, mchan->dma_sig,
367 "DMA engine", hidma_callback, mdesc,
370 dev_err(dmach->device->dev,
371 "channel alloc failed at %u\n", i);
375 list_add_tail(&mdesc->node, &descs);
379 /* return the allocated descriptors */
380 list_for_each_entry_safe(mdesc, tmp, &descs, node) {
381 hidma_ll_free(dmadev->lldev, mdesc->tre_ch);
387 spin_lock_irqsave(&mchan->lock, irqflags);
388 list_splice_tail_init(&descs, &mchan->free);
389 mchan->allocated = true;
390 spin_unlock_irqrestore(&mchan->lock, irqflags);
394 static struct dma_async_tx_descriptor *
395 hidma_prep_dma_memcpy(struct dma_chan *dmach, dma_addr_t dest, dma_addr_t src,
396 size_t len, unsigned long flags)
398 struct hidma_chan *mchan = to_hidma_chan(dmach);
399 struct hidma_desc *mdesc = NULL;
400 struct hidma_dev *mdma = mchan->dmadev;
401 unsigned long irqflags;
403 /* Get free descriptor */
404 spin_lock_irqsave(&mchan->lock, irqflags);
405 if (!list_empty(&mchan->free)) {
406 mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
407 list_del(&mdesc->node);
409 spin_unlock_irqrestore(&mchan->lock, irqflags);
414 mdesc->desc.flags = flags;
415 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
416 src, dest, len, flags,
419 /* Place descriptor in prepared list */
420 spin_lock_irqsave(&mchan->lock, irqflags);
421 list_add_tail(&mdesc->node, &mchan->prepared);
422 spin_unlock_irqrestore(&mchan->lock, irqflags);
427 static struct dma_async_tx_descriptor *
428 hidma_prep_dma_memset(struct dma_chan *dmach, dma_addr_t dest, int value,
429 size_t len, unsigned long flags)
431 struct hidma_chan *mchan = to_hidma_chan(dmach);
432 struct hidma_desc *mdesc = NULL;
433 struct hidma_dev *mdma = mchan->dmadev;
434 unsigned long irqflags;
436 /* Get free descriptor */
437 spin_lock_irqsave(&mchan->lock, irqflags);
438 if (!list_empty(&mchan->free)) {
439 mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
440 list_del(&mdesc->node);
442 spin_unlock_irqrestore(&mchan->lock, irqflags);
447 mdesc->desc.flags = flags;
448 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
449 value, dest, len, flags,
452 /* Place descriptor in prepared list */
453 spin_lock_irqsave(&mchan->lock, irqflags);
454 list_add_tail(&mdesc->node, &mchan->prepared);
455 spin_unlock_irqrestore(&mchan->lock, irqflags);
460 static int hidma_terminate_channel(struct dma_chan *chan)
462 struct hidma_chan *mchan = to_hidma_chan(chan);
463 struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
464 struct hidma_desc *tmp, *mdesc;
465 unsigned long irqflags;
469 pm_runtime_get_sync(dmadev->ddev.dev);
470 /* give completed requests a chance to finish */
471 hidma_process_completed(mchan);
473 spin_lock_irqsave(&mchan->lock, irqflags);
474 mchan->last_success = 0;
475 list_splice_init(&mchan->active, &list);
476 list_splice_init(&mchan->prepared, &list);
477 list_splice_init(&mchan->completed, &list);
478 list_splice_init(&mchan->queued, &list);
479 spin_unlock_irqrestore(&mchan->lock, irqflags);
481 /* this suspends the existing transfer */
482 rc = hidma_ll_disable(dmadev->lldev);
484 dev_err(dmadev->ddev.dev, "channel did not pause\n");
488 /* return all user requests */
489 list_for_each_entry_safe(mdesc, tmp, &list, node) {
490 struct dma_async_tx_descriptor *txd = &mdesc->desc;
492 dma_descriptor_unmap(txd);
493 dmaengine_desc_get_callback_invoke(txd, NULL);
494 dma_run_dependencies(txd);
496 /* move myself to free_list */
497 list_move(&mdesc->node, &mchan->free);
500 rc = hidma_ll_enable(dmadev->lldev);
502 pm_runtime_mark_last_busy(dmadev->ddev.dev);
503 pm_runtime_put_autosuspend(dmadev->ddev.dev);
507 static int hidma_terminate_all(struct dma_chan *chan)
509 struct hidma_chan *mchan = to_hidma_chan(chan);
510 struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
513 rc = hidma_terminate_channel(chan);
517 /* reinitialize the hardware */
518 pm_runtime_get_sync(dmadev->ddev.dev);
519 rc = hidma_ll_setup(dmadev->lldev);
520 pm_runtime_mark_last_busy(dmadev->ddev.dev);
521 pm_runtime_put_autosuspend(dmadev->ddev.dev);
525 static void hidma_free_chan_resources(struct dma_chan *dmach)
527 struct hidma_chan *mchan = to_hidma_chan(dmach);
528 struct hidma_dev *mdma = mchan->dmadev;
529 struct hidma_desc *mdesc, *tmp;
530 unsigned long irqflags;
533 /* terminate running transactions and free descriptors */
534 hidma_terminate_channel(dmach);
536 spin_lock_irqsave(&mchan->lock, irqflags);
539 list_splice_tail_init(&mchan->free, &descs);
541 /* Free descriptors */
542 list_for_each_entry_safe(mdesc, tmp, &descs, node) {
543 hidma_ll_free(mdma->lldev, mdesc->tre_ch);
544 list_del(&mdesc->node);
548 mchan->allocated = 0;
549 spin_unlock_irqrestore(&mchan->lock, irqflags);
552 static int hidma_pause(struct dma_chan *chan)
554 struct hidma_chan *mchan;
555 struct hidma_dev *dmadev;
557 mchan = to_hidma_chan(chan);
558 dmadev = to_hidma_dev(mchan->chan.device);
559 if (!mchan->paused) {
560 pm_runtime_get_sync(dmadev->ddev.dev);
561 if (hidma_ll_disable(dmadev->lldev))
562 dev_warn(dmadev->ddev.dev, "channel did not stop\n");
563 mchan->paused = true;
564 pm_runtime_mark_last_busy(dmadev->ddev.dev);
565 pm_runtime_put_autosuspend(dmadev->ddev.dev);
570 static int hidma_resume(struct dma_chan *chan)
572 struct hidma_chan *mchan;
573 struct hidma_dev *dmadev;
576 mchan = to_hidma_chan(chan);
577 dmadev = to_hidma_dev(mchan->chan.device);
579 pm_runtime_get_sync(dmadev->ddev.dev);
580 rc = hidma_ll_enable(dmadev->lldev);
582 mchan->paused = false;
584 dev_err(dmadev->ddev.dev,
585 "failed to resume the channel");
586 pm_runtime_mark_last_busy(dmadev->ddev.dev);
587 pm_runtime_put_autosuspend(dmadev->ddev.dev);
592 static irqreturn_t hidma_chirq_handler(int chirq, void *arg)
594 struct hidma_lldev *lldev = arg;
597 * All interrupts are request driven.
598 * HW doesn't send an interrupt by itself.
600 return hidma_ll_inthandler(chirq, lldev);
603 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
604 static irqreturn_t hidma_chirq_handler_msi(int chirq, void *arg)
606 struct hidma_lldev **lldevp = arg;
607 struct hidma_dev *dmadev = to_hidma_dev_from_lldev(lldevp);
609 return hidma_ll_inthandler_msi(chirq, *lldevp,
610 1 << (chirq - dmadev->msi_virqbase));
614 static ssize_t hidma_show_values(struct device *dev,
615 struct device_attribute *attr, char *buf)
617 struct platform_device *pdev = to_platform_device(dev);
618 struct hidma_dev *mdev = platform_get_drvdata(pdev);
622 if (strcmp(attr->attr.name, "chid") == 0)
623 sprintf(buf, "%d\n", mdev->chidx);
628 static inline void hidma_sysfs_uninit(struct hidma_dev *dev)
630 device_remove_file(dev->ddev.dev, dev->chid_attrs);
633 static struct device_attribute*
634 hidma_create_sysfs_entry(struct hidma_dev *dev, char *name, int mode)
636 struct device_attribute *attrs;
639 attrs = devm_kmalloc(dev->ddev.dev, sizeof(struct device_attribute),
644 name_copy = devm_kstrdup(dev->ddev.dev, name, GFP_KERNEL);
648 attrs->attr.name = name_copy;
649 attrs->attr.mode = mode;
650 attrs->show = hidma_show_values;
651 sysfs_attr_init(&attrs->attr);
656 static int hidma_sysfs_init(struct hidma_dev *dev)
658 dev->chid_attrs = hidma_create_sysfs_entry(dev, "chid", S_IRUGO);
659 if (!dev->chid_attrs)
662 return device_create_file(dev->ddev.dev, dev->chid_attrs);
665 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
666 static void hidma_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
668 struct device *dev = msi_desc_to_dev(desc);
669 struct hidma_dev *dmadev = dev_get_drvdata(dev);
671 if (!desc->platform.msi_index) {
672 writel(msg->address_lo, dmadev->dev_evca + 0x118);
673 writel(msg->address_hi, dmadev->dev_evca + 0x11C);
674 writel(msg->data, dmadev->dev_evca + 0x120);
679 static void hidma_free_msis(struct hidma_dev *dmadev)
681 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
682 struct device *dev = dmadev->ddev.dev;
683 struct msi_desc *desc;
685 /* free allocated MSI interrupts above */
686 for_each_msi_entry(desc, dev)
687 devm_free_irq(dev, desc->irq, &dmadev->lldev);
689 platform_msi_domain_free_irqs(dev);
693 static int hidma_request_msi(struct hidma_dev *dmadev,
694 struct platform_device *pdev)
696 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
698 struct msi_desc *desc;
699 struct msi_desc *failed_desc = NULL;
701 rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS,
702 hidma_write_msi_msg);
706 for_each_msi_entry(desc, &pdev->dev) {
707 if (!desc->platform.msi_index)
708 dmadev->msi_virqbase = desc->irq;
710 rc = devm_request_irq(&pdev->dev, desc->irq,
711 hidma_chirq_handler_msi,
721 /* free allocated MSI interrupts above */
722 for_each_msi_entry(desc, &pdev->dev) {
723 if (desc == failed_desc)
725 devm_free_irq(&pdev->dev, desc->irq,
729 /* Add callback to free MSIs on teardown */
730 hidma_ll_setup_irq(dmadev->lldev, true);
735 "failed to request MSI irq, falling back to wired IRQ\n");
742 static bool hidma_msi_capable(struct device *dev)
744 struct acpi_device *adev = ACPI_COMPANION(dev);
745 const char *of_compat;
748 if (!adev || acpi_disabled) {
749 ret = device_property_read_string(dev, "compatible",
754 ret = strcmp(of_compat, "qcom,hidma-1.1");
757 ret = strcmp(acpi_device_hid(adev), "QCOM8062");
763 static int hidma_probe(struct platform_device *pdev)
765 struct hidma_dev *dmadev;
766 struct resource *trca_resource;
767 struct resource *evca_resource;
774 pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
775 pm_runtime_use_autosuspend(&pdev->dev);
776 pm_runtime_set_active(&pdev->dev);
777 pm_runtime_enable(&pdev->dev);
779 trca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
780 trca = devm_ioremap_resource(&pdev->dev, trca_resource);
786 evca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
787 evca = devm_ioremap_resource(&pdev->dev, evca_resource);
794 * This driver only handles the channel IRQs.
795 * Common IRQ is handled by the management driver.
797 chirq = platform_get_irq(pdev, 0);
803 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
809 INIT_LIST_HEAD(&dmadev->ddev.channels);
810 spin_lock_init(&dmadev->lock);
811 dmadev->ddev.dev = &pdev->dev;
812 pm_runtime_get_sync(dmadev->ddev.dev);
814 dma_cap_set(DMA_MEMCPY, dmadev->ddev.cap_mask);
815 dma_cap_set(DMA_MEMSET, dmadev->ddev.cap_mask);
816 if (WARN_ON(!pdev->dev.dma_mask)) {
821 dmadev->dev_evca = evca;
822 dmadev->evca_resource = evca_resource;
823 dmadev->dev_trca = trca;
824 dmadev->trca_resource = trca_resource;
825 dmadev->ddev.device_prep_dma_memcpy = hidma_prep_dma_memcpy;
826 dmadev->ddev.device_prep_dma_memset = hidma_prep_dma_memset;
827 dmadev->ddev.device_alloc_chan_resources = hidma_alloc_chan_resources;
828 dmadev->ddev.device_free_chan_resources = hidma_free_chan_resources;
829 dmadev->ddev.device_tx_status = hidma_tx_status;
830 dmadev->ddev.device_issue_pending = hidma_issue_pending;
831 dmadev->ddev.device_pause = hidma_pause;
832 dmadev->ddev.device_resume = hidma_resume;
833 dmadev->ddev.device_terminate_all = hidma_terminate_all;
834 dmadev->ddev.copy_align = 8;
837 * Determine the MSI capability of the platform. Old HW doesn't
840 msi = hidma_msi_capable(&pdev->dev);
842 device_property_read_u32(&pdev->dev, "desc-count",
843 &dmadev->nr_descriptors);
846 dev_info(&pdev->dev, "overriding number of descriptors as %d\n",
848 dmadev->nr_descriptors = nr_desc_prm;
851 if (!dmadev->nr_descriptors)
852 dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
854 dmadev->chidx = readl(dmadev->dev_trca + 0x28);
856 /* Set DMA mask to 64 bits. */
857 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
859 dev_warn(&pdev->dev, "unable to set coherent mask to 64");
860 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
865 dmadev->lldev = hidma_ll_init(dmadev->ddev.dev,
866 dmadev->nr_descriptors, dmadev->dev_trca,
867 dmadev->dev_evca, dmadev->chidx);
868 if (!dmadev->lldev) {
873 platform_set_drvdata(pdev, dmadev);
875 rc = hidma_request_msi(dmadev, pdev);
878 hidma_ll_setup_irq(dmadev->lldev, false);
879 rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler,
880 0, "qcom-hidma", dmadev->lldev);
885 INIT_LIST_HEAD(&dmadev->ddev.channels);
886 rc = hidma_chan_init(dmadev, 0);
890 rc = dma_async_device_register(&dmadev->ddev);
895 tasklet_init(&dmadev->task, hidma_issue_task, (unsigned long)dmadev);
896 hidma_debug_init(dmadev);
897 hidma_sysfs_init(dmadev);
898 dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n");
899 pm_runtime_mark_last_busy(dmadev->ddev.dev);
900 pm_runtime_put_autosuspend(dmadev->ddev.dev);
905 hidma_free_msis(dmadev);
907 hidma_debug_uninit(dmadev);
908 hidma_ll_uninit(dmadev->lldev);
913 pm_runtime_put_sync(&pdev->dev);
914 pm_runtime_disable(&pdev->dev);
918 static void hidma_shutdown(struct platform_device *pdev)
920 struct hidma_dev *dmadev = platform_get_drvdata(pdev);
922 dev_info(dmadev->ddev.dev, "HI-DMA engine shutdown\n");
924 pm_runtime_get_sync(dmadev->ddev.dev);
925 if (hidma_ll_disable(dmadev->lldev))
926 dev_warn(dmadev->ddev.dev, "channel did not stop\n");
927 pm_runtime_mark_last_busy(dmadev->ddev.dev);
928 pm_runtime_put_autosuspend(dmadev->ddev.dev);
932 static int hidma_remove(struct platform_device *pdev)
934 struct hidma_dev *dmadev = platform_get_drvdata(pdev);
936 pm_runtime_get_sync(dmadev->ddev.dev);
937 dma_async_device_unregister(&dmadev->ddev);
938 if (!dmadev->lldev->msi_support)
939 devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
941 hidma_free_msis(dmadev);
943 tasklet_kill(&dmadev->task);
944 hidma_sysfs_uninit(dmadev);
945 hidma_debug_uninit(dmadev);
946 hidma_ll_uninit(dmadev->lldev);
949 dev_info(&pdev->dev, "HI-DMA engine removed\n");
950 pm_runtime_put_sync_suspend(&pdev->dev);
951 pm_runtime_disable(&pdev->dev);
956 #if IS_ENABLED(CONFIG_ACPI)
957 static const struct acpi_device_id hidma_acpi_ids[] = {
962 MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
965 static const struct of_device_id hidma_match[] = {
966 {.compatible = "qcom,hidma-1.0",},
967 {.compatible = "qcom,hidma-1.1",},
970 MODULE_DEVICE_TABLE(of, hidma_match);
972 static struct platform_driver hidma_driver = {
973 .probe = hidma_probe,
974 .remove = hidma_remove,
975 .shutdown = hidma_shutdown,
978 .of_match_table = hidma_match,
979 .acpi_match_table = ACPI_PTR(hidma_acpi_ids),
983 module_platform_driver(hidma_driver);
984 MODULE_LICENSE("GPL v2");