1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * QCOM BAM DMA engine driver
8 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
9 * peripherals on the MSM 8x74. The configuration of the channels are dependent
10 * on the way they are hard wired to that specific peripheral. The peripheral
11 * device tree entries specify the configuration of each channel.
13 * The DMA controller requires the use of external memory for storage of the
14 * hardware descriptors for each channel. The descriptor FIFO is accessed as a
15 * circular buffer and operations are managed according to the offset within the
16 * FIFO. After pipe/channel reset, all of the pipe registers and internal state
17 * are back to defaults.
19 * During DMA operations, we write descriptors to the FIFO, being careful to
20 * handle wrapping and then write the last FIFO offset to that channel's
21 * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register
22 * indicates the current FIFO offset that is being processed, so there is some
23 * indication of where the hardware is currently working.
26 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/slab.h>
30 #include <linux/module.h>
31 #include <linux/interrupt.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/scatterlist.h>
34 #include <linux/device.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_address.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_dma.h>
40 #include <linux/circ_buf.h>
41 #include <linux/clk.h>
42 #include <linux/dmaengine.h>
43 #include <linux/pm_runtime.h>
45 #include "../dmaengine.h"
46 #include "../virt-dma.h"
49 __le32 addr; /* Buffer physical address */
50 __le16 size; /* Buffer size in bytes */
54 #define BAM_DMA_AUTOSUSPEND_DELAY 100
56 #define DESC_FLAG_INT BIT(15)
57 #define DESC_FLAG_EOT BIT(14)
58 #define DESC_FLAG_EOB BIT(13)
59 #define DESC_FLAG_NWD BIT(12)
60 #define DESC_FLAG_CMD BIT(11)
62 struct bam_async_desc {
63 struct virt_dma_desc vd;
68 /* transaction flags, EOT|EOB|NWD */
71 struct bam_desc_hw *curr_desc;
73 /* list node for the desc in the bam_chan list of descriptors */
74 struct list_head desc_node;
75 enum dma_transfer_direction dir;
77 struct bam_desc_hw desc[];
87 BAM_IRQ_SRCS_UNMASKED,
100 BAM_P_EVNT_DEST_ADDR,
103 BAM_P_DATA_FIFO_ADDR,
104 BAM_P_DESC_FIFO_ADDR,
105 BAM_P_EVNT_GEN_TRSHLD,
109 struct reg_offset_data {
111 unsigned int pipe_mult, evnt_mult, ee_mult;
114 static const struct reg_offset_data bam_v1_3_reg_info[] = {
115 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 },
116 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 },
117 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 },
118 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 },
119 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 },
120 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 },
121 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
122 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 },
123 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 },
124 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 },
125 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 },
126 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 },
127 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 },
128 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 },
129 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 },
130 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 },
131 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 },
132 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 },
133 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 },
134 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 },
135 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 },
136 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 },
137 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 },
138 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 },
139 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
140 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 },
143 static const struct reg_offset_data bam_v1_4_reg_info[] = {
144 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 },
145 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 },
146 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 },
147 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 },
148 [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 },
149 [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 },
150 [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
151 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 },
152 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 },
153 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 },
154 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 },
155 [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 },
156 [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 },
157 [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 },
158 [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 },
159 [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 },
160 [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 },
161 [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 },
162 [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 },
163 [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 },
164 [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 },
165 [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 },
166 [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 },
167 [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 },
168 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
169 [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 },
172 static const struct reg_offset_data bam_v1_7_reg_info[] = {
173 [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 },
174 [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 },
175 [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 },
176 [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 },
177 [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 },
178 [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 },
179 [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 },
180 [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 },
181 [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 },
182 [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 },
183 [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 },
184 [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 },
185 [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 },
186 [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 },
187 [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 },
188 [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 },
189 [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 },
190 [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 },
191 [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 },
192 [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 },
193 [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 },
194 [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 },
195 [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 },
196 [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 },
197 [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 },
198 [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 },
202 #define BAM_SW_RST BIT(0)
203 #define BAM_EN BIT(1)
204 #define BAM_EN_ACCUM BIT(4)
205 #define BAM_TESTBUS_SEL_SHIFT 5
206 #define BAM_TESTBUS_SEL_MASK 0x3F
207 #define BAM_DESC_CACHE_SEL_SHIFT 13
208 #define BAM_DESC_CACHE_SEL_MASK 0x3
209 #define BAM_CACHED_DESC_STORE BIT(15)
210 #define IBC_DISABLE BIT(16)
213 #define REVISION_SHIFT 0
214 #define REVISION_MASK 0xFF
215 #define NUM_EES_SHIFT 8
216 #define NUM_EES_MASK 0xF
217 #define CE_BUFFER_SIZE BIT(13)
218 #define AXI_ACTIVE BIT(14)
219 #define USE_VMIDMT BIT(15)
220 #define SECURED BIT(16)
221 #define BAM_HAS_NO_BYPASS BIT(17)
222 #define HIGH_FREQUENCY_BAM BIT(18)
223 #define INACTIV_TMRS_EXST BIT(19)
224 #define NUM_INACTIV_TMRS BIT(20)
225 #define DESC_CACHE_DEPTH_SHIFT 21
226 #define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT)
227 #define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT)
228 #define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT)
229 #define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT)
230 #define CMD_DESC_EN BIT(23)
231 #define INACTIV_TMR_BASE_SHIFT 24
232 #define INACTIV_TMR_BASE_MASK 0xFF
235 #define BAM_NUM_PIPES_SHIFT 0
236 #define BAM_NUM_PIPES_MASK 0xFF
237 #define PERIPH_NON_PIPE_GRP_SHIFT 16
238 #define PERIPH_NON_PIP_GRP_MASK 0xFF
239 #define BAM_NON_PIPE_GRP_SHIFT 24
240 #define BAM_NON_PIPE_GRP_MASK 0xFF
243 #define BAM_PIPE_CNFG BIT(2)
244 #define BAM_FULL_PIPE BIT(11)
245 #define BAM_NO_EXT_P_RST BIT(12)
246 #define BAM_IBC_DISABLE BIT(13)
247 #define BAM_SB_CLK_REQ BIT(14)
248 #define BAM_PSM_CSW_REQ BIT(15)
249 #define BAM_PSM_P_RES BIT(16)
250 #define BAM_AU_P_RES BIT(17)
251 #define BAM_SI_P_RES BIT(18)
252 #define BAM_WB_P_RES BIT(19)
253 #define BAM_WB_BLK_CSW BIT(20)
254 #define BAM_WB_CSW_ACK_IDL BIT(21)
255 #define BAM_WB_RETR_SVPNT BIT(22)
256 #define BAM_WB_DSC_AVL_P_RST BIT(23)
257 #define BAM_REG_P_EN BIT(24)
258 #define BAM_PSM_P_HD_DATA BIT(25)
259 #define BAM_AU_ACCUMED BIT(26)
260 #define BAM_CMD_ENABLE BIT(27)
262 #define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \
272 BAM_WB_CSW_ACK_IDL | \
273 BAM_WB_RETR_SVPNT | \
274 BAM_WB_DSC_AVL_P_RST | \
276 BAM_PSM_P_HD_DATA | \
282 #define P_DIRECTION BIT(3)
283 #define P_SYS_STRM BIT(4)
284 #define P_SYS_MODE BIT(5)
285 #define P_AUTO_EOB BIT(6)
286 #define P_AUTO_EOB_SEL_SHIFT 7
287 #define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT)
288 #define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT)
289 #define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT)
290 #define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT)
291 #define P_PREFETCH_LIMIT_SHIFT 9
292 #define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT)
293 #define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT)
294 #define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT)
295 #define P_WRITE_NWD BIT(11)
296 #define P_LOCK_GROUP_SHIFT 16
297 #define P_LOCK_GROUP_MASK 0x1F
299 /* BAM_DESC_CNT_TRSHLD */
300 #define CNT_TRSHLD 0xffff
301 #define DEFAULT_CNT_THRSHLD 0x4
304 #define BAM_IRQ BIT(31)
305 #define P_IRQ 0x7fffffff
307 /* BAM_IRQ_SRCS_MSK */
308 #define BAM_IRQ_MSK BAM_IRQ
309 #define P_IRQ_MSK P_IRQ
312 #define BAM_TIMER_IRQ BIT(4)
313 #define BAM_EMPTY_IRQ BIT(3)
314 #define BAM_ERROR_IRQ BIT(2)
315 #define BAM_HRESP_ERR_IRQ BIT(1)
318 #define BAM_TIMER_CLR BIT(4)
319 #define BAM_EMPTY_CLR BIT(3)
320 #define BAM_ERROR_CLR BIT(2)
321 #define BAM_HRESP_ERR_CLR BIT(1)
324 #define BAM_TIMER_EN BIT(4)
325 #define BAM_EMPTY_EN BIT(3)
326 #define BAM_ERROR_EN BIT(2)
327 #define BAM_HRESP_ERR_EN BIT(1)
330 #define P_PRCSD_DESC_EN BIT(0)
331 #define P_TIMER_EN BIT(1)
332 #define P_WAKE_EN BIT(2)
333 #define P_OUT_OF_DESC_EN BIT(3)
334 #define P_ERR_EN BIT(4)
335 #define P_TRNSFR_END_EN BIT(5)
336 #define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
339 #define P_SW_OFSTS_MASK 0xffff
341 #define BAM_DESC_FIFO_SIZE SZ_32K
342 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
343 #define BAM_FIFO_SIZE (SZ_32K - 8)
344 #define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\
345 MAX_DESCRIPTORS + 1) == 0)
348 struct virt_dma_chan vc;
350 struct bam_device *bdev;
352 /* configuration from device tree */
355 /* runtime configuration */
356 struct dma_slave_config slave;
359 struct bam_desc_hw *fifo_virt;
360 dma_addr_t fifo_phys;
363 unsigned short head; /* start of active descriptor entries */
364 unsigned short tail; /* end of active descriptor entries */
366 unsigned int initialized; /* is the channel hw initialized? */
367 unsigned int paused; /* is the channel paused? */
368 unsigned int reconfigure; /* new slave config? */
369 /* list of descriptors currently processed */
370 struct list_head desc_list;
372 struct list_head node;
375 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
377 return container_of(common, struct bam_chan, vc.chan);
383 struct dma_device common;
384 struct bam_chan *channels;
388 /* execution environment ID, from DT */
390 bool controlled_remotely;
392 const struct reg_offset_data *layout;
397 /* dma start transaction tasklet */
398 struct tasklet_struct task;
402 * bam_addr - returns BAM register address
404 * @pipe: pipe instance (ignored when register doesn't have multiple instances)
405 * @reg: register enum
407 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
410 const struct reg_offset_data r = bdev->layout[reg];
412 return bdev->regs + r.base_offset +
415 r.ee_mult * bdev->ee;
419 * bam_reset_channel - Reset individual BAM DMA channel
420 * @bchan: bam channel
422 * This function resets a specific BAM channel
424 static void bam_reset_channel(struct bam_chan *bchan)
426 struct bam_device *bdev = bchan->bdev;
428 lockdep_assert_held(&bchan->vc.lock);
431 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
432 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
434 /* don't allow cpu to reorder BAM register accesses done after this */
437 /* make sure hw is initialized when channel is used the first time */
438 bchan->initialized = 0;
442 * bam_chan_init_hw - Initialize channel hardware
443 * @bchan: bam channel
444 * @dir: DMA transfer direction
446 * This function resets and initializes the BAM channel
448 static void bam_chan_init_hw(struct bam_chan *bchan,
449 enum dma_transfer_direction dir)
451 struct bam_device *bdev = bchan->bdev;
454 /* Reset the channel to clear internal state of the FIFO */
455 bam_reset_channel(bchan);
458 * write out 8 byte aligned address. We have enough space for this
459 * because we allocated 1 more descriptor (8 bytes) than we can use
461 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
462 bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
463 writel_relaxed(BAM_FIFO_SIZE,
464 bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
466 /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
467 writel_relaxed(P_DEFAULT_IRQS_EN,
468 bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
470 /* unmask the specific pipe and EE combo */
471 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
472 val |= BIT(bchan->id);
473 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
475 /* don't allow cpu to reorder the channel enable done below */
478 /* set fixed direction and mode, then enable channel */
479 val = P_EN | P_SYS_MODE;
480 if (dir == DMA_DEV_TO_MEM)
483 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
485 bchan->initialized = 1;
487 /* init FIFO pointers */
493 * bam_alloc_chan - Allocate channel resources for DMA channel.
494 * @chan: specified channel
496 * This function allocates the FIFO descriptor memory
498 static int bam_alloc_chan(struct dma_chan *chan)
500 struct bam_chan *bchan = to_bam_chan(chan);
501 struct bam_device *bdev = bchan->bdev;
503 if (bchan->fifo_virt)
506 /* allocate FIFO descriptor space, but only if necessary */
507 bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
508 &bchan->fifo_phys, GFP_KERNEL);
510 if (!bchan->fifo_virt) {
511 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
519 * bam_free_chan - Frees dma resources associated with specific channel
520 * @chan: specified channel
522 * Free the allocated fifo descriptor memory and channel resources
525 static void bam_free_chan(struct dma_chan *chan)
527 struct bam_chan *bchan = to_bam_chan(chan);
528 struct bam_device *bdev = bchan->bdev;
533 ret = pm_runtime_get_sync(bdev->dev);
537 vchan_free_chan_resources(to_virt_chan(chan));
539 if (!list_empty(&bchan->desc_list)) {
540 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
544 spin_lock_irqsave(&bchan->vc.lock, flags);
545 bam_reset_channel(bchan);
546 spin_unlock_irqrestore(&bchan->vc.lock, flags);
548 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
550 bchan->fifo_virt = NULL;
552 /* mask irq for pipe/channel */
553 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
554 val &= ~BIT(bchan->id);
555 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
558 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
561 pm_runtime_mark_last_busy(bdev->dev);
562 pm_runtime_put_autosuspend(bdev->dev);
566 * bam_slave_config - set slave configuration for channel
568 * @cfg: slave configuration
570 * Sets slave configuration for channel
573 static int bam_slave_config(struct dma_chan *chan,
574 struct dma_slave_config *cfg)
576 struct bam_chan *bchan = to_bam_chan(chan);
579 spin_lock_irqsave(&bchan->vc.lock, flag);
580 memcpy(&bchan->slave, cfg, sizeof(*cfg));
581 bchan->reconfigure = 1;
582 spin_unlock_irqrestore(&bchan->vc.lock, flag);
588 * bam_prep_slave_sg - Prep slave sg transaction
591 * @sgl: scatter gather list
592 * @sg_len: length of sg
593 * @direction: DMA transfer direction
595 * @context: transfer context (unused)
597 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
598 struct scatterlist *sgl, unsigned int sg_len,
599 enum dma_transfer_direction direction, unsigned long flags,
602 struct bam_chan *bchan = to_bam_chan(chan);
603 struct bam_device *bdev = bchan->bdev;
604 struct bam_async_desc *async_desc;
605 struct scatterlist *sg;
607 struct bam_desc_hw *desc;
608 unsigned int num_alloc = 0;
611 if (!is_slave_direction(direction)) {
612 dev_err(bdev->dev, "invalid dma direction\n");
616 /* calculate number of required entries */
617 for_each_sg(sgl, sg, sg_len, i)
618 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE);
620 /* allocate enough room to accomodate the number of entries */
621 async_desc = kzalloc(struct_size(async_desc, desc, num_alloc),
627 if (flags & DMA_PREP_FENCE)
628 async_desc->flags |= DESC_FLAG_NWD;
630 if (flags & DMA_PREP_INTERRUPT)
631 async_desc->flags |= DESC_FLAG_EOT;
633 async_desc->num_desc = num_alloc;
634 async_desc->curr_desc = async_desc->desc;
635 async_desc->dir = direction;
637 /* fill in temporary descriptors */
638 desc = async_desc->desc;
639 for_each_sg(sgl, sg, sg_len, i) {
640 unsigned int remainder = sg_dma_len(sg);
641 unsigned int curr_offset = 0;
644 if (flags & DMA_PREP_CMD)
645 desc->flags |= cpu_to_le16(DESC_FLAG_CMD);
647 desc->addr = cpu_to_le32(sg_dma_address(sg) +
650 if (remainder > BAM_FIFO_SIZE) {
651 desc->size = cpu_to_le16(BAM_FIFO_SIZE);
652 remainder -= BAM_FIFO_SIZE;
653 curr_offset += BAM_FIFO_SIZE;
655 desc->size = cpu_to_le16(remainder);
659 async_desc->length += le16_to_cpu(desc->size);
661 } while (remainder > 0);
664 return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
668 * bam_dma_terminate_all - terminate all transactions on a channel
669 * @chan: bam dma channel
671 * Dequeues and frees all transactions
672 * No callbacks are done
675 static int bam_dma_terminate_all(struct dma_chan *chan)
677 struct bam_chan *bchan = to_bam_chan(chan);
678 struct bam_async_desc *async_desc, *tmp;
682 /* remove all transactions, including active transaction */
683 spin_lock_irqsave(&bchan->vc.lock, flag);
685 * If we have transactions queued, then some might be committed to the
686 * hardware in the desc fifo. The only way to reset the desc fifo is
687 * to do a hardware reset (either by pipe or the entire block).
688 * bam_chan_init_hw() will trigger a pipe reset, and also reinit the
689 * pipe. If the pipe is left disabled (default state after pipe reset)
690 * and is accessed by a connected hardware engine, a fatal error in
691 * the BAM will occur. There is a small window where this could happen
692 * with bam_chan_init_hw(), but it is assumed that the caller has
693 * stopped activity on any attached hardware engine. Make sure to do
694 * this first so that the BAM hardware doesn't cause memory corruption
695 * by accessing freed resources.
697 if (!list_empty(&bchan->desc_list)) {
698 async_desc = list_first_entry(&bchan->desc_list,
699 struct bam_async_desc, desc_node);
700 bam_chan_init_hw(bchan, async_desc->dir);
703 list_for_each_entry_safe(async_desc, tmp,
704 &bchan->desc_list, desc_node) {
705 list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
706 list_del(&async_desc->desc_node);
709 vchan_get_all_descriptors(&bchan->vc, &head);
710 spin_unlock_irqrestore(&bchan->vc.lock, flag);
712 vchan_dma_desc_free_list(&bchan->vc, &head);
718 * bam_pause - Pause DMA channel
722 static int bam_pause(struct dma_chan *chan)
724 struct bam_chan *bchan = to_bam_chan(chan);
725 struct bam_device *bdev = bchan->bdev;
729 ret = pm_runtime_get_sync(bdev->dev);
733 spin_lock_irqsave(&bchan->vc.lock, flag);
734 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
736 spin_unlock_irqrestore(&bchan->vc.lock, flag);
737 pm_runtime_mark_last_busy(bdev->dev);
738 pm_runtime_put_autosuspend(bdev->dev);
744 * bam_resume - Resume DMA channel operations
748 static int bam_resume(struct dma_chan *chan)
750 struct bam_chan *bchan = to_bam_chan(chan);
751 struct bam_device *bdev = bchan->bdev;
755 ret = pm_runtime_get_sync(bdev->dev);
759 spin_lock_irqsave(&bchan->vc.lock, flag);
760 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
762 spin_unlock_irqrestore(&bchan->vc.lock, flag);
763 pm_runtime_mark_last_busy(bdev->dev);
764 pm_runtime_put_autosuspend(bdev->dev);
770 * process_channel_irqs - processes the channel interrupts
771 * @bdev: bam controller
773 * This function processes the channel interrupts
776 static u32 process_channel_irqs(struct bam_device *bdev)
778 u32 i, srcs, pipe_stts, offset, avail;
780 struct bam_async_desc *async_desc, *tmp;
782 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
784 /* return early if no pipe/channel interrupts are present */
788 for (i = 0; i < bdev->num_channels; i++) {
789 struct bam_chan *bchan = &bdev->channels[i];
791 if (!(srcs & BIT(i)))
795 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
797 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
799 spin_lock_irqsave(&bchan->vc.lock, flags);
801 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
803 offset /= sizeof(struct bam_desc_hw);
805 /* Number of bytes available to read */
806 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
808 if (offset < bchan->head)
811 list_for_each_entry_safe(async_desc, tmp,
812 &bchan->desc_list, desc_node) {
813 /* Not enough data to read */
814 if (avail < async_desc->xfer_len)
818 bchan->head += async_desc->xfer_len;
819 bchan->head %= MAX_DESCRIPTORS;
821 async_desc->num_desc -= async_desc->xfer_len;
822 async_desc->curr_desc += async_desc->xfer_len;
823 avail -= async_desc->xfer_len;
826 * if complete, process cookie. Otherwise
827 * push back to front of desc_issued so that
828 * it gets restarted by the tasklet
830 if (!async_desc->num_desc) {
831 vchan_cookie_complete(&async_desc->vd);
833 list_add(&async_desc->vd.node,
834 &bchan->vc.desc_issued);
836 list_del(&async_desc->desc_node);
839 spin_unlock_irqrestore(&bchan->vc.lock, flags);
846 * bam_dma_irq - irq handler for bam controller
847 * @irq: IRQ of interrupt
848 * @data: callback data
850 * IRQ handler for the bam controller
852 static irqreturn_t bam_dma_irq(int irq, void *data)
854 struct bam_device *bdev = data;
855 u32 clr_mask = 0, srcs = 0;
858 srcs |= process_channel_irqs(bdev);
860 /* kick off tasklet to start next dma transfer */
862 tasklet_schedule(&bdev->task);
864 ret = pm_runtime_get_sync(bdev->dev);
868 if (srcs & BAM_IRQ) {
869 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
872 * don't allow reorder of the various accesses to the BAM
877 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
880 pm_runtime_mark_last_busy(bdev->dev);
881 pm_runtime_put_autosuspend(bdev->dev);
887 * bam_tx_status - returns status of transaction
889 * @cookie: transaction cookie
890 * @txstate: DMA transaction state
892 * Return status of dma transaction
894 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
895 struct dma_tx_state *txstate)
897 struct bam_chan *bchan = to_bam_chan(chan);
898 struct bam_async_desc *async_desc;
899 struct virt_dma_desc *vd;
905 ret = dma_cookie_status(chan, cookie, txstate);
906 if (ret == DMA_COMPLETE)
910 return bchan->paused ? DMA_PAUSED : ret;
912 spin_lock_irqsave(&bchan->vc.lock, flags);
913 vd = vchan_find_desc(&bchan->vc, cookie);
915 residue = container_of(vd, struct bam_async_desc, vd)->length;
917 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
918 if (async_desc->vd.tx.cookie != cookie)
921 for (i = 0; i < async_desc->num_desc; i++)
922 residue += le16_to_cpu(
923 async_desc->curr_desc[i].size);
927 spin_unlock_irqrestore(&bchan->vc.lock, flags);
929 dma_set_residue(txstate, residue);
931 if (ret == DMA_IN_PROGRESS && bchan->paused)
938 * bam_apply_new_config
939 * @bchan: bam dma channel
940 * @dir: DMA direction
942 static void bam_apply_new_config(struct bam_chan *bchan,
943 enum dma_transfer_direction dir)
945 struct bam_device *bdev = bchan->bdev;
948 if (!bdev->controlled_remotely) {
949 if (dir == DMA_DEV_TO_MEM)
950 maxburst = bchan->slave.src_maxburst;
952 maxburst = bchan->slave.dst_maxburst;
954 writel_relaxed(maxburst,
955 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
958 bchan->reconfigure = 0;
962 * bam_start_dma - start next transaction
963 * @bchan: bam dma channel
965 static void bam_start_dma(struct bam_chan *bchan)
967 struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
968 struct bam_device *bdev = bchan->bdev;
969 struct bam_async_desc *async_desc = NULL;
970 struct bam_desc_hw *desc;
971 struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
972 sizeof(struct bam_desc_hw));
975 struct dmaengine_desc_callback cb;
977 lockdep_assert_held(&bchan->vc.lock);
982 ret = pm_runtime_get_sync(bdev->dev);
986 while (vd && !IS_BUSY(bchan)) {
989 async_desc = container_of(vd, struct bam_async_desc, vd);
991 /* on first use, initialize the channel hardware */
992 if (!bchan->initialized)
993 bam_chan_init_hw(bchan, async_desc->dir);
995 /* apply new slave config changes, if necessary */
996 if (bchan->reconfigure)
997 bam_apply_new_config(bchan, async_desc->dir);
999 desc = async_desc->curr_desc;
1000 avail = CIRC_SPACE(bchan->tail, bchan->head,
1001 MAX_DESCRIPTORS + 1);
1003 if (async_desc->num_desc > avail)
1004 async_desc->xfer_len = avail;
1006 async_desc->xfer_len = async_desc->num_desc;
1008 /* set any special flags on the last descriptor */
1009 if (async_desc->num_desc == async_desc->xfer_len)
1010 desc[async_desc->xfer_len - 1].flags |=
1011 cpu_to_le16(async_desc->flags);
1013 vd = vchan_next_desc(&bchan->vc);
1015 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
1018 * An interrupt is generated at this desc, if
1020 * - No more descriptors to add.
1021 * - If a callback completion was requested for this DESC,
1022 * In this case, BAM will deliver the completion callback
1023 * for this desc and continue processing the next desc.
1025 if (((avail <= async_desc->xfer_len) || !vd ||
1026 dmaengine_desc_callback_valid(&cb)) &&
1027 !(async_desc->flags & DESC_FLAG_EOT))
1028 desc[async_desc->xfer_len - 1].flags |=
1029 cpu_to_le16(DESC_FLAG_INT);
1031 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
1032 u32 partial = MAX_DESCRIPTORS - bchan->tail;
1034 memcpy(&fifo[bchan->tail], desc,
1035 partial * sizeof(struct bam_desc_hw));
1036 memcpy(fifo, &desc[partial],
1037 (async_desc->xfer_len - partial) *
1038 sizeof(struct bam_desc_hw));
1040 memcpy(&fifo[bchan->tail], desc,
1041 async_desc->xfer_len *
1042 sizeof(struct bam_desc_hw));
1045 bchan->tail += async_desc->xfer_len;
1046 bchan->tail %= MAX_DESCRIPTORS;
1047 list_add_tail(&async_desc->desc_node, &bchan->desc_list);
1050 /* ensure descriptor writes and dma start not reordered */
1052 writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
1053 bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
1055 pm_runtime_mark_last_busy(bdev->dev);
1056 pm_runtime_put_autosuspend(bdev->dev);
1060 * dma_tasklet - DMA IRQ tasklet
1061 * @t: tasklet argument (bam controller structure)
1063 * Sets up next DMA operation and then processes all completed transactions
1065 static void dma_tasklet(struct tasklet_struct *t)
1067 struct bam_device *bdev = from_tasklet(bdev, t, task);
1068 struct bam_chan *bchan;
1069 unsigned long flags;
1072 /* go through the channels and kick off transactions */
1073 for (i = 0; i < bdev->num_channels; i++) {
1074 bchan = &bdev->channels[i];
1075 spin_lock_irqsave(&bchan->vc.lock, flags);
1077 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
1078 bam_start_dma(bchan);
1079 spin_unlock_irqrestore(&bchan->vc.lock, flags);
1085 * bam_issue_pending - starts pending transactions
1086 * @chan: dma channel
1088 * Calls tasklet directly which in turn starts any pending transactions
1090 static void bam_issue_pending(struct dma_chan *chan)
1092 struct bam_chan *bchan = to_bam_chan(chan);
1093 unsigned long flags;
1095 spin_lock_irqsave(&bchan->vc.lock, flags);
1097 /* if work pending and idle, start a transaction */
1098 if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
1099 bam_start_dma(bchan);
1101 spin_unlock_irqrestore(&bchan->vc.lock, flags);
1105 * bam_dma_free_desc - free descriptor memory
1106 * @vd: virtual descriptor
1109 static void bam_dma_free_desc(struct virt_dma_desc *vd)
1111 struct bam_async_desc *async_desc = container_of(vd,
1112 struct bam_async_desc, vd);
1117 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
1120 struct bam_device *bdev = container_of(of->of_dma_data,
1121 struct bam_device, common);
1122 unsigned int request;
1124 if (dma_spec->args_count != 1)
1127 request = dma_spec->args[0];
1128 if (request >= bdev->num_channels)
1131 return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
1138 * Initialization helper for global bam registers
1140 static int bam_init(struct bam_device *bdev)
1144 /* read revision and configuration information */
1145 if (!bdev->num_ees) {
1146 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
1147 bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
1150 /* check that configured EE is within range */
1151 if (bdev->ee >= bdev->num_ees)
1154 if (!bdev->num_channels) {
1155 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
1156 bdev->num_channels = val & BAM_NUM_PIPES_MASK;
1159 if (bdev->controlled_remotely)
1163 /* after reset all pipes are disabled and idle */
1164 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
1166 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1168 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1170 /* make sure previous stores are visible before enabling BAM */
1175 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1177 /* set descriptor threshhold, start with 4 bytes */
1178 writel_relaxed(DEFAULT_CNT_THRSHLD,
1179 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1181 /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
1182 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
1184 /* enable irqs for errors */
1185 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
1186 bam_addr(bdev, 0, BAM_IRQ_EN));
1188 /* unmask global bam interrupt */
1189 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1194 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1200 vchan_init(&bchan->vc, &bdev->common);
1201 bchan->vc.desc_free = bam_dma_free_desc;
1202 INIT_LIST_HEAD(&bchan->desc_list);
1205 static const struct of_device_id bam_of_match[] = {
1206 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1207 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1208 { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
1212 MODULE_DEVICE_TABLE(of, bam_of_match);
1214 static int bam_dma_probe(struct platform_device *pdev)
1216 struct bam_device *bdev;
1217 const struct of_device_id *match;
1218 struct resource *iores;
1221 bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1225 bdev->dev = &pdev->dev;
1227 match = of_match_node(bam_of_match, pdev->dev.of_node);
1229 dev_err(&pdev->dev, "Unsupported BAM module\n");
1233 bdev->layout = match->data;
1235 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1237 if (IS_ERR(bdev->regs))
1238 return PTR_ERR(bdev->regs);
1240 bdev->irq = platform_get_irq(pdev, 0);
1244 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1246 dev_err(bdev->dev, "Execution environment unspecified\n");
1250 bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node,
1251 "qcom,controlled-remotely");
1253 if (bdev->controlled_remotely) {
1254 ret = of_property_read_u32(pdev->dev.of_node, "num-channels",
1255 &bdev->num_channels);
1257 dev_err(bdev->dev, "num-channels unspecified in dt\n");
1259 ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-ees",
1262 dev_err(bdev->dev, "num-ees unspecified in dt\n");
1265 if (bdev->controlled_remotely)
1266 bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk");
1268 bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1270 if (IS_ERR(bdev->bamclk))
1271 return PTR_ERR(bdev->bamclk);
1273 ret = clk_prepare_enable(bdev->bamclk);
1275 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1279 ret = bam_init(bdev);
1281 goto err_disable_clk;
1283 tasklet_setup(&bdev->task, dma_tasklet);
1285 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1286 sizeof(*bdev->channels), GFP_KERNEL);
1288 if (!bdev->channels) {
1290 goto err_tasklet_kill;
1293 /* allocate and initialize channels */
1294 INIT_LIST_HEAD(&bdev->common.channels);
1296 for (i = 0; i < bdev->num_channels; i++)
1297 bam_channel_init(bdev, &bdev->channels[i], i);
1299 ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1300 IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1302 goto err_bam_channel_exit;
1304 /* set max dma segment size */
1305 bdev->common.dev = bdev->dev;
1306 ret = dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
1308 dev_err(bdev->dev, "cannot set maximum segment size\n");
1309 goto err_bam_channel_exit;
1312 platform_set_drvdata(pdev, bdev);
1314 /* set capabilities */
1315 dma_cap_zero(bdev->common.cap_mask);
1316 dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1318 /* initialize dmaengine apis */
1319 bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1320 bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1321 bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1322 bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1323 bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1324 bdev->common.device_free_chan_resources = bam_free_chan;
1325 bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1326 bdev->common.device_config = bam_slave_config;
1327 bdev->common.device_pause = bam_pause;
1328 bdev->common.device_resume = bam_resume;
1329 bdev->common.device_terminate_all = bam_dma_terminate_all;
1330 bdev->common.device_issue_pending = bam_issue_pending;
1331 bdev->common.device_tx_status = bam_tx_status;
1332 bdev->common.dev = bdev->dev;
1334 ret = dma_async_device_register(&bdev->common);
1336 dev_err(bdev->dev, "failed to register dma async device\n");
1337 goto err_bam_channel_exit;
1340 ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1343 goto err_unregister_dma;
1345 pm_runtime_irq_safe(&pdev->dev);
1346 pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY);
1347 pm_runtime_use_autosuspend(&pdev->dev);
1348 pm_runtime_mark_last_busy(&pdev->dev);
1349 pm_runtime_set_active(&pdev->dev);
1350 pm_runtime_enable(&pdev->dev);
1355 dma_async_device_unregister(&bdev->common);
1356 err_bam_channel_exit:
1357 for (i = 0; i < bdev->num_channels; i++)
1358 tasklet_kill(&bdev->channels[i].vc.task);
1360 tasklet_kill(&bdev->task);
1362 clk_disable_unprepare(bdev->bamclk);
1367 static int bam_dma_remove(struct platform_device *pdev)
1369 struct bam_device *bdev = platform_get_drvdata(pdev);
1372 pm_runtime_force_suspend(&pdev->dev);
1374 of_dma_controller_free(pdev->dev.of_node);
1375 dma_async_device_unregister(&bdev->common);
1377 /* mask all interrupts for this execution environment */
1378 writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1380 devm_free_irq(bdev->dev, bdev->irq, bdev);
1382 for (i = 0; i < bdev->num_channels; i++) {
1383 bam_dma_terminate_all(&bdev->channels[i].vc.chan);
1384 tasklet_kill(&bdev->channels[i].vc.task);
1386 if (!bdev->channels[i].fifo_virt)
1389 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
1390 bdev->channels[i].fifo_virt,
1391 bdev->channels[i].fifo_phys);
1394 tasklet_kill(&bdev->task);
1396 clk_disable_unprepare(bdev->bamclk);
1401 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev)
1403 struct bam_device *bdev = dev_get_drvdata(dev);
1405 clk_disable(bdev->bamclk);
1410 static int __maybe_unused bam_dma_runtime_resume(struct device *dev)
1412 struct bam_device *bdev = dev_get_drvdata(dev);
1415 ret = clk_enable(bdev->bamclk);
1417 dev_err(dev, "clk_enable failed: %d\n", ret);
1424 static int __maybe_unused bam_dma_suspend(struct device *dev)
1426 struct bam_device *bdev = dev_get_drvdata(dev);
1428 pm_runtime_force_suspend(dev);
1429 clk_unprepare(bdev->bamclk);
1434 static int __maybe_unused bam_dma_resume(struct device *dev)
1436 struct bam_device *bdev = dev_get_drvdata(dev);
1439 ret = clk_prepare(bdev->bamclk);
1443 pm_runtime_force_resume(dev);
1448 static const struct dev_pm_ops bam_dma_pm_ops = {
1449 SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume)
1450 SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume,
1454 static struct platform_driver bam_dma_driver = {
1455 .probe = bam_dma_probe,
1456 .remove = bam_dma_remove,
1458 .name = "bam-dma-engine",
1459 .pm = &bam_dma_pm_ops,
1460 .of_match_table = bam_of_match,
1464 module_platform_driver(bam_dma_driver);
1466 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1467 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1468 MODULE_LICENSE("GPL v2");